1 /* 2 * Copyright (c) 2022 FuZhou Lockzhiner Electronic Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef __RK2206_USB_H 17 #define __RK2206_USB_H 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 /****************************************************************************************/ 22 /* */ 23 /* Module Structure Section */ 24 /* */ 25 /****************************************************************************************/ 26 #ifndef __ASSEMBLY__ 27 /* USB_OTG_CORE Register Structure Define */ 28 struct USB_GLOBAL_REG { 29 __IO uint32_t GOTGCTL; /* Address Offset: 0x0000 */ 30 __IO uint32_t GOTGINT; /* Address Offset: 0x0004 */ 31 __IO uint32_t GAHBCFG; /* Address Offset: 0x0008 */ 32 __IO uint32_t GUSBCFG; /* Address Offset: 0x000C */ 33 __IO uint32_t GRSTCTL; /* Address Offset: 0x0010 */ 34 __IO uint32_t GINTSTS; /* Address Offset: 0x0014 */ 35 __IO uint32_t GINTMSK; /* Address Offset: 0x0018 */ 36 __IO uint32_t GRXSTSR; /* Address Offset: 0x001C */ 37 __IO uint32_t GRXSTSP; /* Address Offset: 0x0020 */ 38 __IO uint32_t GRXFSIZ; /* Address Offset: 0x0024 */ 39 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /* Address Offset: 0x0028 */ 40 __IO uint32_t HNPTXSTS; /* Address Offset: 0x002C */ 41 uint32_t RESERVED0[2]; /* Address Offset: 0x0030 */ 42 __IO uint32_t GGPIO; /* Address Offset: 0x0038 */ 43 __IO uint32_t GUID; /* Address Offset: 0x003C */ 44 __O uint32_t GSNPSID; /* Address Offset: 0x0040 */ 45 __O uint32_t GHWCFG1; /* Address Offset: 0x0044 */ 46 __O uint32_t GHWCFG2; /* Address Offset: 0x0048 */ 47 __O uint32_t GHWCFG3; /* Address Offset: 0x004C */ 48 __O uint32_t GHWCFG4; /* Address Offset: 0x0050 */ 49 __IO uint32_t GLPMCFG; /* Address Offset: 0x0054 */ 50 __IO uint32_t GPWRDN; /* Address Offset: 0x0058 */ 51 __IO uint32_t GDFIFOCFG; /* Address Offset: 0x005C */ 52 __IO uint32_t GADPCTL; /* Address Offset: 0x0060 */ 53 uint32_t RESERVED1[39]; /* Address Offset: 0x0064 */ 54 __IO uint32_t HPTXFSIZ; /* Address Offset: 0x0100 */ 55 __IO uint32_t DIEPTXF[0x0F]; /* Address Offset: 0x0104 */ 56 }; 57 /* USB_OTG_DEV Register Structure Define */ 58 struct USB_DEVICE_REG { 59 __IO uint32_t DCFG; /* Address Offset: 0x0800 */ 60 __IO uint32_t DCTL; /* Address Offset: 0x0804 */ 61 __IO uint32_t DSTS; /* Address Offset: 0x0808 */ 62 uint32_t RESERVED0; /* Address Offset: 0x080C */ 63 __IO uint32_t DIEPMSK; /* Address Offset: 0x0810 */ 64 __IO uint32_t DOEPMSK; /* Address Offset: 0x0814 */ 65 __IO uint32_t DAINT; /* Address Offset: 0x0818 */ 66 __IO uint32_t DAINTMSK; /* Address Offset: 0x081C */ 67 uint32_t RESERVED1[2]; /* Address Offset: 0x0820 */ 68 __IO uint32_t DVBUSDIS; /* Address Offset: 0x0828 */ 69 __IO uint32_t DVBUSPULSE; /* Address Offset: 0x082C */ 70 __IO uint32_t DTHRCTL; /* Address Offset: 0x0830 */ 71 __IO uint32_t DIEPEMPMSK; /* Address Offset: 0x0834 */ 72 __IO uint32_t DEACHINT; /* Address Offset: 0x0838 */ 73 __IO uint32_t DEACHMSK; /* Address Offset: 0x083C */ 74 uint32_t RESERVED2; /* Address Offset: 0x0840 */ 75 __IO uint32_t DINEP1MSK; /* Address Offset: 0x0844 */ 76 uint32_t RESERVED3[15]; /* Address Offset: 0x0848 */ 77 __IO uint32_t DOUTEP1MSK; /* Address Offset: 0x0884 */ 78 }; 79 /* USB_OTG_DEV_IN_ENDPOINT Register Structure Define */ 80 struct USB_IN_EP_REG { 81 __IO uint32_t DIEPCTL; /* Address Offset: 900h + (ep_num * 20h) + 00h */ 82 uint32_t RESERVED0; /* Address Offset: 900h + (ep_num * 20h) + 04h */ 83 __IO uint32_t DIEPINT; /* Address Offset: 900h + (ep_num * 20h) + 08h */ 84 uint32_t RESERVED1; /* Address Offset: 900h + (ep_num * 20h) + 0Ch */ 85 __IO uint32_t DIEPTSIZ; /* Address Offset: 900h + (ep_num * 20h) + 10h */ 86 __IO uint32_t DIEPDMA; /* Address Offset: 900h + (ep_num * 20h) + 14h */ 87 __IO uint32_t DTXFSTS; /* Address Offset: 900h + (ep_num * 20h) + 18h */ 88 uint32_t RESERVED2; /* Address Offset: 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ 89 }; 90 /* USB_OTG_DEV_OUT_ENDPOINT Register Structure Define */ 91 struct USB_OUT_EP_REG { 92 __IO uint32_t DOEPCTL; /* Address Offset: B00h + (ep_num * 20h) + 00h */ 93 uint32_t RESERVED0; /* Address Offset: B00h + (ep_num * 20h) + 04h */ 94 __IO uint32_t DOEPINT; /* Address Offset: B00h + (ep_num * 20h) + 08h */ 95 uint32_t RESERVED1; /* Address Offset: B00h + (ep_num * 20h) + 0Ch */ 96 __IO uint32_t DOEPTSIZ; /* Address Offset: B00h + (ep_num * 20h) + 10h */ 97 __IO uint32_t DOEPDMA; /* Address Offset: B00h + (ep_num * 20h) + 14h */ 98 uint32_t RESERVED2[2]; /* Address Offset: B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ 99 }; 100 /* USB_OTG_HOST Register Structure Define */ 101 struct USB_HOST_REG { 102 __IO uint32_t HCFG; /* Address Offset: 0x0400 */ 103 __IO uint32_t HFIR; /* Address Offset: 0x0404 */ 104 __IO uint32_t HFNUM; /* Address Offset: 0x0408 */ 105 uint32_t RESERVED0; /* Address Offset: 0x040C */ 106 __IO uint32_t HPTXSTS; /* Address Offset: 0x0410 */ 107 __IO uint32_t HAINT; /* Address Offset: 0x0414 */ 108 __IO uint32_t HAINTMSK; /* Address Offset: 0x0418 */ 109 }; 110 /* USB_OTG_HOST_CHANNEL Register Structure Define */ 111 struct USB_HOST_CH_REG { 112 __IO uint32_t HCCHAR; /* Address Offset: 0x0500 */ 113 __IO uint32_t HCSPLT; /* Address Offset: 0x0504 */ 114 __IO uint32_t HCINT; /* Address Offset: 0x0508 */ 115 __IO uint32_t HCINTMSK; /* Address Offset: 0x050C */ 116 __IO uint32_t HCTSIZ; /* Address Offset: 0x0510 */ 117 __IO uint32_t HCDMA; /* Address Offset: 0x0514 */ 118 uint32_t RESERVED0[2]; /* Address Offset: 0x0518 */ 119 }; 120 #endif /* __ASSEMBLY__ */ 121 /****************************************************************************************/ 122 /* */ 123 /* Module Variable Section */ 124 /* */ 125 /****************************************************************************************/ 126 /* Module Variable Define */ 127 #define USB ((struct USB_GLOBAL_REG *) USB_BASE) 128 129 #define IS_PCD_INSTANCE(instance) ((instance) == USB) 130 #define IS_HCD_INSTANCE(instance) ((instance) == USB) 131 /****************************************************************************************/ 132 /* */ 133 /* Register Bitmap Section */ 134 /* */ 135 /****************************************************************************************/ 136 /***************************************USB_OTG_GOTGCTL*********************************/ 137 #define USB_OTG_GOTGCTL_SRQSCS_SHIFT (0U) 138 #define USB_OTG_GOTGCTL_SRQSCS_MASK (0x1U << USB_OTG_GOTGCTL_SRQSCS_SHIFT) /* 0x00000001 */ 139 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_MASK /* Session request success */ 140 #define USB_OTG_GOTGCTL_SRQ_SHIFT (1U) 141 #define USB_OTG_GOTGCTL_SRQ_MASK (0x1U << USB_OTG_GOTGCTL_SRQ_SHIFT) /* 0x00000002 */ 142 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_MASK /* Session request */ 143 #define USB_OTG_GOTGCTL_VBVALOEN_SHIFT (2U) 144 #define USB_OTG_GOTGCTL_VBVALOEN_MASK (0x1U << USB_OTG_GOTGCTL_VBVALOEN_SHIFT) /* 0x00000004 */ 145 #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_MASK /* VBUS valid override enable */ 146 #define USB_OTG_GOTGCTL_VBVALOVAL_SHIFT (3U) 147 #define USB_OTG_GOTGCTL_VBVALOVAL_MASK (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_SHIFT) /* 0x00000008 */ 148 #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_MASK /* VBUS valid override value */ 149 #define USB_OTG_GOTGCTL_AVALOEN_SHIFT (4U) 150 #define USB_OTG_GOTGCTL_AVALOEN_MASK (0x1U << USB_OTG_GOTGCTL_AVALOEN_SHIFT) /* 0x00000010 */ 151 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_MASK 152 #define USB_OTG_GOTGCTL_AVALOVAL_SHIFT (5U) 153 #define USB_OTG_GOTGCTL_AVALOVAL_MASK (0x1U << USB_OTG_GOTGCTL_AVALOVAL_SHIFT) /* 0x00000020 */ 154 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_MASK 155 #define USB_OTG_GOTGCTL_BVALOEN_SHIFT (6U) 156 #define USB_OTG_GOTGCTL_BVALOEN_MASK (0x1U << USB_OTG_GOTGCTL_BVALOEN_SHIFT) /* 0x00000040 */ 157 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_MASK 158 #define USB_OTG_GOTGCTL_BVALOVAL_SHIFT (7U) 159 #define USB_OTG_GOTGCTL_BVALOVAL_MASK (0x1U << USB_OTG_GOTGCTL_BVALOVAL_SHIFT) /* 0x00000080 */ 160 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_MASK 161 #define USB_OTG_GOTGCTL_HNGSCS_SHIFT (8U) 162 #define USB_OTG_GOTGCTL_HNGSCS_MASK (0x1U << USB_OTG_GOTGCTL_HNGSCS_SHIFT) /* 0x00000100 */ 163 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_MASK /* Host set HNP enable */ 164 #define USB_OTG_GOTGCTL_HNPRQ_SHIFT (9U) 165 #define USB_OTG_GOTGCTL_HNPRQ_MASK (0x1U << USB_OTG_GOTGCTL_HNPRQ_SHIFT) /* 0x00000200 */ 166 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_MASK /* HNP request */ 167 #define USB_OTG_GOTGCTL_HSHNPEN_SHIFT (10U) 168 #define USB_OTG_GOTGCTL_HSHNPEN_MASK (0x1U << USB_OTG_GOTGCTL_HSHNPEN_SHIFT) /* 0x00000400 */ 169 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_MASK /* Host set HNP enable */ 170 #define USB_OTG_GOTGCTL_DHNPEN_SHIFT (11U) 171 #define USB_OTG_GOTGCTL_DHNPEN_MASK (0x1U << USB_OTG_GOTGCTL_DHNPEN_SHIFT) /* 0x00000800 */ 172 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_MASK /* Device HNP enabled */ 173 #define USB_OTG_GOTGCTL_EHEN_SHIFT (12U) 174 #define USB_OTG_GOTGCTL_EHEN_MASK (0x1U << USB_OTG_GOTGCTL_EHEN_SHIFT) /* 0x00001000 */ 175 #define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_MASK /* Embedded host enable */ 176 #define USB_OTG_GOTGCTL_CIDSTS_SHIFT (16) 177 #define USB_OTG_GOTGCTL_CIDSTS_MASK (0x1U << USB_OTG_GOTGCTL_CIDSTS_SHIFT) /* 0x00010000 */ 178 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_MASK /* Connector ID status */ 179 #define USB_OTG_GOTGCTL_DBCT_SHIFT (17U) 180 #define USB_OTG_GOTGCTL_DBCT_MASK (0x1U << USB_OTG_GOTGCTL_DBCT_SHIFT) /* 0x00020000 */ 181 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_MASK /* Long/short debounce time */ 182 #define USB_OTG_GOTGCTL_ASVLD_SHIFT (18U) 183 #define USB_OTG_GOTGCTL_ASVLD_MASK (0x1U << USB_OTG_GOTGCTL_ASVLD_SHIFT) /* 0x00040000 */ 184 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_MASK /* A-session valid */ 185 #define USB_OTG_GOTGCTL_BSESVLD_SHIFT (19U) 186 #define USB_OTG_GOTGCTL_BSESVLD_MASK (0x1U << USB_OTG_GOTGCTL_BSESVLD_SHIFT) /* 0x00080000 */ 187 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_MASK /* B-session valid */ 188 #define USB_OTG_GOTGCTL_OTGVER_SHIFT (20U) 189 #define USB_OTG_GOTGCTL_OTGVER_MASK (0x1U << USB_OTG_GOTGCTL_OTGVER_SHIFT) /* 0x00100000 */ 190 #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_MASK /* OTG version */ 191 /******************** Bit definition for USB_OTG_GOTGINT register ********************/ 192 #define USB_OTG_GOTGINT_SEDET_SHIFT (2U) 193 #define USB_OTG_GOTGINT_SEDET_MASK (0x1U << USB_OTG_GOTGINT_SEDET_SHIFT) /* 0x00000004 */ 194 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_MASK /* Session end detected */ 195 #define USB_OTG_GOTGINT_SRSSCHG_SHIFT (8U) 196 #define USB_OTG_GOTGINT_SRSSCHG_MASK (0x1U << USB_OTG_GOTGINT_SRSSCHG_SHIFT) /* 0x00000100 */ 197 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_MASK 198 #define USB_OTG_GOTGINT_HNSSCHG_SHIFT (9U) 199 #define USB_OTG_GOTGINT_HNSSCHG_MASK (0x1U << USB_OTG_GOTGINT_HNSSCHG_SHIFT) /* 0x00000200 */ 200 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_MASK 201 #define USB_OTG_GOTGINT_HNGDET_SHIFT (17U) 202 #define USB_OTG_GOTGINT_HNGDET_MASK (0x1U << USB_OTG_GOTGINT_HNGDET_SHIFT) /* 0x00020000 */ 203 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_MASK /* Host negotiation detected */ 204 #define USB_OTG_GOTGINT_ADTOCHG_SHIFT (18U) 205 #define USB_OTG_GOTGINT_ADTOCHG_MASK (0x1U << USB_OTG_GOTGINT_ADTOCHG_SHIFT) /* 0x00040000 */ 206 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_MASK /* A-device timeout change */ 207 #define USB_OTG_GOTGINT_DBCDNE_SHIFT (19U) 208 #define USB_OTG_GOTGINT_DBCDNE_MASK (0x1U << USB_OTG_GOTGINT_DBCDNE_SHIFT) /* 0x00080000 */ 209 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_MASK /* Debounce done */ 210 #define USB_OTG_GOTGINT_IDCHNG_SHIFT (20U) 211 #define USB_OTG_GOTGINT_IDCHNG_MASK (0x1U << USB_OTG_GOTGINT_IDCHNG_SHIFT) /* 0x00100000 */ 212 #define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_MASK /* Change in ID pin input value */ 213 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ 214 #define USB_OTG_GAHBCFG_GINT_SHIFT (0U) 215 #define USB_OTG_GAHBCFG_GINT_MASK (0x1U << USB_OTG_GAHBCFG_GINT_SHIFT) /* 0x00000001 */ 216 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_MASK /* Global interrupt mask */ 217 #define USB_OTG_GAHBCFG_HBSTLEN_SHIFT (1U) 218 #define USB_OTG_GAHBCFG_HBSTLEN_MASK (0xFU << USB_OTG_GAHBCFG_HBSTLEN_SHIFT) /* 0x0000001E */ 219 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_MASK /* Burst length/type */ 220 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_SHIFT) /* Single */ 221 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_SHIFT) /* INCR */ 222 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_SHIFT) /* INCR4 */ 223 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_SHIFT) /* INCR8 */ 224 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_SHIFT) /* INCR16 */ 225 #define USB_OTG_GAHBCFG_DMAEN_SHIFT (5U) 226 #define USB_OTG_GAHBCFG_DMAEN_MASK (0x1U << USB_OTG_GAHBCFG_DMAEN_SHIFT) /* 0x00000020 */ 227 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_MASK /* DMA enable */ 228 #define USB_OTG_GAHBCFG_TXFELVL_SHIFT (7U) 229 #define USB_OTG_GAHBCFG_TXFELVL_MASK (0x1U << USB_OTG_GAHBCFG_TXFELVL_SHIFT) /* 0x00000080 */ 230 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_MASK /* TxFIFO empty level */ 231 #define USB_OTG_GAHBCFG_PTXFELVL_SHIFT (8U) 232 #define USB_OTG_GAHBCFG_PTXFELVL_MASK (0x1U << USB_OTG_GAHBCFG_PTXFELVL_SHIFT) /* 0x00000100 */ 233 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_MASK /* Periodic TxFIFO empty level */ 234 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/ 235 #define USB_OTG_GUSBCFG_TOCAL_SHIFT (0U) 236 #define USB_OTG_GUSBCFG_TOCAL_MASK (0x7U << USB_OTG_GUSBCFG_TOCAL_SHIFT) /* 0x00000007 */ 237 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_MASK /* FS timeout calibration */ 238 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_SHIFT) /* 0x00000001 */ 239 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_SHIFT) /* 0x00000002 */ 240 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_SHIFT) /* 0x00000004 */ 241 #define USB_OTG_GUSBCFG_PHYIF_SHIFT (3U) 242 #define USB_OTG_GUSBCFG_PHYIF_MASK (0x1U << USB_OTG_GUSBCFG_PHYIF_SHIFT) /* 0x00000008 */ 243 #define USB_OTG_GUSBCFG_PHYIF USB_OTG_GUSBCFG_PHYIF_MASK /* PHY Interface (PHYIf) */ 244 #define USB_OTG_GUSBCFG_ULPI_UTMI_SEL_SHIFT (4U) 245 #define USB_OTG_GUSBCFG_ULPI_UTMI_SEL_MASK (0x1U << USB_OTG_GUSBCFG_ULPI_UTMI_SEL_SHIFT) /* 0x00000010 */ 246 #define USB_OTG_GUSBCFG_ULPI_UTMI_SEL USB_OTG_GUSBCFG_ULPI_UTMI_SEL_MASK 247 #define USB_OTG_GUSBCFG_PHYSEL_SHIFT (6U) 248 #define USB_OTG_GUSBCFG_PHYSEL_MASK (0x1U << USB_OTG_GUSBCFG_PHYSEL_SHIFT) /* 0x00000040 */ 249 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_MASK 250 #define USB_OTG_GUSBCFG_SRPCAP_SHIFT (8U) 251 #define USB_OTG_GUSBCFG_SRPCAP_MASK (0x1U << USB_OTG_GUSBCFG_SRPCAP_SHIFT) /* 0x00000100 */ 252 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_MASK /* SRP-capable */ 253 #define USB_OTG_GUSBCFG_HNPCAP_SHIFT (9U) 254 #define USB_OTG_GUSBCFG_HNPCAP_MASK (0x1U << USB_OTG_GUSBCFG_HNPCAP_SHIFT) /* 0x00000200 */ 255 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_MASK /* HNP-capable */ 256 #define USB_OTG_GUSBCFG_TRDT_SHIFT (10U) 257 #define USB_OTG_GUSBCFG_TRDT_MASK (0xFU << USB_OTG_GUSBCFG_TRDT_SHIFT) /* 0x00003C00 */ 258 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_MASK /* USB turnaround time */ 259 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_SHIFT) /* 0x00000400 */ 260 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_SHIFT) /* 0x00000800 */ 261 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_SHIFT) /* 0x00001000 */ 262 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_SHIFT) /* 0x00002000 */ 263 #define USB_OTG_GUSBCFG_PHYLPCS_SHIFT (15U) 264 #define USB_OTG_GUSBCFG_PHYLPCS_MASK (0x1U << USB_OTG_GUSBCFG_PHYLPCS_SHIFT) /* 0x00008000 */ 265 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_MASK /* PHY Low-power clock select */ 266 #define USB_OTG_GUSBCFG_ULPIFSLS_SHIFT (17U) 267 #define USB_OTG_GUSBCFG_ULPIFSLS_MASK (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_SHIFT) /* 0x00020000 */ 268 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_MASK /* ULPI FS/LS select */ 269 #define USB_OTG_GUSBCFG_ULPIAR_SHIFT (18U) 270 #define USB_OTG_GUSBCFG_ULPIAR_MASK (0x1U << USB_OTG_GUSBCFG_ULPIAR_SHIFT) /* 0x00040000 */ 271 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_MASK /* ULPI Auto-resume */ 272 #define USB_OTG_GUSBCFG_ULPICSM_SHIFT (19U) 273 #define USB_OTG_GUSBCFG_ULPICSM_MASK (0x1U << USB_OTG_GUSBCFG_ULPICSM_SHIFT) /* 0x00080000 */ 274 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_MASK /* ULPI Clock SuspendM */ 275 #define USB_OTG_GUSBCFG_ULPIEVBUSD_SHIFT (20U) 276 #define USB_OTG_GUSBCFG_ULPIEVBUSD_MASK (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_SHIFT) /* 0x00100000 */ 277 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_MASK /* ULPI External VBUS Drive */ 278 #define USB_OTG_GUSBCFG_ULPIEVBUSI_SHIFT (21U) 279 #define USB_OTG_GUSBCFG_ULPIEVBUSI_MASK (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_SHIFT) /* 0x00200000 */ 280 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_MASK /* ULPI external VBUS indicator */ 281 #define USB_OTG_GUSBCFG_TSDPS_SHIFT (22U) 282 #define USB_OTG_GUSBCFG_TSDPS_MASK (0x1U << USB_OTG_GUSBCFG_TSDPS_SHIFT) /* 0x00400000 */ 283 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_MASK /* TermSel DLine pulsing selection */ 284 #define USB_OTG_GUSBCFG_PCCI_SHIFT (23U) 285 #define USB_OTG_GUSBCFG_PCCI_MASK (0x1U << USB_OTG_GUSBCFG_PCCI_SHIFT) /* 0x00800000 */ 286 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_MASK /* Indicator complement */ 287 #define USB_OTG_GUSBCFG_PTCI_SHIFT (24U) 288 #define USB_OTG_GUSBCFG_PTCI_MASK (0x1U << USB_OTG_GUSBCFG_PTCI_SHIFT) /* 0x01000000 */ 289 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_MASK /* Indicator pass through */ 290 #define USB_OTG_GUSBCFG_ULPIIPD_SHIFT (25U) 291 #define USB_OTG_GUSBCFG_ULPIIPD_MASK (0x1U << USB_OTG_GUSBCFG_ULPIIPD_SHIFT) /* 0x02000000 */ 292 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_MASK /* ULPI interface protect disable */ 293 #define USB_OTG_GUSBCFG_FHMOD_SHIFT (29U) 294 #define USB_OTG_GUSBCFG_FHMOD_MASK (0x1U << USB_OTG_GUSBCFG_FHMOD_SHIFT) /* 0x20000000 */ 295 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_MASK /* Forced host mode */ 296 #define USB_OTG_GUSBCFG_FDMOD_SHIFT (30U) 297 #define USB_OTG_GUSBCFG_FDMOD_MASK (0x1U << USB_OTG_GUSBCFG_FDMOD_SHIFT) /* 0x40000000 */ 298 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_MASK /* Forced peripheral mode */ 299 #define USB_OTG_GUSBCFG_CTXPKT_SHIFT (31U) 300 #define USB_OTG_GUSBCFG_CTXPKT_MASK (0x1U << USB_OTG_GUSBCFG_CTXPKT_SHIFT) /* 0x80000000 */ 301 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_MASK /* Corrupt Tx packet */ 302 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/ 303 #define USB_OTG_GRSTCTL_CSRST_SHIFT (0U) 304 #define USB_OTG_GRSTCTL_CSRST_MASK (0x1U << USB_OTG_GRSTCTL_CSRST_SHIFT) /* 0x00000001 */ 305 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_MASK /* Core soft reset */ 306 #define USB_OTG_GRSTCTL_HSRST_SHIFT (1U) 307 #define USB_OTG_GRSTCTL_HSRST_MASK (0x1U << USB_OTG_GRSTCTL_HSRST_SHIFT) /* 0x00000002 */ 308 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_MASK /* HCLK soft reset */ 309 #define USB_OTG_GRSTCTL_FCRST_SHIFT (2U) 310 #define USB_OTG_GRSTCTL_FCRST_MASK (0x1U << USB_OTG_GRSTCTL_FCRST_SHIFT) /* 0x00000004 */ 311 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_MASK /* Host frame counter reset */ 312 #define USB_OTG_GRSTCTL_INTKNQFLSH_SHIFT (3U) 313 #define USB_OTG_GRSTCTL_INTKNQFLSH_MASK (0x1U << USB_OTG_GRSTCTL_INTKNQFLSH_SHIFT) /* 0x00000080 */ 314 #define USB_OTG_GRSTCTL_INTKNQFLSH USB_OTG_GRSTCTL_INTKNQFLSH_MASK /* INTknQ flush */ 315 #define USB_OTG_GRSTCTL_RXFFLSH_SHIFT (4U) 316 #define USB_OTG_GRSTCTL_RXFFLSH_MASK (0x1U << USB_OTG_GRSTCTL_RXFFLSH_SHIFT) /* 0x00000010 */ 317 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_MASK /* RxFIFO flush */ 318 #define USB_OTG_GRSTCTL_TXFFLSH_SHIFT (5U) 319 #define USB_OTG_GRSTCTL_TXFFLSH_MASK (0x1U << USB_OTG_GRSTCTL_TXFFLSH_SHIFT) /* 0x00000020 */ 320 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_MASK /* TxFIFO flush */ 321 #define USB_OTG_GRSTCTL_TXFNUM_SHIFT (6U) 322 #define USB_OTG_GRSTCTL_TXFNUM_MASK (0x1FU << USB_OTG_GRSTCTL_TXFNUM_SHIFT) /* 0x000007C0 */ 323 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_MASK /* TxFIFO number */ 324 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_SHIFT) /* 0x00000040 */ 325 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_SHIFT) /* 0x00000080 */ 326 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_SHIFT) /* 0x00000100 */ 327 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_SHIFT) /* 0x00000200 */ 328 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_SHIFT) /* 0x00000400 */ 329 #define USB_OTG_GRSTCTL_DMAREQ_SHIFT (30U) 330 #define USB_OTG_GRSTCTL_DMAREQ_MASK (0x1U << USB_OTG_GRSTCTL_DMAREQ_SHIFT) /* 0x40000000 */ 331 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_MASK /* DMA request signal */ 332 #define USB_OTG_GRSTCTL_AHBIDL_SHIFT (31U) 333 #define USB_OTG_GRSTCTL_AHBIDL_MASK (0x1U << USB_OTG_GRSTCTL_AHBIDL_SHIFT) /* 0x80000000 */ 334 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_MASK /* AHB master idle */ 335 /******************** Bit definition for USB_OTG_GINTSTS register ********************/ 336 #define USB_OTG_GINTSTS_CMOD_SHIFT (0U) 337 #define USB_OTG_GINTSTS_CMOD_MASK (0x1U << USB_OTG_GINTSTS_CMOD_SHIFT) /* 0x00000001 */ 338 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_MASK /* Current mode of operation */ 339 #define USB_OTG_GINTSTS_MMIS_SHIFT (1U) 340 #define USB_OTG_GINTSTS_MMIS_MASK (0x1U << USB_OTG_GINTSTS_MMIS_SHIFT) /* 0x00000002 */ 341 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_MASK /* Mode mismatch interrupt */ 342 #define USB_OTG_GINTSTS_OTGINT_SHIFT (2U) 343 #define USB_OTG_GINTSTS_OTGINT_MASK (0x1U << USB_OTG_GINTSTS_OTGINT_SHIFT) /* 0x00000004 */ 344 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_MASK /* OTG interrupt */ 345 #define USB_OTG_GINTSTS_SOF_SHIFT (3U) 346 #define USB_OTG_GINTSTS_SOF_MASK (0x1U << USB_OTG_GINTSTS_SOF_SHIFT) /* 0x00000008 */ 347 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_MASK /* Start of frame */ 348 #define USB_OTG_GINTSTS_RXFLVL_SHIFT (4U) 349 #define USB_OTG_GINTSTS_RXFLVL_MASK (0x1U << USB_OTG_GINTSTS_RXFLVL_SHIFT) /* 0x00000010 */ 350 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_MASK /* RxFIFO nonempty */ 351 #define USB_OTG_GINTSTS_NPTXFE_SHIFT (5U) 352 #define USB_OTG_GINTSTS_NPTXFE_MASK (0x1U << USB_OTG_GINTSTS_NPTXFE_SHIFT) /* 0x00000020 */ 353 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_MASK /* Nonperiodic TxFIFO empty */ 354 #define USB_OTG_GINTSTS_GINAKEFF_SHIFT (6U) 355 #define USB_OTG_GINTSTS_GINAKEFF_MASK (0x1U << USB_OTG_GINTSTS_GINAKEFF_SHIFT) /* 0x00000040 */ 356 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_MASK 357 #define USB_OTG_GINTSTS_BOUTNAKEFF_SHIFT (7U) 358 #define USB_OTG_GINTSTS_BOUTNAKEFF_MASK (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_SHIFT) /* 0x00000080 */ 359 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_MASK /* Global OUT NAK effective */ 360 #define USB_OTG_GINTSTS_ESUSP_SHIFT (10U) 361 #define USB_OTG_GINTSTS_ESUSP_MASK (0x1U << USB_OTG_GINTSTS_ESUSP_SHIFT) /* 0x00000400 */ 362 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_MASK /* Early suspend */ 363 #define USB_OTG_GINTSTS_USBSUSP_SHIFT (11U) 364 #define USB_OTG_GINTSTS_USBSUSP_MASK (0x1U << USB_OTG_GINTSTS_USBSUSP_SHIFT) /* 0x00000800 */ 365 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_MASK /* USB suspend */ 366 #define USB_OTG_GINTSTS_USBRST_SHIFT (12U) 367 #define USB_OTG_GINTSTS_USBRST_MASK (0x1U << USB_OTG_GINTSTS_USBRST_SHIFT) /* 0x00001000 */ 368 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_MASK /* USB reset */ 369 #define USB_OTG_GINTSTS_ENUMDNE_SHIFT (13U) 370 #define USB_OTG_GINTSTS_ENUMDNE_MASK (0x1U << USB_OTG_GINTSTS_ENUMDNE_SHIFT) /* 0x00002000 */ 371 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_MASK /* Enumeration done */ 372 #define USB_OTG_GINTSTS_ISOODRP_SHIFT (14U) 373 #define USB_OTG_GINTSTS_ISOODRP_MASK (0x1U << USB_OTG_GINTSTS_ISOODRP_SHIFT) /* 0x00004000 */ 374 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_MASK 375 #define USB_OTG_GINTSTS_EOPF_SHIFT (15U) 376 #define USB_OTG_GINTSTS_EOPF_MASK (0x1U << USB_OTG_GINTSTS_EOPF_SHIFT) /* 0x00008000 */ 377 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_MASK /* End of periodic frame interrupt */ 378 #define USB_OTG_GINTSTS_IEPINT_SHIFT (18U) 379 #define USB_OTG_GINTSTS_IEPINT_MASK (0x1U << USB_OTG_GINTSTS_IEPINT_SHIFT) /* 0x00040000 */ 380 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_MASK /* IN endpoint interrupt */ 381 #define USB_OTG_GINTSTS_OEPINT_SHIFT (19U) 382 #define USB_OTG_GINTSTS_OEPINT_MASK (0x1U << USB_OTG_GINTSTS_OEPINT_SHIFT) /* 0x00080000 */ 383 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_MASK /* OUT endpoint interrupt */ 384 #define USB_OTG_GINTSTS_IISOIXFR_SHIFT (20U) 385 #define USB_OTG_GINTSTS_IISOIXFR_MASK (0x1U << USB_OTG_GINTSTS_IISOIXFR_SHIFT) /* 0x00100000 */ 386 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_MASK 387 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_SHIFT (21U) 388 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_MASK (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_SHIFT) /* 0x00200000 */ 389 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_MASK 390 #define USB_OTG_GINTSTS_DATAFSUSP_SHIFT (22U) 391 #define USB_OTG_GINTSTS_DATAFSUSP_MASK (0x1U << USB_OTG_GINTSTS_DATAFSUSP_SHIFT) /* 0x00400000 */ 392 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_MASK /* Data fetch suspended */ 393 #define USB_OTG_GINTSTS_RSTDET_SHIFT (23U) 394 #define USB_OTG_GINTSTS_RSTDET_MASK (0x1U << USB_OTG_GINTSTS_RSTDET_SHIFT) /* 0x00800000 */ 395 #define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_MASK /* Reset detected interrupt */ 396 #define USB_OTG_GINTSTS_HPRTINT_SHIFT (24U) 397 #define USB_OTG_GINTSTS_HPRTINT_MASK (0x1U << USB_OTG_GINTSTS_HPRTINT_SHIFT) /* 0x01000000 */ 398 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_MASK /* Host port interrupt */ 399 #define USB_OTG_GINTSTS_HCINT_SHIFT (25U) 400 #define USB_OTG_GINTSTS_HCINT_MASK (0x1U << USB_OTG_GINTSTS_HCINT_SHIFT) /* 0x02000000 */ 401 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_MASK /* Host channels interrupt */ 402 #define USB_OTG_GINTSTS_PTXFE_SHIFT (26U) 403 #define USB_OTG_GINTSTS_PTXFE_MASK (0x1U << USB_OTG_GINTSTS_PTXFE_SHIFT) /* 0x04000000 */ 404 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_MASK /* Periodic TxFIFO empty */ 405 #define USB_OTG_GINTSTS_LPMINT_SHIFT (27U) 406 #define USB_OTG_GINTSTS_LPMINT_MASK (0x1U << USB_OTG_GINTSTS_LPMINT_SHIFT) /* 0x08000000 */ 407 #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_MASK /* LPM interrupt */ 408 #define USB_OTG_GINTSTS_CIDSCHG_SHIFT (28U) 409 #define USB_OTG_GINTSTS_CIDSCHG_MASK (0x1U << USB_OTG_GINTSTS_CIDSCHG_SHIFT) /* 0x10000000 */ 410 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_MASK /* Connector ID status change */ 411 #define USB_OTG_GINTSTS_DISCINT_SHIFT (29U) 412 #define USB_OTG_GINTSTS_DISCINT_MASK (0x1U << USB_OTG_GINTSTS_DISCINT_SHIFT) /* 0x20000000 */ 413 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_MASK /* Disconnect detected interrupt */ 414 #define USB_OTG_GINTSTS_SRQINT_SHIFT (30U) 415 #define USB_OTG_GINTSTS_SRQINT_MASK (0x1U << USB_OTG_GINTSTS_SRQINT_SHIFT) /* 0x40000000 */ 416 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_MASK 417 #define USB_OTG_GINTSTS_WKUINT_SHIFT (31U) 418 #define USB_OTG_GINTSTS_WKUINT_MASK (0x1U << USB_OTG_GINTSTS_WKUINT_SHIFT) /* 0x80000000 */ 419 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_MASK 420 /******************** Bit definition for USB_OTG_GINTMSK register ********************/ 421 #define USB_OTG_GINTMSK_MMISM_SHIFT (1U) 422 #define USB_OTG_GINTMSK_MMISM_MASK (0x1U << USB_OTG_GINTMSK_MMISM_SHIFT) /* 0x00000002 */ 423 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_MASK /* Mode mismatch interrupt mask */ 424 #define USB_OTG_GINTMSK_OTGINT_SHIFT (2U) 425 #define USB_OTG_GINTMSK_OTGINT_MASK (0x1U << USB_OTG_GINTMSK_OTGINT_SHIFT) /* 0x00000004 */ 426 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_MASK /* OTG interrupt mask */ 427 #define USB_OTG_GINTMSK_SOFM_SHIFT (3U) 428 #define USB_OTG_GINTMSK_SOFM_MASK (0x1U << USB_OTG_GINTMSK_SOFM_SHIFT) /* 0x00000008 */ 429 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_MASK /* Start of frame mask */ 430 #define USB_OTG_GINTMSK_RXFLVLM_SHIFT (4U) 431 #define USB_OTG_GINTMSK_RXFLVLM_MASK (0x1U << USB_OTG_GINTMSK_RXFLVLM_SHIFT) /* 0x00000010 */ 432 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_MASK /* Receive FIFO nonempty mask */ 433 #define USB_OTG_GINTMSK_NPTXFEM_SHIFT (5U) 434 #define USB_OTG_GINTMSK_NPTXFEM_MASK (0x1U << USB_OTG_GINTMSK_NPTXFEM_SHIFT) /* 0x00000020 */ 435 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_MASK /* Nonperiodic TxFIFO empty mask */ 436 #define USB_OTG_GINTMSK_GINAKEFFM_SHIFT (6U) 437 #define USB_OTG_GINTMSK_GINAKEFFM_MASK (0x1U << USB_OTG_GINTMSK_GINAKEFFM_SHIFT) /* 0x00000040 */ 438 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_MASK 439 #define USB_OTG_GINTMSK_GONAKEFFM_SHIFT (7U) 440 #define USB_OTG_GINTMSK_GONAKEFFM_MASK (0x1U << USB_OTG_GINTMSK_GONAKEFFM_SHIFT) /* 0x00000080 */ 441 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_MASK /* Global OUT NAK effective mask */ 442 #define USB_OTG_GINTMSK_ESUSPM_SHIFT (10U) 443 #define USB_OTG_GINTMSK_ESUSPM_MASK (0x1U << USB_OTG_GINTMSK_ESUSPM_SHIFT) /* 0x00000400 */ 444 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_MASK /* Early suspend mask */ 445 #define USB_OTG_GINTMSK_USBSUSPM_SHIFT (11U) 446 #define USB_OTG_GINTMSK_USBSUSPM_MASK (0x1U << USB_OTG_GINTMSK_USBSUSPM_SHIFT) /* 0x00000800 */ 447 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_MASK /* USB suspend mask */ 448 #define USB_OTG_GINTMSK_USBRST_SHIFT (12U) 449 #define USB_OTG_GINTMSK_USBRST_MASK (0x1U << USB_OTG_GINTMSK_USBRST_SHIFT) /* 0x00001000 */ 450 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_MASK /* USB reset mask */ 451 #define USB_OTG_GINTMSK_ENUMDNEM_SHIFT (13U) 452 #define USB_OTG_GINTMSK_ENUMDNEM_MASK (0x1U << USB_OTG_GINTMSK_ENUMDNEM_SHIFT) /* 0x00002000 */ 453 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_MASK /* Enumeration done mask */ 454 #define USB_OTG_GINTMSK_ISOODRPM_SHIFT (14U) 455 #define USB_OTG_GINTMSK_ISOODRPM_MASK (0x1U << USB_OTG_GINTMSK_ISOODRPM_SHIFT) /* 0x00004000 */ 456 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_MASK 457 #define USB_OTG_GINTMSK_EOPFM_SHIFT (15U) 458 #define USB_OTG_GINTMSK_EOPFM_MASK (0x1U << USB_OTG_GINTMSK_EOPFM_SHIFT) /* 0x00008000 */ 459 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_MASK 460 #define USB_OTG_GINTMSK_EPMISM_SHIFT (17U) 461 #define USB_OTG_GINTMSK_EPMISM_MASK (0x1U << USB_OTG_GINTMSK_EPMISM_SHIFT) /* 0x00020000 */ 462 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_MASK /* Endpoint mismatch interrupt mask */ 463 #define USB_OTG_GINTMSK_IEPINT_SHIFT (18U) 464 #define USB_OTG_GINTMSK_IEPINT_MASK (0x1U << USB_OTG_GINTMSK_IEPINT_SHIFT) /* 0x00040000 */ 465 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_MASK /* IN endpoints interrupt mask */ 466 #define USB_OTG_GINTMSK_OEPINT_SHIFT (19U) 467 #define USB_OTG_GINTMSK_OEPINT_MASK (0x1U << USB_OTG_GINTMSK_OEPINT_SHIFT) /* 0x00080000 */ 468 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_MASK /* OUT endpoints interrupt mask */ 469 #define USB_OTG_GINTMSK_IISOIXFRM_SHIFT (20U) 470 #define USB_OTG_GINTMSK_IISOIXFRM_MASK (0x1U << USB_OTG_GINTMSK_IISOIXFRM_SHIFT) /* 0x00100000 */ 471 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_MASK 472 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_SHIFT (21U) 473 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_MASK (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_SHIFT) /* 0x00200000 */ 474 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_MASK 475 #define USB_OTG_GINTMSK_FSUSPM_SHIFT (22U) 476 #define USB_OTG_GINTMSK_FSUSPM_MASK (0x1U << USB_OTG_GINTMSK_FSUSPM_SHIFT) /* 0x00400000 */ 477 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_MASK /* Data fetch suspended mask */ 478 #define USB_OTG_GINTMSK_RSTDEM_SHIFT (23U) 479 #define USB_OTG_GINTMSK_RSTDEM_MASK (0x1U << USB_OTG_GINTMSK_RSTDEM_SHIFT) /* 0x00800000 */ 480 #define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_MASK /* Reset detected interrupt mask */ 481 #define USB_OTG_GINTMSK_PRTIM_SHIFT (24U) 482 #define USB_OTG_GINTMSK_PRTIM_MASK (0x1U << USB_OTG_GINTMSK_PRTIM_SHIFT) /* 0x01000000 */ 483 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_MASK /* Host port interrupt mask */ 484 #define USB_OTG_GINTMSK_HCIM_SHIFT (25U) 485 #define USB_OTG_GINTMSK_HCIM_MASK (0x1U << USB_OTG_GINTMSK_HCIM_SHIFT) /* 0x02000000 */ 486 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_MASK /* Host channels interrupt mask */ 487 #define USB_OTG_GINTMSK_PTXFEM_SHIFT (26U) 488 #define USB_OTG_GINTMSK_PTXFEM_MASK (0x1U << USB_OTG_GINTMSK_PTXFEM_SHIFT) /* 0x04000000 */ 489 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_MASK /* Periodic TxFIFO empty mask */ 490 #define USB_OTG_GINTMSK_LPMINTM_SHIFT (27U) 491 #define USB_OTG_GINTMSK_LPMINTM_MASK (0x1U << USB_OTG_GINTMSK_LPMINTM_SHIFT) /* 0x08000000 */ 492 #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_MASK /* LPM interrupt Mask */ 493 #define USB_OTG_GINTMSK_CIDSCHGM_SHIFT (28U) 494 #define USB_OTG_GINTMSK_CIDSCHGM_MASK (0x1U << USB_OTG_GINTMSK_CIDSCHGM_SHIFT) /* 0x10000000 */ 495 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_MASK /* Connector ID status change mask */ 496 #define USB_OTG_GINTMSK_DISCINT_SHIFT (29U) 497 #define USB_OTG_GINTMSK_DISCINT_MASK (0x1U << USB_OTG_GINTMSK_DISCINT_SHIFT) /* 0x20000000 */ 498 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_MASK 499 #define USB_OTG_GINTMSK_SRQIM_SHIFT (30U) 500 #define USB_OTG_GINTMSK_SRQIM_MASK (0x1U << USB_OTG_GINTMSK_SRQIM_SHIFT) /* 0x40000000 */ 501 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_MASK 502 #define USB_OTG_GINTMSK_WUIM_SHIFT (31U) 503 #define USB_OTG_GINTMSK_WUIM_MASK (0x1U << USB_OTG_GINTMSK_WUIM_SHIFT) /* 0x80000000 */ 504 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_MASK 505 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ 506 #define USB_OTG_GRXSTSP_EPNUM_SHIFT (0U) 507 #define USB_OTG_GRXSTSP_EPNUM_MASK (0xFU << USB_OTG_GRXSTSP_EPNUM_SHIFT) /* 0x0000000F */ 508 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_MASK /* IN EP interrupt mask bits */ 509 #define USB_OTG_GRXSTSP_BCNT_SHIFT (4U) 510 #define USB_OTG_GRXSTSP_BCNT_MASK (0x7FFU << USB_OTG_GRXSTSP_BCNT_SHIFT) /* 0x00007FF0 */ 511 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_MASK /* OUT EP interrupt mask bits */ 512 #define USB_OTG_GRXSTSP_DPID_SHIFT (15U) 513 #define USB_OTG_GRXSTSP_DPID_MASK (0x3U << USB_OTG_GRXSTSP_DPID_SHIFT) /* 0x00018000 */ 514 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_MASK /* OUT EP interrupt mask bits */ 515 #define USB_OTG_GRXSTSP_PKTSTS_SHIFT (17U) 516 #define USB_OTG_GRXSTSP_PKTSTS_MASK (0xFU << USB_OTG_GRXSTSP_PKTSTS_SHIFT) /* 0x001E0000 */ 517 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_MASK /* OUT EP interrupt mask bits */ 518 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ 519 #define USB_OTG_GRXFSIZ_RXFD_SHIFT (0U) 520 #define USB_OTG_GRXFSIZ_RXFD_MASK (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_SHIFT) /* 0x0000FFFF */ 521 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_MASK /* RxFIFO depth */ 522 /******************** Bit definition for USB_OTG_GNPTXFSIZ register *******************/ 523 #define USB_OTG_GNPTXFSIZ_NPTXFSA_SHIFT (0U) 524 #define USB_OTG_GNPTXFSIZ_NPTXFSA_MASK (0xFFFFU << USB_OTG_GNPTXFSIZ_NPTXFSA_SHIFT) /* 0x0000FFFF */ 525 #define USB_OTG_GNPTXFSIZ_NPTXFSA USB_OTG_GNPTXFSIZ_NPTXFSA_MASK 526 #define USB_OTG_GNPTXFSIZ_NPTXFD_SHIFT (16U) 527 #define USB_OTG_GNPTXFSIZ_NPTXFD_MASK (0xFFFFU << USB_OTG_GNPTXFSIZ_NPTXFD_SHIFT) /* 0xFFFF0000 */ 528 #define USB_OTG_GNPTXFSIZ_NPTXFD USB_OTG_GNPTXFSIZ_NPTXFD_MASK /* Nonperiodic TxFIFO depth */ 529 #define USB_OTG_GNPTXFSIZ_TXF0SA_SHIFT (0U) 530 #define USB_OTG_GNPTXFSIZ_TXF0SA_MASK (0xFFFFU << USB_OTG_GNPTXFSIZ_TXF0SA_SHIFT) /* 0x0000FFFF */ 531 #define USB_OTG_GNPTXFSIZ_TXF0SA USB_OTG_GNPTXFSIZ_TXF0SA_MASK 532 #define USB_OTG_GNPTXFSIZ_TXF0D_SHIFT (16U) 533 #define USB_OTG_GNPTXFSIZ_TXF0D_MASK (0xFFFFU << USB_OTG_GNPTXFSIZ_TXF0D_SHIFT) /* 0xFFFF0000 */ 534 #define USB_OTG_GNPTXFSIZ_TXF0D USB_OTG_GNPTXFSIZ_TXF0D_MASK /* Endpoint 0 TxFIFO depth */ 535 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/ 536 #define USB_OTG_GNPTXSTS_NPTXFSAV_SHIFT (0U) 537 #define USB_OTG_GNPTXSTS_NPTXFSAV_MASK (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_SHIFT) /* 0x0000FFFF */ 538 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_MASK 539 #define USB_OTG_GNPTXSTS_NPTQXSAV_SHIFT (16U) 540 #define USB_OTG_GNPTXSTS_NPTQXSAV_MASK (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_SHIFT) /* 0x00FF0000 */ 541 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_MASK 542 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_SHIFT) /* 0x00010000 */ 543 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_SHIFT) /* 0x00020000 */ 544 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_SHIFT) /* 0x00040000 */ 545 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_SHIFT) /* 0x00080000 */ 546 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_SHIFT) /* 0x00100000 */ 547 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_SHIFT) /* 0x00200000 */ 548 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_SHIFT) /* 0x00400000 */ 549 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_SHIFT) /* 0x00800000 */ 550 551 #define USB_OTG_GNPTXSTS_NPTXQTOP_SHIFT (24U) 552 #define USB_OTG_GNPTXSTS_NPTXQTOP_MASK (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_SHIFT) /* 0x7F000000 */ 553 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_MASK 554 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_SHIFT) /* 0x01000000 */ 555 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_SHIFT) /* 0x02000000 */ 556 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_SHIFT) /* 0x04000000 */ 557 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_SHIFT) /* 0x08000000 */ 558 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_SHIFT) /* 0x10000000 */ 559 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_SHIFT) /* 0x20000000 */ 560 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_SHIFT) /* 0x40000000 */ 561 /******************** Bit definition for USB_OTG_GHWCFG2 register ********************/ 562 #define USB_OTG_GHWCFG2_DYNFIFOSIZING_SHIFT (19U) 563 #define USB_OTG_GHWCFG2_DYNFIFOSIZING_MASK (0x1U << USB_OTG_GHWCFG2_DYNFIFOSIZING_SHIFT) /* 0x00080000 */ 564 #define USB_OTG_GHWCFG2_DYNFIFOSIZING USB_OTG_GHWCFG2_DYNFIFOSIZING_MASK 565 /******************** Bit definition for USB_OTG_GHWCFG4 register ********************/ 566 #define USB_OTG_GHWCFG4_DEDFIFOMODE_SHIFT (25U) 567 #define USB_OTG_GHWCFG4_DEDFIFOMODE_MASK (0x1U << USB_OTG_GHWCFG4_DEDFIFOMODE_SHIFT) /* 0x00080000 */ 568 #define USB_OTG_GHWCFG4_DEDFIFOMODE USB_OTG_GHWCFG4_DEDFIFOMODE_MASK /* Dedicated FIFO enabled */ 569 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ 570 #define USB_OTG_GLPMCFG_LPMEN_SHIFT (0U) 571 #define USB_OTG_GLPMCFG_LPMEN_MASK (0x1U << USB_OTG_GLPMCFG_LPMEN_SHIFT) /* 0x00000001 */ 572 #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_MASK /* LPM support enable */ 573 #define USB_OTG_GLPMCFG_LPMACK_SHIFT (1U) 574 #define USB_OTG_GLPMCFG_LPMACK_MASK (0x1U << USB_OTG_GLPMCFG_LPMACK_SHIFT) /* 0x00000002 */ 575 #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_MASK /* LPM Token acknowledge enable */ 576 #define USB_OTG_GLPMCFG_BESL_SHIFT (2U) 577 #define USB_OTG_GLPMCFG_BESL_MASK (0xFU << USB_OTG_GLPMCFG_BESL_SHIFT) /* 0x0000003C */ 578 #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_MASK 579 #define USB_OTG_GLPMCFG_REMWAKE_SHIFT (6U) 580 #define USB_OTG_GLPMCFG_REMWAKE_MASK (0x1U << USB_OTG_GLPMCFG_REMWAKE_SHIFT) /* 0x00000040 */ 581 #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_MASK 582 #define USB_OTG_GLPMCFG_L1SSEN_SHIFT (7U) 583 #define USB_OTG_GLPMCFG_L1SSEN_MASK (0x1U << USB_OTG_GLPMCFG_L1SSEN_SHIFT) /* 0x00000080 */ 584 #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_MASK /* L1 shallow sleep enable */ 585 #define USB_OTG_GLPMCFG_BESLTHRS_SHIFT (8U) 586 #define USB_OTG_GLPMCFG_BESLTHRS_MASK (0xFU << USB_OTG_GLPMCFG_BESLTHRS_SHIFT) /* 0x00000F00 */ 587 #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_MASK /* BESL threshold */ 588 #define USB_OTG_GLPMCFG_L1DSEN_SHIFT (12U) 589 #define USB_OTG_GLPMCFG_L1DSEN_MASK (0x1U << USB_OTG_GLPMCFG_L1DSEN_SHIFT) /* 0x00001000 */ 590 #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_MASK /* L1 deep sleep enable */ 591 #define USB_OTG_GLPMCFG_LPMRSP_SHIFT (13U) 592 #define USB_OTG_GLPMCFG_LPMRSP_MASK (0x3U << USB_OTG_GLPMCFG_LPMRSP_SHIFT) /* 0x00006000 */ 593 #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_MASK /* LPM response */ 594 #define USB_OTG_GLPMCFG_SLPSTS_SHIFT (15U) 595 #define USB_OTG_GLPMCFG_SLPSTS_MASK (0x1U << USB_OTG_GLPMCFG_SLPSTS_SHIFT) /* 0x00008000 */ 596 #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_MASK /* Port sleep status */ 597 #define USB_OTG_GLPMCFG_L1RSMOK_SHIFT (16U) 598 #define USB_OTG_GLPMCFG_L1RSMOK_MASK (0x1U << USB_OTG_GLPMCFG_L1RSMOK_SHIFT) /* 0x00010000 */ 599 #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_MASK /* Sleep State Resume OK */ 600 #define USB_OTG_GLPMCFG_LPMCHIDX_SHIFT (17U) 601 #define USB_OTG_GLPMCFG_LPMCHIDX_MASK (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_SHIFT) /* 0x001E0000 */ 602 #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_MASK /* LPM Channel Index */ 603 #define USB_OTG_GLPMCFG_LPMRCNT_SHIFT (21U) 604 #define USB_OTG_GLPMCFG_LPMRCNT_MASK (0x7U << USB_OTG_GLPMCFG_LPMRCNT_SHIFT) /* 0x00E00000 */ 605 #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_MASK /* LPM retry count */ 606 #define USB_OTG_GLPMCFG_SNDLPM_SHIFT (24U) 607 #define USB_OTG_GLPMCFG_SNDLPM_MASK (0x1U << USB_OTG_GLPMCFG_SNDLPM_SHIFT) /* 0x01000000 */ 608 #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_MASK /* Send LPM transaction */ 609 #define USB_OTG_GLPMCFG_LPMRCNTSTS_SHIFT (25U) 610 #define USB_OTG_GLPMCFG_LPMRCNTSTS_MASK (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_SHIFT) /* 0x0E000000 */ 611 #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_MASK /* LPM retry count status */ 612 #define USB_OTG_GLPMCFG_ENBESL_SHIFT (28U) 613 #define USB_OTG_GLPMCFG_ENBESL_MASK (0x1U << USB_OTG_GLPMCFG_ENBESL_SHIFT) /* 0x10000000 */ 614 #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_MASK 615 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/ 616 #define USB_OTG_HPTXFSIZ_PTXSA_SHIFT (0U) 617 #define USB_OTG_HPTXFSIZ_PTXSA_MASK (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_SHIFT) /* 0x0000FFFF */ 618 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_MASK 619 #define USB_OTG_HPTXFSIZ_PTXFD_SHIFT (16U) 620 #define USB_OTG_HPTXFSIZ_PTXFD_MASK (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_SHIFT) /* 0xFFFF0000 */ 621 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_MASK /* Host periodic TxFIFO depth */ 622 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/ 623 #define USB_OTG_DIEPTXF_INEPTXSA_SHIFT (0U) 624 #define USB_OTG_DIEPTXF_INEPTXSA_MASK (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_SHIFT) /* 0x0000FFFF */ 625 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_MASK 626 #define USB_OTG_DIEPTXF_INEPTXFD_SHIFT (16U) 627 #define USB_OTG_DIEPTXF_INEPTXFD_MASK (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_SHIFT) /* 0xFFFF0000 */ 628 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_MASK /* IN endpoint TxFIFO depth */ 629 /******************** Bit definition for USB_OTG_HCFG register ********************/ 630 #define USB_OTG_HCFG_FSLSPCS_SHIFT (0U) 631 #define USB_OTG_HCFG_FSLSPCS_MASK (0x3U << USB_OTG_HCFG_FSLSPCS_SHIFT) /* 0x00000003 */ 632 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_MASK /* FS/LS PHY clock select */ 633 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_SHIFT) /* 0x00000001 */ 634 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_SHIFT) /* 0x00000002 */ 635 #define USB_OTG_HCFG_FSLSS_SHIFT (2U) 636 #define USB_OTG_HCFG_FSLSS_MASK (0x1U << USB_OTG_HCFG_FSLSS_SHIFT) /* 0x00000004 */ 637 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_MASK /* FS- and LS-only support */ 638 /******************** Bit definition for USB_OTG_HFIR register ********************/ 639 #define USB_OTG_HFIR_FRIVL_SHIFT (0U) 640 #define USB_OTG_HFIR_FRIVL_MASK (0xFFFFU << USB_OTG_HFIR_FRIVL_SHIFT) /* 0x0000FFFF */ 641 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_MASK /* Frame interval */ 642 /******************** Bit definition for USB_OTG_HFNUM register ********************/ 643 #define USB_OTG_HFNUM_FRNUM_SHIFT (0U) 644 #define USB_OTG_HFNUM_FRNUM_MASK (0xFFFFU << USB_OTG_HFNUM_FRNUM_SHIFT) /* 0x0000FFFF */ 645 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_MASK /* Frame number */ 646 #define USB_OTG_HFNUM_FTREM_SHIFT (16U) 647 #define USB_OTG_HFNUM_FTREM_MASK (0xFFFFU << USB_OTG_HFNUM_FTREM_SHIFT) /* 0xFFFF0000 */ 648 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_MASK /* Frame time remaining */ 649 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ 650 #define USB_OTG_HPTXSTS_PTXFSAVL_SHIFT (0U) 651 #define USB_OTG_HPTXSTS_PTXFSAVL_MASK (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_SHIFT) /* 0x0000FFFF */ 652 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_MASK 653 #define USB_OTG_HPTXSTS_PTXQSAV_SHIFT (16U) 654 #define USB_OTG_HPTXSTS_PTXQSAV_MASK (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_SHIFT) /* 0x00FF0000 */ 655 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_MASK 656 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_SHIFT) /* 0x00010000 */ 657 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_SHIFT) /* 0x00020000 */ 658 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_SHIFT) /* 0x00040000 */ 659 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_SHIFT) /* 0x00080000 */ 660 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_SHIFT) /* 0x00100000 */ 661 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_SHIFT) /* 0x00200000 */ 662 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_SHIFT) /* 0x00400000 */ 663 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_SHIFT) /* 0x00800000 */ 664 #define USB_OTG_HPTXSTS_PTXQTOP_SHIFT (24U) 665 #define USB_OTG_HPTXSTS_PTXQTOP_MASK (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_SHIFT) /* 0xFF000000 */ 666 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_MASK 667 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_SHIFT) /* 0x01000000 */ 668 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_SHIFT) /* 0x02000000 */ 669 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_SHIFT) /* 0x04000000 */ 670 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_SHIFT) /* 0x08000000 */ 671 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_SHIFT) /* 0x10000000 */ 672 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_SHIFT) /* 0x20000000 */ 673 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_SHIFT) /* 0x40000000 */ 674 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_SHIFT) /* 0x80000000 */ 675 /******************** Bit definition for USB_OTG_HAINT register ********************/ 676 #define USB_OTG_HAINT_HAINT_SHIFT (0U) 677 #define USB_OTG_HAINT_HAINT_MASK (0xFFFFU << USB_OTG_HAINT_HAINT_SHIFT) /* 0x0000FFFF */ 678 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_MASK /* Channel interrupts */ 679 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/ 680 #define USB_OTG_HAINTMSK_HAINTM_SHIFT (0U) 681 #define USB_OTG_HAINTMSK_HAINTM_MASK (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_SHIFT) /* 0x0000FFFF */ 682 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_MASK /* Channel interrupt mask */ 683 /******************** Bit definition for USB_OTG_HPRT register ********************/ 684 #define USB_OTG_HPRT_PCSTS_SHIFT (0U) 685 #define USB_OTG_HPRT_PCSTS_MASK (0x1U << USB_OTG_HPRT_PCSTS_SHIFT) /* 0x00000001 */ 686 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_MASK /* Port connect status */ 687 #define USB_OTG_HPRT_PCDET_SHIFT (1U) 688 #define USB_OTG_HPRT_PCDET_MASK (0x1U << USB_OTG_HPRT_PCDET_SHIFT) /* 0x00000002 */ 689 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_MASK /* Port connect detected */ 690 #define USB_OTG_HPRT_PENA_SHIFT (2U) 691 #define USB_OTG_HPRT_PENA_MASK (0x1U << USB_OTG_HPRT_PENA_SHIFT) /* 0x00000004 */ 692 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_MASK /* Port enable */ 693 #define USB_OTG_HPRT_PENCHNG_SHIFT (3U) 694 #define USB_OTG_HPRT_PENCHNG_MASK (0x1U << USB_OTG_HPRT_PENCHNG_SHIFT) /* 0x00000008 */ 695 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_MASK /* Port enable/disable change */ 696 #define USB_OTG_HPRT_POCA_SHIFT (4U) 697 #define USB_OTG_HPRT_POCA_MASK (0x1U << USB_OTG_HPRT_POCA_SHIFT) /* 0x00000010 */ 698 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_MASK /* Port overcurrent active */ 699 #define USB_OTG_HPRT_POCCHNG_SHIFT (5U) 700 #define USB_OTG_HPRT_POCCHNG_MASK (0x1U << USB_OTG_HPRT_POCCHNG_SHIFT) /* 0x00000020 */ 701 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_MASK /* Port overcurrent change */ 702 #define USB_OTG_HPRT_PRES_SHIFT (6U) 703 #define USB_OTG_HPRT_PRES_MASK (0x1U << USB_OTG_HPRT_PRES_SHIFT) /* 0x00000040 */ 704 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_MASK /* Port resume */ 705 #define USB_OTG_HPRT_PSUSP_SHIFT (7U) 706 #define USB_OTG_HPRT_PSUSP_MASK (0x1U << USB_OTG_HPRT_PSUSP_SHIFT) /* 0x00000080 */ 707 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_MASK /* Port suspend */ 708 #define USB_OTG_HPRT_PRST_SHIFT (8U) 709 #define USB_OTG_HPRT_PRST_MASK (0x1U << USB_OTG_HPRT_PRST_SHIFT) /* 0x00000100 */ 710 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_MASK /* Port reset */ 711 #define USB_OTG_HPRT_PLSTS_SHIFT (10U) 712 #define USB_OTG_HPRT_PLSTS_MASK (0x3U << USB_OTG_HPRT_PLSTS_SHIFT) /* 0x00000C00 */ 713 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_MASK /* Port line status */ 714 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_SHIFT) /* 0x00000400 */ 715 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_SHIFT) /* 0x00000800 */ 716 #define USB_OTG_HPRT_PPWR_SHIFT (12U) 717 #define USB_OTG_HPRT_PPWR_MASK (0x1U << USB_OTG_HPRT_PPWR_SHIFT) /* 0x00001000 */ 718 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_MASK /* Port power */ 719 #define USB_OTG_HPRT_PTCTL_SHIFT (13U) 720 #define USB_OTG_HPRT_PTCTL_MASK (0xFU << USB_OTG_HPRT_PTCTL_SHIFT) /* 0x0001E000 */ 721 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_MASK /* Port test control */ 722 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_SHIFT) /* 0x00002000 */ 723 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_SHIFT) /* 0x00004000 */ 724 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_SHIFT) /* 0x00008000 */ 725 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_SHIFT) /* 0x00010000 */ 726 #define USB_OTG_HPRT_PSPD_SHIFT (17U) 727 #define USB_OTG_HPRT_PSPD_MASK (0x3U << USB_OTG_HPRT_PSPD_SHIFT) /* 0x00060000 */ 728 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_MASK /* Port speed */ 729 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_SHIFT) /* 0x00020000 */ 730 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_SHIFT) /* 0x00040000 */ 731 /******************** Bit definition for USB_OTG_HCCHAR register ********************/ 732 #define USB_OTG_HCCHAR_MPSIZ_SHIFT (0U) 733 #define USB_OTG_HCCHAR_MPSIZ_MASK (0x7FFU << USB_OTG_HCCHAR_MPSIZ_SHIFT) /* 0x000007FF */ 734 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_MASK /* Maximum packet size */ 735 #define USB_OTG_HCCHAR_EPNUM_SHIFT (11U) 736 #define USB_OTG_HCCHAR_EPNUM_MASK (0xFU << USB_OTG_HCCHAR_EPNUM_SHIFT) /* 0x00007800 */ 737 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_MASK /* Endpoint number */ 738 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_SHIFT) /* 0x00000800 */ 739 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_SHIFT) /* 0x00001000 */ 740 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_SHIFT) /* 0x00002000 */ 741 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_SHIFT) /* 0x00004000 */ 742 #define USB_OTG_HCCHAR_EPDIR_SHIFT (15U) 743 #define USB_OTG_HCCHAR_EPDIR_MASK (0x1U << USB_OTG_HCCHAR_EPDIR_SHIFT) /* 0x00008000 */ 744 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_MASK /* Endpoint direction */ 745 #define USB_OTG_HCCHAR_LSDEV_SHIFT (17U) 746 #define USB_OTG_HCCHAR_LSDEV_MASK (0x1U << USB_OTG_HCCHAR_LSDEV_SHIFT) /* 0x00020000 */ 747 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_MASK /* Low-speed device */ 748 #define USB_OTG_HCCHAR_EPTYP_SHIFT (18U) 749 #define USB_OTG_HCCHAR_EPTYP_MASK (0x3U << USB_OTG_HCCHAR_EPTYP_SHIFT) /* 0x000C0000 */ 750 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_MASK /* Endpoint type */ 751 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_SHIFT) /* 0x00040000 */ 752 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_SHIFT) /* 0x00080000 */ 753 #define USB_OTG_HCCHAR_MC_SHIFT (20U) 754 #define USB_OTG_HCCHAR_MC_MASK (0x3U << USB_OTG_HCCHAR_MC_SHIFT) /* 0x00300000 */ 755 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_MASK 756 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_SHIFT) /* 0x00100000 */ 757 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_SHIFT) /* 0x00200000 */ 758 #define USB_OTG_HCCHAR_DAD_SHIFT (22U) 759 #define USB_OTG_HCCHAR_DAD_MASK (0x7FU << USB_OTG_HCCHAR_DAD_SHIFT) /* 0x1FC00000 */ 760 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_MASK /* Device address */ 761 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_SHIFT) /* 0x00400000 */ 762 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_SHIFT) /* 0x00800000 */ 763 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_SHIFT) /* 0x01000000 */ 764 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_SHIFT) /* 0x02000000 */ 765 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_SHIFT) /* 0x04000000 */ 766 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_SHIFT) /* 0x08000000 */ 767 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_SHIFT) /* 0x10000000 */ 768 #define USB_OTG_HCCHAR_ODDFRM_SHIFT (29U) 769 #define USB_OTG_HCCHAR_ODDFRM_MASK (0x1U << USB_OTG_HCCHAR_ODDFRM_SHIFT) /* 0x20000000 */ 770 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_MASK /* Odd frame */ 771 #define USB_OTG_HCCHAR_CHDIS_SHIFT (30U) 772 #define USB_OTG_HCCHAR_CHDIS_MASK (0x1U << USB_OTG_HCCHAR_CHDIS_SHIFT) /* 0x40000000 */ 773 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_MASK /* Channel disable */ 774 #define USB_OTG_HCCHAR_CHENA_SHIFT (31U) 775 #define USB_OTG_HCCHAR_CHENA_MASK (0x1U << USB_OTG_HCCHAR_CHENA_SHIFT) /* 0x80000000 */ 776 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_MASK /* Channel enable */ 777 /******************** Bit definition for USB_OTG_HCSPLT register ********************/ 778 #define USB_OTG_HCSPLT_PRTADDR_SHIFT (0U) 779 #define USB_OTG_HCSPLT_PRTADDR_MASK (0x7FU << USB_OTG_HCSPLT_PRTADDR_SHIFT) /* 0x0000007F */ 780 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_MASK /* Port address */ 781 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_SHIFT) /* 0x00000001 */ 782 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_SHIFT) /* 0x00000002 */ 783 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_SHIFT) /* 0x00000004 */ 784 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_SHIFT) /* 0x00000008 */ 785 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_SHIFT) /* 0x00000010 */ 786 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_SHIFT) /* 0x00000020 */ 787 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_SHIFT) /* 0x00000040 */ 788 #define USB_OTG_HCSPLT_HUBADDR_SHIFT (7U) 789 #define USB_OTG_HCSPLT_HUBADDR_MASK (0x7FU << USB_OTG_HCSPLT_HUBADDR_SHIFT) /* 0x00003F80 */ 790 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_MASK /* Hub address */ 791 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_SHIFT) /* 0x00000080 */ 792 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_SHIFT) /* 0x00000100 */ 793 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_SHIFT) /* 0x00000200 */ 794 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_SHIFT) /* 0x00000400 */ 795 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_SHIFT) /* 0x00000800 */ 796 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_SHIFT) /* 0x00001000 */ 797 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_SHIFT) /* 0x00002000 */ 798 #define USB_OTG_HCSPLT_XACTPOS_SHIFT (14U) 799 #define USB_OTG_HCSPLT_XACTPOS_MASK (0x3U << USB_OTG_HCSPLT_XACTPOS_SHIFT) /* 0x0000C000 */ 800 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_MASK /* XACTPOS */ 801 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_SHIFT) /* 0x00004000 */ 802 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_SHIFT) /* 0x00008000 */ 803 #define USB_OTG_HCSPLT_COMPLSPLT_SHIFT (16U) 804 #define USB_OTG_HCSPLT_COMPLSPLT_MASK (0x1U << USB_OTG_HCSPLT_COMPLSPLT_SHIFT) /* 0x00010000 */ 805 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_MASK /* Do complete split */ 806 #define USB_OTG_HCSPLT_SPLITEN_SHIFT (31U) 807 #define USB_OTG_HCSPLT_SPLITEN_MASK (0x1U << USB_OTG_HCSPLT_SPLITEN_SHIFT) /* 0x80000000 */ 808 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_MASK /* Split enable */ 809 /******************** Bit definition for USB_OTG_HCINT register ********************/ 810 #define USB_OTG_HCINT_XFRC_SHIFT (0U) 811 #define USB_OTG_HCINT_XFRC_MASK (0x1U << USB_OTG_HCINT_XFRC_SHIFT) /* 0x00000001 */ 812 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_MASK /* Transfer completed */ 813 #define USB_OTG_HCINT_CHH_SHIFT (1U) 814 #define USB_OTG_HCINT_CHH_MASK (0x1U << USB_OTG_HCINT_CHH_SHIFT) /* 0x00000002 */ 815 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_MASK /* Channel halted */ 816 #define USB_OTG_HCINT_AHBERR_SHIFT (2U) 817 #define USB_OTG_HCINT_AHBERR_MASK (0x1U << USB_OTG_HCINT_AHBERR_SHIFT) /* 0x00000004 */ 818 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_MASK /* AHB error */ 819 #define USB_OTG_HCINT_STALL_SHIFT (3U) 820 #define USB_OTG_HCINT_STALL_MASK (0x1U << USB_OTG_HCINT_STALL_SHIFT) /* 0x00000008 */ 821 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_MASK 822 #define USB_OTG_HCINT_NAK_SHIFT (4U) 823 #define USB_OTG_HCINT_NAK_MASK (0x1U << USB_OTG_HCINT_NAK_SHIFT) /* 0x00000010 */ 824 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_MASK /* NAK response received interrupt */ 825 #define USB_OTG_HCINT_ACK_SHIFT (5U) 826 #define USB_OTG_HCINT_ACK_MASK (0x1U << USB_OTG_HCINT_ACK_SHIFT) /* 0x00000020 */ 827 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_MASK 828 #define USB_OTG_HCINT_NYET_SHIFT (6U) 829 #define USB_OTG_HCINT_NYET_MASK (0x1U << USB_OTG_HCINT_NYET_SHIFT) /* 0x00000040 */ 830 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_MASK /* Response received interrupt */ 831 #define USB_OTG_HCINT_TXERR_SHIFT (7U) 832 #define USB_OTG_HCINT_TXERR_MASK (0x1U << USB_OTG_HCINT_TXERR_SHIFT) /* 0x00000080 */ 833 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_MASK /* Transaction error */ 834 #define USB_OTG_HCINT_BBERR_SHIFT (8U) 835 #define USB_OTG_HCINT_BBERR_MASK (0x1U << USB_OTG_HCINT_BBERR_SHIFT) /* 0x00000100 */ 836 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_MASK /* Babble error */ 837 #define USB_OTG_HCINT_FRMOR_SHIFT (9U) 838 #define USB_OTG_HCINT_FRMOR_MASK (0x1U << USB_OTG_HCINT_FRMOR_SHIFT) /* 0x00000200 */ 839 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_MASK /* Frame overrun */ 840 #define USB_OTG_HCINT_DTERR_SHIFT (10U) 841 #define USB_OTG_HCINT_DTERR_MASK (0x1U << USB_OTG_HCINT_DTERR_SHIFT) /* 0x00000400 */ 842 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_MASK /* Data toggle error */ 843 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/ 844 #define USB_OTG_HCINTMSK_XFRCM_SHIFT (0U) 845 #define USB_OTG_HCINTMSK_XFRCM_MASK (0x1U << USB_OTG_HCINTMSK_XFRCM_SHIFT) /* 0x00000001 */ 846 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_MASK /* Transfer completed mask */ 847 #define USB_OTG_HCINTMSK_CHHM_SHIFT (1U) 848 #define USB_OTG_HCINTMSK_CHHM_MASK (0x1U << USB_OTG_HCINTMSK_CHHM_SHIFT) /* 0x00000002 */ 849 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_MASK /* Channel halted mask */ 850 #define USB_OTG_HCINTMSK_AHBERR_SHIFT (2U) 851 #define USB_OTG_HCINTMSK_AHBERR_MASK (0x1U << USB_OTG_HCINTMSK_AHBERR_SHIFT) /* 0x00000004 */ 852 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_MASK /* AHB error */ 853 #define USB_OTG_HCINTMSK_STALLM_SHIFT (3U) 854 #define USB_OTG_HCINTMSK_STALLM_MASK (0x1U << USB_OTG_HCINTMSK_STALLM_SHIFT) /* 0x00000008 */ 855 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_MASK 856 #define USB_OTG_HCINTMSK_NAKM_SHIFT (4U) 857 #define USB_OTG_HCINTMSK_NAKM_MASK (0x1U << USB_OTG_HCINTMSK_NAKM_SHIFT) /* 0x00000010 */ 858 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_MASK 859 #define USB_OTG_HCINTMSK_ACKM_SHIFT (5U) 860 #define USB_OTG_HCINTMSK_ACKM_MASK (0x1U << USB_OTG_HCINTMSK_ACKM_SHIFT) /* 0x00000020 */ 861 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_MASK 862 #define USB_OTG_HCINTMSK_NYET_SHIFT (6U) 863 #define USB_OTG_HCINTMSK_NYET_MASK (0x1U << USB_OTG_HCINTMSK_NYET_SHIFT) /* 0x00000040 */ 864 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_MASK /* response received interrupt mask */ 865 #define USB_OTG_HCINTMSK_TXERRM_SHIFT (7U) 866 #define USB_OTG_HCINTMSK_TXERRM_MASK (0x1U << USB_OTG_HCINTMSK_TXERRM_SHIFT) /* 0x00000080 */ 867 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_MASK /* Transaction error mask */ 868 #define USB_OTG_HCINTMSK_BBERRM_SHIFT (8U) 869 #define USB_OTG_HCINTMSK_BBERRM_MASK (0x1U << USB_OTG_HCINTMSK_BBERRM_SHIFT) /* 0x00000100 */ 870 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_MASK /* Babble error mask */ 871 #define USB_OTG_HCINTMSK_FRMORM_SHIFT (9U) 872 #define USB_OTG_HCINTMSK_FRMORM_MASK (0x1U << USB_OTG_HCINTMSK_FRMORM_SHIFT) /* 0x00000200 */ 873 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_MASK /* Frame overrun mask */ 874 #define USB_OTG_HCINTMSK_DTERRM_SHIFT (10U) 875 #define USB_OTG_HCINTMSK_DTERRM_MASK (0x1U << USB_OTG_HCINTMSK_DTERRM_SHIFT) /* 0x00000400 */ 876 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_MASK /* Data toggle error mask */ 877 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ 878 #define USB_OTG_HCTSIZ_XFRSIZ_SHIFT (0U) 879 #define USB_OTG_HCTSIZ_XFRSIZ_MASK (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_SHIFT) /* 0x0007FFFF */ 880 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_MASK /* Transfer size */ 881 #define USB_OTG_HCTSIZ_PKTCNT_SHIFT (19U) 882 #define USB_OTG_HCTSIZ_PKTCNT_MASK (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_SHIFT) /* 0x1FF80000 */ 883 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_MASK /* Packet count */ 884 #define USB_OTG_HCTSIZ_DOPING_SHIFT (31U) 885 #define USB_OTG_HCTSIZ_DOPING_MASK (0x1U << USB_OTG_HCTSIZ_DOPING_SHIFT) /* 0x80000000 */ 886 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_MASK /* Do PING */ 887 #define USB_OTG_HCTSIZ_DPID_SHIFT (29U) 888 #define USB_OTG_HCTSIZ_DPID_MASK (0x3U << USB_OTG_HCTSIZ_DPID_SHIFT) /* 0x60000000 */ 889 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_MASK /* Data PID */ 890 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_SHIFT) /* 0x20000000 */ 891 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_SHIFT) /* 0x40000000 */ 892 /******************** Bit definition for USB_OTG_HCDMA register ********************/ 893 #define USB_OTG_HCDMA_DMAADDR_SHIFT (0U) 894 #define USB_OTG_HCDMA_DMAADDR_MASK (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_SHIFT) /* 0xFFFFFFFF */ 895 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_MASK /* DMA address */ 896 /******************** Bit definition for USB_OTG_DCFG register ********************/ 897 #define USB_OTG_DCFG_DSPD_SHIFT (0U) 898 #define USB_OTG_DCFG_DSPD_MASK (0x3U << USB_OTG_DCFG_DSPD_SHIFT) /* 0x00000003 */ 899 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_MASK /* Device speed */ 900 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_SHIFT) /* 0x00000001 */ 901 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_SHIFT) /* 0x00000002 */ 902 #define USB_OTG_DCFG_NZLSOHSK_SHIFT (2U) 903 #define USB_OTG_DCFG_NZLSOHSK_MASK (0x1U << USB_OTG_DCFG_NZLSOHSK_SHIFT) /* 0x00000004 */ 904 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_MASK 905 #define USB_OTG_DCFG_DAD_SHIFT (4U) 906 #define USB_OTG_DCFG_DAD_MASK (0x7FU << USB_OTG_DCFG_DAD_SHIFT) /* 0x000007F0 */ 907 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_MASK /* Device address */ 908 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_SHIFT) /* 0x00000010 */ 909 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_SHIFT) /* 0x00000020 */ 910 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_SHIFT) /* 0x00000040 */ 911 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_SHIFT) /* 0x00000080 */ 912 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_SHIFT) /* 0x00000100 */ 913 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_SHIFT) /* 0x00000200 */ 914 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_SHIFT) /* 0x00000400 */ 915 #define USB_OTG_DCFG_PFIVL_SHIFT (11U) 916 #define USB_OTG_DCFG_PFIVL_MASK (0x3U << USB_OTG_DCFG_PFIVL_SHIFT) /* 0x00001800 */ 917 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_MASK /* Periodic (micro)frame interval */ 918 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_SHIFT) /* 0x00000800 */ 919 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_SHIFT) /* 0x00001000 */ 920 #define USB_OTG_DCFG_PERSCHIVL_SHIFT (24U) 921 #define USB_OTG_DCFG_PERSCHIVL_MASK (0x3U << USB_OTG_DCFG_PERSCHIVL_SHIFT) /* 0x03000000 */ 922 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_MASK /* Periodic scheduling interval */ 923 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_SHIFT) /* 0x01000000 */ 924 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_SHIFT) /* 0x02000000 */ 925 /******************** Bit definition for USB_OTG_DCTL register ********************/ 926 #define USB_OTG_DCTL_RWUSIG_SHIFT (0U) 927 #define USB_OTG_DCTL_RWUSIG_MASK (0x1U << USB_OTG_DCTL_RWUSIG_SHIFT) /* 0x00000001 */ 928 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_MASK /* Remote wakeup signaling */ 929 #define USB_OTG_DCTL_SDIS_SHIFT (1U) 930 #define USB_OTG_DCTL_SDIS_MASK (0x1U << USB_OTG_DCTL_SDIS_SHIFT) /* 0x00000002 */ 931 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_MASK /* Soft disconnect */ 932 #define USB_OTG_DCTL_GINSTS_SHIFT (2U) 933 #define USB_OTG_DCTL_GINSTS_MASK (0x1U << USB_OTG_DCTL_GINSTS_SHIFT) /* 0x00000004 */ 934 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_MASK /* Global IN NAK status */ 935 #define USB_OTG_DCTL_GONSTS_SHIFT (3U) 936 #define USB_OTG_DCTL_GONSTS_MASK (0x1U << USB_OTG_DCTL_GONSTS_SHIFT) /* 0x00000008 */ 937 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_MASK /* Global OUT NAK status */ 938 #define USB_OTG_DCTL_TCTL_SHIFT (4U) 939 #define USB_OTG_DCTL_TCTL_MASK (0x7U << USB_OTG_DCTL_TCTL_SHIFT) /* 0x00000070 */ 940 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_MASK /* Test control */ 941 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_SHIFT) /* 0x00000010 */ 942 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_SHIFT) /* 0x00000020 */ 943 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_SHIFT) /* 0x00000040 */ 944 #define USB_OTG_DCTL_SGINAK_SHIFT (7U) 945 #define USB_OTG_DCTL_SGINAK_MASK (0x1U << USB_OTG_DCTL_SGINAK_SHIFT) /* 0x00000080 */ 946 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_MASK /* Set global IN NAK */ 947 #define USB_OTG_DCTL_CGINAK_SHIFT (8U) 948 #define USB_OTG_DCTL_CGINAK_MASK (0x1U << USB_OTG_DCTL_CGINAK_SHIFT) /* 0x00000100 */ 949 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_MASK /* Clear global IN NAK */ 950 #define USB_OTG_DCTL_SGONAK_SHIFT (9U) 951 #define USB_OTG_DCTL_SGONAK_MASK (0x1U << USB_OTG_DCTL_SGONAK_SHIFT) /* 0x00000200 */ 952 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_MASK /* Set global OUT NAK */ 953 #define USB_OTG_DCTL_CGONAK_SHIFT (10U) 954 #define USB_OTG_DCTL_CGONAK_MASK (0x1U << USB_OTG_DCTL_CGONAK_SHIFT) /* 0x00000400 */ 955 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_MASK /* Clear global OUT NAK */ 956 #define USB_OTG_DCTL_POPRGDNE_SHIFT (11U) 957 #define USB_OTG_DCTL_POPRGDNE_MASK (0x1U << USB_OTG_DCTL_POPRGDNE_SHIFT) /* 0x00000800 */ 958 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_MASK /* Power-on programming done */ 959 /******************** Bit definition for USB_OTG_DSTS register ********************/ 960 #define USB_OTG_DSTS_SUSPSTS_SHIFT (0U) 961 #define USB_OTG_DSTS_SUSPSTS_MASK (0x1U << USB_OTG_DSTS_SUSPSTS_SHIFT) /* 0x00000001 */ 962 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_MASK /* Suspend status */ 963 #define USB_OTG_DSTS_ENUMSPD_SHIFT (1U) 964 #define USB_OTG_DSTS_ENUMSPD_MASK (0x3U << USB_OTG_DSTS_ENUMSPD_SHIFT) /* 0x00000006 */ 965 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_MASK /* Enumerated speed */ 966 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_SHIFT) /* 0x00000002 */ 967 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_SHIFT) /* 0x00000004 */ 968 #define USB_OTG_DSTS_EERR_SHIFT (3U) 969 #define USB_OTG_DSTS_EERR_MASK (0x1U << USB_OTG_DSTS_EERR_SHIFT) /* 0x00000008 */ 970 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_MASK /* Erratic error */ 971 #define USB_OTG_DSTS_FNSOF_SHIFT (8U) 972 #define USB_OTG_DSTS_FNSOF_MASK (0x3FFFU << USB_OTG_DSTS_FNSOF_SHIFT) /* 0x003FFF00 */ 973 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_MASK /* Frame number of the received SOF */ 974 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/ 975 #define USB_OTG_DIEPMSK_XFRCM_SHIFT (0U) 976 #define USB_OTG_DIEPMSK_XFRCM_MASK (0x1U << USB_OTG_DIEPMSK_XFRCM_SHIFT) /* 0x00000001 */ 977 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_MASK 978 #define USB_OTG_DIEPMSK_EPDM_SHIFT (1U) 979 #define USB_OTG_DIEPMSK_EPDM_MASK (0x1U << USB_OTG_DIEPMSK_EPDM_SHIFT) /* 0x00000002 */ 980 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_MASK /* Endpoint disabled interrupt mask */ 981 #define USB_OTG_DIEPMSK_TOM_SHIFT (3U) 982 #define USB_OTG_DIEPMSK_TOM_MASK (0x1U << USB_OTG_DIEPMSK_TOM_SHIFT) /* 0x00000008 */ 983 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_MASK 984 #define USB_OTG_DIEPMSK_ITTXFEMSK_SHIFT (4U) 985 #define USB_OTG_DIEPMSK_ITTXFEMSK_MASK (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_SHIFT) /* 0x00000010 */ 986 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_MASK 987 #define USB_OTG_DIEPMSK_INEPNMM_SHIFT (5U) 988 #define USB_OTG_DIEPMSK_INEPNMM_MASK (0x1U << USB_OTG_DIEPMSK_INEPNMM_SHIFT) /* 0x00000020 */ 989 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_MASK 990 #define USB_OTG_DIEPMSK_INEPNEM_SHIFT (6U) 991 #define USB_OTG_DIEPMSK_INEPNEM_MASK (0x1U << USB_OTG_DIEPMSK_INEPNEM_SHIFT) /* 0x00000040 */ 992 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_MASK /* IN endpoint NAK effective mask */ 993 #define USB_OTG_DIEPMSK_TXFURM_SHIFT (8U) 994 #define USB_OTG_DIEPMSK_TXFURM_MASK (0x1U << USB_OTG_DIEPMSK_TXFURM_SHIFT) /* 0x00000100 */ 995 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_MASK /* FIFO underrun mask */ 996 #define USB_OTG_DIEPMSK_BIM_SHIFT (9U) 997 #define USB_OTG_DIEPMSK_BIM_MASK (0x1U << USB_OTG_DIEPMSK_BIM_SHIFT) /* 0x00000200 */ 998 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_MASK /* BNA interrupt mask */ 999 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/ 1000 #define USB_OTG_DOEPMSK_XFRCM_SHIFT (0U) 1001 #define USB_OTG_DOEPMSK_XFRCM_MASK (0x1U << USB_OTG_DOEPMSK_XFRCM_SHIFT) /* 0x00000001 */ 1002 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_MASK 1003 #define USB_OTG_DOEPMSK_EPDM_SHIFT (1U) 1004 #define USB_OTG_DOEPMSK_EPDM_MASK (0x1U << USB_OTG_DOEPMSK_EPDM_SHIFT) /* 0x00000002 */ 1005 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_MASK /* Endpoint disabled interrupt mask */ 1006 #define USB_OTG_DOEPMSK_STUPM_SHIFT (3U) 1007 #define USB_OTG_DOEPMSK_STUPM_MASK (0x1U << USB_OTG_DOEPMSK_STUPM_SHIFT) /* 0x00000008 */ 1008 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_MASK /* SETUP phase done mask */ 1009 #define USB_OTG_DOEPMSK_OTEPDM_SHIFT (4U) 1010 #define USB_OTG_DOEPMSK_OTEPDM_MASK (0x1U << USB_OTG_DOEPMSK_OTEPDM_SHIFT) /* 0x00000010 */ 1011 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_MASK 1012 #define USB_OTG_DOEPMSK_OTEPSPRM_SHIFT (5U) 1013 #define USB_OTG_DOEPMSK_OTEPSPRM_MASK (0x1U << USB_OTG_DOEPMSK_OTEPSPRM_SHIFT) /* 0x00000020 */ 1014 #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_MASK /* Status Phase Received mask */ 1015 #define USB_OTG_DOEPMSK_B2BSTUP_SHIFT (6U) 1016 #define USB_OTG_DOEPMSK_B2BSTUP_MASK (0x1U << USB_OTG_DOEPMSK_B2BSTUP_SHIFT) /* 0x00000040 */ 1017 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_MASK 1018 #define USB_OTG_DOEPMSK_OPEM_SHIFT (8U) 1019 #define USB_OTG_DOEPMSK_OPEM_MASK (0x1U << USB_OTG_DOEPMSK_OPEM_SHIFT) /* 0x00000100 */ 1020 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_MASK /* OUT packet error mask */ 1021 #define USB_OTG_DOEPMSK_BOIM_SHIFT (9U) 1022 #define USB_OTG_DOEPMSK_BOIM_MASK (0x1U << USB_OTG_DOEPMSK_BOIM_SHIFT) /* 0x00000200 */ 1023 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_MASK /* BNA interrupt mask */ 1024 /******************** Bit definition for USB_OTG_DAINT register ********************/ 1025 #define USB_OTG_DAINT_IEPINT_SHIFT (0U) 1026 #define USB_OTG_DAINT_IEPINT_MASK (0xFFFFU << USB_OTG_DAINT_IEPINT_SHIFT) /* 0x0000FFFF */ 1027 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_MASK /* IN endpoint interrupt bits */ 1028 #define USB_OTG_DAINT_OEPINT_SHIFT (16U) 1029 #define USB_OTG_DAINT_OEPINT_MASK (0xFFFFU << USB_OTG_DAINT_OEPINT_SHIFT) /* 0xFFFF0000 */ 1030 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_MASK /* OUT endpoint interrupt bits */ 1031 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ 1032 #define USB_OTG_DAINTMSK_IEPM_SHIFT (0U) 1033 #define USB_OTG_DAINTMSK_IEPM_MASK (0xFFFFU << USB_OTG_DAINTMSK_IEPM_SHIFT) /* 0x0000FFFF */ 1034 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_MASK /* IN EP interrupt mask bits */ 1035 #define USB_OTG_DAINTMSK_OEPM_SHIFT (16U) 1036 #define USB_OTG_DAINTMSK_OEPM_MASK (0xFFFFU << USB_OTG_DAINTMSK_OEPM_SHIFT) /* 0xFFFF0000 */ 1037 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_MASK /* OUT EP interrupt mask bits */ 1038 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/ 1039 #define USB_OTG_DTHRCTL_NONISOTHREN_SHIFT (0U) 1040 #define USB_OTG_DTHRCTL_NONISOTHREN_MASK (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_SHIFT) /* 0x00000001 */ 1041 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_MASK 1042 #define USB_OTG_DTHRCTL_ISOTHREN_SHIFT (1U) 1043 #define USB_OTG_DTHRCTL_ISOTHREN_MASK (0x1U << USB_OTG_DTHRCTL_ISOTHREN_SHIFT) /* 0x00000002 */ 1044 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_MASK /* ISO IN endpoint threshold enable */ 1045 1046 #define USB_OTG_DTHRCTL_TXTHRLEN_SHIFT (2U) 1047 #define USB_OTG_DTHRCTL_TXTHRLEN_MASK (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_SHIFT) /* 0x000007FC */ 1048 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_MASK /* Transmit threshold length */ 1049 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_SHIFT) /* 0x00000004 */ 1050 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_SHIFT) /* 0x00000008 */ 1051 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_SHIFT) /* 0x00000010 */ 1052 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_SHIFT) /* 0x00000020 */ 1053 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_SHIFT) /* 0x00000040 */ 1054 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_SHIFT) /* 0x00000080 */ 1055 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_SHIFT) /* 0x00000100 */ 1056 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_SHIFT) /* 0x00000200 */ 1057 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_SHIFT) /* 0x00000400 */ 1058 #define USB_OTG_DTHRCTL_RXTHREN_SHIFT (16U) 1059 #define USB_OTG_DTHRCTL_RXTHREN_MASK (0x1U << USB_OTG_DTHRCTL_RXTHREN_SHIFT) /* 0x00010000 */ 1060 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_MASK /* Receive threshold enable */ 1061 1062 #define USB_OTG_DTHRCTL_RXTHRLEN_SHIFT (17U) 1063 #define USB_OTG_DTHRCTL_RXTHRLEN_MASK (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_SHIFT) /* 0x03FE0000 */ 1064 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_MASK /* Receive threshold length */ 1065 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_SHIFT) /* 0x00020000 */ 1066 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_SHIFT) /* 0x00040000 */ 1067 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_SHIFT) /* 0x00080000 */ 1068 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_SHIFT) /* 0x00100000 */ 1069 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_SHIFT) /* 0x00200000 */ 1070 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_SHIFT) /* 0x00400000 */ 1071 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_SHIFT) /* 0x00800000 */ 1072 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_SHIFT) /* 0x01000000 */ 1073 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_SHIFT) /* 0x02000000 */ 1074 #define USB_OTG_DTHRCTL_ARPEN_SHIFT (27U) 1075 #define USB_OTG_DTHRCTL_ARPEN_MASK (0x1U << USB_OTG_DTHRCTL_ARPEN_SHIFT) /* 0x08000000 */ 1076 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_MASK /* Arbiter parking enable */ 1077 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/ 1078 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_SHIFT (0U) 1079 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_MASK (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_SHIFT) /* 0x0000FFFF */ 1080 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_MASK 1081 /******************** Bit definition for USB_OTG_DEACHINT register ********************/ 1082 #define USB_OTG_DEACHINT_IEP1INT_SHIFT (1U) 1083 #define USB_OTG_DEACHINT_IEP1INT_MASK (0x1U << USB_OTG_DEACHINT_IEP1INT_SHIFT) /* 0x00000002 */ 1084 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_MASK /* IN endpoint 1interrupt bit */ 1085 #define USB_OTG_DEACHINT_OEP1INT_SHIFT (17U) 1086 #define USB_OTG_DEACHINT_OEP1INT_MASK (0x1U << USB_OTG_DEACHINT_OEP1INT_SHIFT) /* 0x00020000 */ 1087 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_MASK /* OUT endpoint 1 interrupt bit */ 1088 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/ 1089 #define USB_OTG_DEACHINTMSK_IEP1INTM_SHIFT (1U) 1090 #define USB_OTG_DEACHINTMSK_IEP1INTM_MASK (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_SHIFT) /* 0x00000002 */ 1091 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_MASK 1092 #define USB_OTG_DEACHINTMSK_OEP1INTM_SHIFT (17U) 1093 #define USB_OTG_DEACHINTMSK_OEP1INTM_MASK (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_SHIFT) /* 0x00020000 */ 1094 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_MASK 1095 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ 1096 #define USB_OTG_DIEPEACHMSK1_XFRCM_SHIFT (0U) 1097 #define USB_OTG_DIEPEACHMSK1_XFRCM_MASK (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_SHIFT) /* 0x00000001 */ 1098 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_MASK 1099 #define USB_OTG_DIEPEACHMSK1_EPDM_SHIFT (1U) 1100 #define USB_OTG_DIEPEACHMSK1_EPDM_MASK (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_SHIFT) /* 0x00000002 */ 1101 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_MASK /* Endpoint disabled interrupt mask */ 1102 #define USB_OTG_DIEPEACHMSK1_TOM_SHIFT (3U) 1103 #define USB_OTG_DIEPEACHMSK1_TOM_MASK (0x1U << USB_OTG_DIEPEACHMSK1_TOM_SHIFT) /* 0x00000008 */ 1104 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_MASK 1105 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_SHIFT (4U) 1106 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_MASK (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_SHIFT) /* 0x00000010 */ 1107 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_MASK 1108 #define USB_OTG_DIEPEACHMSK1_INEPNMM_SHIFT (5U) 1109 #define USB_OTG_DIEPEACHMSK1_INEPNMM_MASK (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_SHIFT) /* 0x00000020 */ 1110 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_MASK 1111 #define USB_OTG_DIEPEACHMSK1_INEPNEM_SHIFT (6U) 1112 #define USB_OTG_DIEPEACHMSK1_INEPNEM_MASK (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_SHIFT) /* 0x00000040 */ 1113 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_MASK 1114 #define USB_OTG_DIEPEACHMSK1_TXFURM_SHIFT (8U) 1115 #define USB_OTG_DIEPEACHMSK1_TXFURM_MASK (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_SHIFT) /* 0x00000100 */ 1116 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_MASK /* FIFO underrun mask */ 1117 #define USB_OTG_DIEPEACHMSK1_BIM_SHIFT (9U) 1118 #define USB_OTG_DIEPEACHMSK1_BIM_MASK (0x1U << USB_OTG_DIEPEACHMSK1_BIM_SHIFT) /* 0x00000200 */ 1119 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_MASK /* BNA interrupt mask */ 1120 #define USB_OTG_DIEPEACHMSK1_NAKM_SHIFT (13U) 1121 #define USB_OTG_DIEPEACHMSK1_NAKM_MASK (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_SHIFT) /* 0x00002000 */ 1122 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_MASK /* NAK interrupt mask */ 1123 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/ 1124 #define USB_OTG_DOEPEACHMSK1_XFRCM_SHIFT (0U) 1125 #define USB_OTG_DOEPEACHMSK1_XFRCM_MASK (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_SHIFT) /* 0x00000001 */ 1126 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_MASK 1127 #define USB_OTG_DOEPEACHMSK1_EPDM_SHIFT (1U) 1128 #define USB_OTG_DOEPEACHMSK1_EPDM_MASK (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_SHIFT) /* 0x00000002 */ 1129 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_MASK /* Endpoint disabled interrupt mask */ 1130 #define USB_OTG_DOEPEACHMSK1_TOM_SHIFT (3U) 1131 #define USB_OTG_DOEPEACHMSK1_TOM_MASK (0x1U << USB_OTG_DOEPEACHMSK1_TOM_SHIFT) /* 0x00000008 */ 1132 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_MASK /* Timeout condition mask */ 1133 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_SHIFT (4U) 1134 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_MASK (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_SHIFT) /* 0x00000010 */ 1135 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_MASK 1136 #define USB_OTG_DOEPEACHMSK1_INEPNMM_SHIFT (5U) 1137 #define USB_OTG_DOEPEACHMSK1_INEPNMM_MASK (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_SHIFT) /* 0x00000020 */ 1138 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_MASK 1139 #define USB_OTG_DOEPEACHMSK1_INEPNEM_SHIFT (6U) 1140 #define USB_OTG_DOEPEACHMSK1_INEPNEM_MASK (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_SHIFT) /* 0x00000040 */ 1141 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_MASK 1142 #define USB_OTG_DOEPEACHMSK1_TXFURM_SHIFT (8U) 1143 #define USB_OTG_DOEPEACHMSK1_TXFURM_MASK (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_SHIFT) /* 0x00000100 */ 1144 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_MASK /* OUT packet error mask */ 1145 #define USB_OTG_DOEPEACHMSK1_BIM_SHIFT (9U) 1146 #define USB_OTG_DOEPEACHMSK1_BIM_MASK (0x1U << USB_OTG_DOEPEACHMSK1_BIM_SHIFT) /* 0x00000200 */ 1147 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_MASK /* BNA interrupt mask */ 1148 #define USB_OTG_DOEPEACHMSK1_BERRM_SHIFT (12U) 1149 #define USB_OTG_DOEPEACHMSK1_BERRM_MASK (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_SHIFT) /* 0x00001000 */ 1150 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_MASK /* Bubble error interrupt mask */ 1151 #define USB_OTG_DOEPEACHMSK1_NAKM_SHIFT (13U) 1152 #define USB_OTG_DOEPEACHMSK1_NAKM_MASK (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_SHIFT) /* 0x00002000 */ 1153 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_MASK /* NAK interrupt mask */ 1154 #define USB_OTG_DOEPEACHMSK1_NYETM_SHIFT (14U) 1155 #define USB_OTG_DOEPEACHMSK1_NYETM_MASK (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_SHIFT) /* 0x00004000 */ 1156 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_MASK /* NYET interrupt mask */ 1157 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ 1158 #define USB_OTG_DIEPCTL_MPSIZ_SHIFT (0U) 1159 #define USB_OTG_DIEPCTL_MPSIZ_MASK (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_SHIFT) /* 0x000007FF */ 1160 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_MASK /* Maximum packet size */ 1161 #define USB_OTG_DIEPCTL_USBAEP_SHIFT (15U) 1162 #define USB_OTG_DIEPCTL_USBAEP_MASK (0x1U << USB_OTG_DIEPCTL_USBAEP_SHIFT) /* 0x00008000 */ 1163 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_MASK /* USB active endpoint */ 1164 #define USB_OTG_DIEPCTL_EONUM_DPID_SHIFT (16U) 1165 #define USB_OTG_DIEPCTL_EONUM_DPID_MASK (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_SHIFT) /* 0x00010000 */ 1166 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_MASK /* Even/odd frame */ 1167 #define USB_OTG_DIEPCTL_NAKSTS_SHIFT (17U) 1168 #define USB_OTG_DIEPCTL_NAKSTS_MASK (0x1U << USB_OTG_DIEPCTL_NAKSTS_SHIFT) /* 0x00020000 */ 1169 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_MASK /* NAK status */ 1170 #define USB_OTG_DIEPCTL_EPTYP_SHIFT (18U) 1171 #define USB_OTG_DIEPCTL_EPTYP_MASK (0x3U << USB_OTG_DIEPCTL_EPTYP_SHIFT) /* 0x000C0000 */ 1172 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_MASK /* Endpoint type */ 1173 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_SHIFT) /* 0x00040000 */ 1174 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_SHIFT) /* 0x00080000 */ 1175 #define USB_OTG_DIEPCTL_STALL_SHIFT (21U) 1176 #define USB_OTG_DIEPCTL_STALL_MASK (0x1U << USB_OTG_DIEPCTL_STALL_SHIFT) /* 0x00200000 */ 1177 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_MASK /* STALL handshake */ 1178 #define USB_OTG_DIEPCTL_TXFNUM_SHIFT (22U) 1179 #define USB_OTG_DIEPCTL_TXFNUM_MASK (0xFU << USB_OTG_DIEPCTL_TXFNUM_SHIFT) /* 0x03C00000 */ 1180 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_MASK /* TxFIFO number */ 1181 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_SHIFT) /* 0x00400000 */ 1182 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_SHIFT) /* 0x00800000 */ 1183 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_SHIFT) /* 0x01000000 */ 1184 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_SHIFT) /* 0x02000000 */ 1185 #define USB_OTG_DIEPCTL_CNAK_SHIFT (26U) 1186 #define USB_OTG_DIEPCTL_CNAK_MASK (0x1U << USB_OTG_DIEPCTL_CNAK_SHIFT) /* 0x04000000 */ 1187 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_MASK /* Clear NAK */ 1188 #define USB_OTG_DIEPCTL_SNAK_SHIFT (27U) 1189 #define USB_OTG_DIEPCTL_SNAK_MASK (0x1U << USB_OTG_DIEPCTL_SNAK_SHIFT) /* 0x08000000 */ 1190 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_MASK /* Set NAK */ 1191 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_SHIFT (28U) 1192 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_MASK (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_SHIFT) /* 0x10000000 */ 1193 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_MASK /* Set DATA0 PID */ 1194 #define USB_OTG_DIEPCTL_SODDFRM_SHIFT (29U) 1195 #define USB_OTG_DIEPCTL_SODDFRM_MASK (0x1U << USB_OTG_DIEPCTL_SODDFRM_SHIFT) /* 0x20000000 */ 1196 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_MASK /* Set odd frame */ 1197 #define USB_OTG_DIEPCTL_EPDIS_SHIFT (30U) 1198 #define USB_OTG_DIEPCTL_EPDIS_MASK (0x1U << USB_OTG_DIEPCTL_EPDIS_SHIFT) /* 0x40000000 */ 1199 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_MASK /* Endpoint disable */ 1200 #define USB_OTG_DIEPCTL_EPENA_SHIFT (31U) 1201 #define USB_OTG_DIEPCTL_EPENA_MASK (0x1U << USB_OTG_DIEPCTL_EPENA_SHIFT) /* 0x80000000 */ 1202 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_MASK /* Endpoint enable */ 1203 /******************** Bit definition for USB_OTG_DIEPINT register ********************/ 1204 #define USB_OTG_DIEPINT_XFRC_SHIFT (0U) 1205 #define USB_OTG_DIEPINT_XFRC_MASK (0x1U << USB_OTG_DIEPINT_XFRC_SHIFT) /* 0x00000001 */ 1206 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_MASK /* Transfer completed interrupt */ 1207 #define USB_OTG_DIEPINT_EPDISD_SHIFT (1U) 1208 #define USB_OTG_DIEPINT_EPDISD_MASK (0x1U << USB_OTG_DIEPINT_EPDISD_SHIFT) /* 0x00000002 */ 1209 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_MASK /* Endpoint disabled interrupt */ 1210 #define USB_OTG_DIEPINT_TOC_SHIFT (3U) 1211 #define USB_OTG_DIEPINT_TOC_MASK (0x1U << USB_OTG_DIEPINT_TOC_SHIFT) /* 0x00000008 */ 1212 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_MASK /* Timeout condition */ 1213 #define USB_OTG_DIEPINT_ITTXFE_SHIFT (4U) 1214 #define USB_OTG_DIEPINT_ITTXFE_MASK (0x1U << USB_OTG_DIEPINT_ITTXFE_SHIFT) /* 0x00000010 */ 1215 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_MASK 1216 #define USB_OTG_DIEPINT_INEPNE_SHIFT (6U) 1217 #define USB_OTG_DIEPINT_INEPNE_MASK (0x1U << USB_OTG_DIEPINT_INEPNE_SHIFT) /* 0x00000040 */ 1218 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_MASK /* IN endpoint NAK effective */ 1219 #define USB_OTG_DIEPINT_TXFE_SHIFT (7U) 1220 #define USB_OTG_DIEPINT_TXFE_MASK (0x1U << USB_OTG_DIEPINT_TXFE_SHIFT) /* 0x00000080 */ 1221 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_MASK /* Transmit FIFO empty */ 1222 #define USB_OTG_DIEPINT_TXFIFOUDRN_SHIFT (8U) 1223 #define USB_OTG_DIEPINT_TXFIFOUDRN_MASK (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_SHIFT) /* 0x00000100 */ 1224 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_MASK /* Transmit Fifo Underrun */ 1225 #define USB_OTG_DIEPINT_BNA_SHIFT (9U) 1226 #define USB_OTG_DIEPINT_BNA_MASK (0x1U << USB_OTG_DIEPINT_BNA_SHIFT) /* 0x00000200 */ 1227 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_MASK /* Buffer not available interrupt */ 1228 #define USB_OTG_DIEPINT_PKTDRPSTS_SHIFT (11U) 1229 #define USB_OTG_DIEPINT_PKTDRPSTS_MASK (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_SHIFT) /* 0x00000800 */ 1230 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_MASK /* Packet dropped status */ 1231 #define USB_OTG_DIEPINT_BERR_SHIFT (12U) 1232 #define USB_OTG_DIEPINT_BERR_MASK (0x1U << USB_OTG_DIEPINT_BERR_SHIFT) /* 0x00001000 */ 1233 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_MASK /* Babble error interrupt */ 1234 #define USB_OTG_DIEPINT_NAK_SHIFT (13U) 1235 #define USB_OTG_DIEPINT_NAK_MASK (0x1U << USB_OTG_DIEPINT_NAK_SHIFT) /* 0x00002000 */ 1236 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_MASK /* NAK interrupt */ 1237 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/ 1238 #define USB_OTG_DIEPTSIZ_XFRSIZ_SHIFT (0U) 1239 #define USB_OTG_DIEPTSIZ_XFRSIZ_MASK (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_SHIFT) /* 0x0007FFFF */ 1240 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_MASK /* Transfer size */ 1241 #define USB_OTG_DIEPTSIZ_PKTCNT_SHIFT (19U) 1242 #define USB_OTG_DIEPTSIZ_PKTCNT_MASK (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_SHIFT) /* 0x1FF80000 */ 1243 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_MASK /* Packet count */ 1244 #define USB_OTG_DIEPTSIZ_MULCNT_SHIFT (29U) 1245 #define USB_OTG_DIEPTSIZ_MULCNT_MASK (0x3U << USB_OTG_DIEPTSIZ_MULCNT_SHIFT) /* 0x60000000 */ 1246 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_MASK /* Packet count */ 1247 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ 1248 #define USB_OTG_DIEPDMA_DMAADDR_SHIFT (0U) 1249 #define USB_OTG_DIEPDMA_DMAADDR_MASK (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_SHIFT) /* 0xFFFFFFFF */ 1250 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_MASK /* DMA address */ 1251 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/ 1252 #define USB_OTG_DTXFSTS_INEPTFSAV_SHIFT (0U) 1253 #define USB_OTG_DTXFSTS_INEPTFSAV_MASK (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_SHIFT) /* 0x0000FFFF */ 1254 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_MASK 1255 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/ 1256 #define USB_OTG_DOEPCTL_MPSIZ_SHIFT (0U) 1257 #define USB_OTG_DOEPCTL_MPSIZ_MASK (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_SHIFT) /* 0x000007FF */ 1258 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_MASK /* Maximum packet size */ 1259 #define USB_OTG_DOEPCTL_USBAEP_SHIFT (15U) 1260 #define USB_OTG_DOEPCTL_USBAEP_MASK (0x1U << USB_OTG_DOEPCTL_USBAEP_SHIFT) /* 0x00008000 */ 1261 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_MASK /* USB active endpoint */ 1262 #define USB_OTG_DOEPCTL_NAKSTS_SHIFT (17U) 1263 #define USB_OTG_DOEPCTL_NAKSTS_MASK (0x1U << USB_OTG_DOEPCTL_NAKSTS_SHIFT) /* 0x00020000 */ 1264 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_MASK /* NAK status */ 1265 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_SHIFT (28U) 1266 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_MASK (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_SHIFT) /* 0x10000000 */ 1267 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_MASK /* Set DATA0 PID */ 1268 #define USB_OTG_DOEPCTL_SODDFRM_SHIFT (29U) 1269 #define USB_OTG_DOEPCTL_SODDFRM_MASK (0x1U << USB_OTG_DOEPCTL_SODDFRM_SHIFT) /* 0x20000000 */ 1270 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_MASK /* Set odd frame */ 1271 #define USB_OTG_DOEPCTL_EPTYP_SHIFT (18U) 1272 #define USB_OTG_DOEPCTL_EPTYP_MASK (0x3U << USB_OTG_DOEPCTL_EPTYP_SHIFT) /* 0x000C0000 */ 1273 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_MASK /* Endpoint type */ 1274 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_SHIFT) /* 0x00040000 */ 1275 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_SHIFT) /* 0x00080000 */ 1276 #define USB_OTG_DOEPCTL_SNPM_SHIFT (20U) 1277 #define USB_OTG_DOEPCTL_SNPM_MASK (0x1U << USB_OTG_DOEPCTL_SNPM_SHIFT) /* 0x00100000 */ 1278 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_MASK /* Snoop mode */ 1279 #define USB_OTG_DOEPCTL_STALL_SHIFT (21U) 1280 #define USB_OTG_DOEPCTL_STALL_MASK (0x1U << USB_OTG_DOEPCTL_STALL_SHIFT) /* 0x00200000 */ 1281 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_MASK /* STALL handshake */ 1282 #define USB_OTG_DOEPCTL_CNAK_SHIFT (26U) 1283 #define USB_OTG_DOEPCTL_CNAK_MASK (0x1U << USB_OTG_DOEPCTL_CNAK_SHIFT) /* 0x04000000 */ 1284 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_MASK /* Clear NAK */ 1285 #define USB_OTG_DOEPCTL_SNAK_SHIFT (27U) 1286 #define USB_OTG_DOEPCTL_SNAK_MASK (0x1U << USB_OTG_DOEPCTL_SNAK_SHIFT) /* 0x08000000 */ 1287 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_MASK /* Set NAK */ 1288 #define USB_OTG_DOEPCTL_EPDIS_SHIFT (30U) 1289 #define USB_OTG_DOEPCTL_EPDIS_MASK (0x1U << USB_OTG_DOEPCTL_EPDIS_SHIFT) /* 0x40000000 */ 1290 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_MASK /* Endpoint disable */ 1291 #define USB_OTG_DOEPCTL_EPENA_SHIFT (31U) 1292 #define USB_OTG_DOEPCTL_EPENA_MASK (0x1U << USB_OTG_DOEPCTL_EPENA_SHIFT) /* 0x80000000 */ 1293 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_MASK /* Endpoint enable */ 1294 /******************** Bit definition for USB_OTG_DOEPINT register ********************/ 1295 #define USB_OTG_DOEPINT_XFRC_SHIFT (0U) 1296 #define USB_OTG_DOEPINT_XFRC_MASK (0x1U << USB_OTG_DOEPINT_XFRC_SHIFT) /* 0x00000001 */ 1297 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_MASK /* Transfer completed interrupt */ 1298 #define USB_OTG_DOEPINT_EPDISD_SHIFT (1U) 1299 #define USB_OTG_DOEPINT_EPDISD_MASK (0x1U << USB_OTG_DOEPINT_EPDISD_SHIFT) /* 0x00000002 */ 1300 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_MASK /* Endpoint disabled interrupt */ 1301 #define USB_OTG_DOEPINT_STUP_SHIFT (3U) 1302 #define USB_OTG_DOEPINT_STUP_MASK (0x1U << USB_OTG_DOEPINT_STUP_SHIFT) /* 0x00000008 */ 1303 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_MASK /* SETUP phase done */ 1304 #define USB_OTG_DOEPINT_OTEPDIS_SHIFT (4U) 1305 #define USB_OTG_DOEPINT_OTEPDIS_MASK (0x1U << USB_OTG_DOEPINT_OTEPDIS_SHIFT) /* 0x00000010 */ 1306 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_MASK 1307 #define USB_OTG_DOEPINT_OTEPSPR_SHIFT (5U) 1308 #define USB_OTG_DOEPINT_OTEPSPR_MASK (0x1U << USB_OTG_DOEPINT_OTEPSPR_SHIFT) /* 0x00000020 */ 1309 #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_MASK 1310 #define USB_OTG_DOEPINT_B2BSTUP_SHIFT (6U) 1311 #define USB_OTG_DOEPINT_B2BSTUP_MASK (0x1U << USB_OTG_DOEPINT_B2BSTUP_SHIFT) /* 0x00000040 */ 1312 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_MASK 1313 #define USB_OTG_DOEPINT_NYET_SHIFT (14U) 1314 #define USB_OTG_DOEPINT_NYET_MASK (0x1U << USB_OTG_DOEPINT_NYET_SHIFT) /* 0x00004000 */ 1315 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_MASK /* NYET interrupt */ 1316 #define USB_OTG_DOEPINT_STUPPKTRCVD_SHIFT (15U) 1317 #define USB_OTG_DOEPINT_STUPPKTRCVD_MASK (0x1U << USB_OTG_DOEPINT_STUPPKTRCVD_SHIFT) /* 0x00008000 */ 1318 #define USB_OTG_DOEPINT_STUPPKTRCVD USB_OTG_DOEPINT_STUPPKTRCVD_MASK /* STUPPKTRCVD interrupt */ 1319 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ 1320 #define USB_OTG_DOEPTSIZ_XFRSIZ_SHIFT (0U) 1321 #define USB_OTG_DOEPTSIZ_XFRSIZ_MASK (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_SHIFT) /* 0x0007FFFF */ 1322 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_MASK /* Transfer size */ 1323 #define USB_OTG_DOEPTSIZ_PKTCNT_SHIFT (19U) 1324 #define USB_OTG_DOEPTSIZ_PKTCNT_MASK (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_SHIFT) /* 0x1FF80000 */ 1325 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_MASK /* Packet count */ 1326 #define USB_OTG_DOEPTSIZ_STUPCNT_SHIFT (29U) 1327 #define USB_OTG_DOEPTSIZ_STUPCNT_MASK (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_SHIFT) /* 0x60000000 */ 1328 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_MASK /* SETUP packet count */ 1329 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_SHIFT) /* 0x20000000 */ 1330 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_SHIFT) /* 0x40000000 */ 1331 /******************** Bit definition for PCGCCTL register ********************/ 1332 #define USB_OTG_PCGCCTL_STOPCLK_SHIFT (0U) 1333 #define USB_OTG_PCGCCTL_STOPCLK_MASK (0x1U << USB_OTG_PCGCCTL_STOPCLK_SHIFT) /* 0x00000001 */ 1334 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_MASK /* SETUP packet count */ 1335 #define USB_OTG_PCGCCTL_GATECLK_SHIFT (1U) 1336 #define USB_OTG_PCGCCTL_GATECLK_MASK (0x1U << USB_OTG_PCGCCTL_GATECLK_SHIFT) /* 0x00000002 */ 1337 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_MASK /* Gate Hclk */ 1338 1339 #ifdef __cplusplus 1340 } 1341 #endif /* __cplusplus */ 1342 #endif /* __RK2206_USB_H */ 1343