1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) Rockchip Electronics Co.Ltd
4 * Author:
5 * Algea Cao <algea.cao@rock-chips.com>
6 */
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/err.h>
11 #include <linux/extcon-provider.h>
12 #include <linux/extcon.h>
13 #include <linux/hdmi.h>
14 #include <linux/irq.h>
15 #include <linux/module.h>
16 #include <linux/mutex.h>
17 #include <linux/of_device.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/regmap.h>
20 #include <linux/spinlock.h>
21
22 #include <drm/drm_atomic.h>
23 #include <drm/drm_atomic_helper.h>
24 #include <drm/drm_crtc_helper.h>
25 #include <drm/drm_dsc.h>
26 #include <drm/drm_edid.h>
27 #include <drm/drm_encoder_slave.h>
28 #include <drm/drm_of.h>
29 #include <drm/drm_print.h>
30 #include <drm/drm_probe_helper.h>
31 #include <drm/drm_scdc_helper.h>
32 #include <drm/bridge/dw_hdmi.h>
33
34 #include <uapi/linux/media-bus-format.h>
35 #include <uapi/linux/videodev2.h>
36
37 #include "dw-hdmi-qp-audio.h"
38 #include "dw-hdmi-qp.h"
39
40 #include <media/cec-notifier.h>
41
42 #define DDC_CI_ADDR 0x37
43 #define DDC_SEGMENT_ADDR 0x30
44
45 #define HDMI_EDID_LEN 512
46
47 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
48 #define SCDC_MIN_SOURCE_VERSION 0x1
49
50 #define HDMI14_MAX_TMDSCLK 340000000
51
52 static const unsigned int dw_hdmi_cable[] = {
53 EXTCON_DISP_HDMI,
54 EXTCON_NONE,
55 };
56
57 /*
58 * Unless otherwise noted, entries in this table are 100% optimization.
59 * Values can be obtained from hdmi_compute_n() but that function is
60 * slow so we pre-compute values we expect to see.
61 *
62 * All 32k and 48k values are expected to be the same (due to the way
63 * the math works) for any rate that's an exact kHz.
64 */
65 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = {
66 { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, },
67 { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, },
68 { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
69 { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, },
70 { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, },
71 { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
72 { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
73 { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
74 { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
75 { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
76 { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
77 { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
78 { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
79 { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
80 { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, },
81 { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
82 { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, },
83 { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
84 { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
85 { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, },
86 { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
87 { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
88 { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
89 { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
90 { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
91 { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
92 { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
93 { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
94 { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
95 { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
96 { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, },
97 { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
98 { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
99 { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
100 { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
101 { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
102 { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
103
104 /* For 297 MHz+ HDMI spec have some other rule for setting N */
105 { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, },
106 { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, },
107
108 /* End of table */
109 { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, },
110 };
111
112 static const struct drm_display_mode dw_hdmi_default_modes[] = {
113 /* 16 - 1920x1080@60Hz 16:9 */
114 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
115 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
116 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
117 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
118 /* 2 - 720x480@60Hz 4:3 */
119 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
120 798, 858, 0, 480, 489, 495, 525, 0,
121 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
122 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
123 /* 4 - 1280x720@60Hz 16:9 */
124 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
125 1430, 1650, 0, 720, 725, 730, 750, 0,
126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
127 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
128 /* 31 - 1920x1080@50Hz 16:9 */
129 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
130 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
131 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
132 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
133 /* 19 - 1280x720@50Hz 16:9 */
134 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
135 1760, 1980, 0, 720, 725, 730, 750, 0,
136 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
137 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
138 /* 17 - 720x576@50Hz 4:3 */
139 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
140 796, 864, 0, 576, 581, 586, 625, 0,
141 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
142 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
143 /* 2 - 720x480@60Hz 4:3 */
144 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
145 798, 858, 0, 480, 489, 495, 525, 0,
146 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
147 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
148 };
149
150 enum frl_mask {
151 FRL_3GBPS_3LANE = 1,
152 FRL_6GBPS_3LANE,
153 FRL_6GBPS_4LANE,
154 FRL_8GBPS_4LANE,
155 FRL_10GBPS_4LANE,
156 FRL_12GBPS_4LANE,
157 };
158
159 struct hdmi_vmode_qp {
160 bool mdataenablepolarity;
161
162 unsigned int previous_pixelclock;
163 unsigned long mpixelclock;
164 unsigned int mpixelrepetitioninput;
165 unsigned int mpixelrepetitionoutput;
166 unsigned long previous_tmdsclock;
167 unsigned int mtmdsclock;
168 };
169
170 struct hdmi_qp_data_info {
171 unsigned int enc_in_bus_format;
172 unsigned int enc_out_bus_format;
173 unsigned int enc_in_encoding;
174 unsigned int enc_out_encoding;
175 unsigned int quant_range;
176 unsigned int pix_repet_factor;
177 struct hdmi_vmode_qp video_mode;
178 bool update;
179 };
180
181 struct dw_hdmi_qp_i2c {
182 struct i2c_adapter adap;
183
184 struct mutex lock; /* used to serialize data transfers */
185 struct completion cmp;
186 u32 stat;
187
188 u8 slave_reg;
189 bool is_regaddr;
190 bool is_segment;
191
192 unsigned int scl_high_ns;
193 unsigned int scl_low_ns;
194 };
195
196 struct dw_hdmi_phy_data {
197 enum dw_hdmi_phy_type type;
198 const char *name;
199 unsigned int gen;
200 bool has_svsret;
201 int (*configure)(struct dw_hdmi_qp *hdmi,
202 const struct dw_hdmi_plat_data *pdata,
203 unsigned long mpixelclock);
204 };
205
206 struct dw_hdmi_qp {
207 struct drm_connector connector;
208 struct drm_bridge bridge;
209 struct platform_device *hdcp_dev;
210 struct platform_device *audio;
211
212 struct device *dev;
213 struct dw_hdmi_qp_i2c *i2c;
214
215 struct hdmi_qp_data_info hdmi_data;
216 const struct dw_hdmi_plat_data *plat_data;
217
218 int vic;
219 int main_irq;
220 int avp_irq;
221 int earc_irq;
222
223 u8 edid[HDMI_EDID_LEN];
224
225 struct {
226 const struct dw_hdmi_qp_phy_ops *ops;
227 const char *name;
228 void *data;
229 bool enabled;
230 } phy;
231
232 struct drm_display_mode previous_mode;
233
234 struct i2c_adapter *ddc;
235 void __iomem *regs;
236 bool sink_is_hdmi;
237 bool sink_has_audio;
238 bool hpd_state;
239
240 struct mutex mutex; /* for state below and previous_mode */
241 struct drm_connector *curr_conn;/* current connector (only valid when !disabled) */
242 enum drm_connector_force force; /* mutex-protected force state */
243 bool disabled; /* DRM has disabled our bridge */
244 bool bridge_is_on; /* indicates the bridge is on */
245 bool rxsense; /* rxsense state */
246 u8 phy_mask; /* desired phy int mask settings */
247 u8 mc_clkdis; /* clock disable register */
248
249 u32 scdc_intr;
250 u32 flt_intr;
251 u32 earc_intr;
252
253 spinlock_t audio_lock;
254 struct mutex audio_mutex;
255 unsigned int sample_rate;
256 unsigned int audio_cts;
257 unsigned int audio_n;
258 bool audio_enable;
259 void (*enable_audio)(struct dw_hdmi_qp *hdmi);
260 void (*disable_audio)(struct dw_hdmi_qp *hdmi);
261
262 struct dentry *debugfs_dir;
263 bool scramble_low_rates;
264
265 struct extcon_dev *extcon;
266
267 struct regmap *regm;
268
269 bool initialized; /* hdmi is enabled before bind */
270 struct completion flt_cmp;
271 struct completion earc_cmp;
272
273 struct cec_notifier *cec_notifier;
274 struct cec_adapter *cec_adap;
275 struct mutex cec_notifier_mutex;
276
277 hdmi_codec_plugged_cb plugged_cb;
278 struct device *codec_dev;
279 enum drm_connector_status last_connector_result;
280 };
281
hdmi_writel(struct dw_hdmi_qp * hdmi,u32 val,int offset)282 static inline void hdmi_writel(struct dw_hdmi_qp *hdmi, u32 val, int offset)
283 {
284 regmap_write(hdmi->regm, offset, val);
285 }
286
hdmi_readl(struct dw_hdmi_qp * hdmi,int offset)287 static inline u32 hdmi_readl(struct dw_hdmi_qp *hdmi, int offset)
288 {
289 unsigned int val = 0;
290
291 regmap_read(hdmi->regm, offset, &val);
292
293 return val;
294 }
295
handle_plugged_change(struct dw_hdmi_qp * hdmi,bool plugged)296 static void handle_plugged_change(struct dw_hdmi_qp *hdmi, bool plugged)
297 {
298 if (hdmi->plugged_cb && hdmi->codec_dev)
299 hdmi->plugged_cb(hdmi->codec_dev, plugged);
300 }
301
dw_hdmi_qp_set_plugged_cb(struct dw_hdmi_qp * hdmi,hdmi_codec_plugged_cb fn,struct device * codec_dev)302 int dw_hdmi_qp_set_plugged_cb(struct dw_hdmi_qp *hdmi, hdmi_codec_plugged_cb fn,
303 struct device *codec_dev)
304 {
305 bool plugged;
306
307 mutex_lock(&hdmi->mutex);
308 hdmi->plugged_cb = fn;
309 hdmi->codec_dev = codec_dev;
310 plugged = hdmi->last_connector_result == connector_status_connected;
311 handle_plugged_change(hdmi, plugged);
312 mutex_unlock(&hdmi->mutex);
313
314 return 0;
315 }
316 EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_plugged_cb);
317
hdmi_modb(struct dw_hdmi_qp * hdmi,u32 data,u32 mask,u32 reg)318 static void hdmi_modb(struct dw_hdmi_qp *hdmi, u32 data, u32 mask, u32 reg)
319 {
320 regmap_update_bits(hdmi->regm, reg, mask, data);
321 }
322
hdmi_set_cts_n(struct dw_hdmi_qp * hdmi,unsigned int cts,unsigned int n)323 static void hdmi_set_cts_n(struct dw_hdmi_qp *hdmi, unsigned int cts,
324 unsigned int n)
325 {
326 /* Set N */
327 hdmi_modb(hdmi, n, AUDPKT_ACR_N_VALUE, AUDPKT_ACR_CONTROL0);
328
329 /* Set CTS */
330 if (cts)
331 hdmi_modb(hdmi, AUDPKT_ACR_CTS_OVR_EN, AUDPKT_ACR_CTS_OVR_EN_MSK,
332 AUDPKT_ACR_CONTROL1);
333 else
334 hdmi_modb(hdmi, 0, AUDPKT_ACR_CTS_OVR_EN_MSK,
335 AUDPKT_ACR_CONTROL1);
336
337 hdmi_modb(hdmi, AUDPKT_ACR_CTS_OVR_VAL(cts), AUDPKT_ACR_CTS_OVR_VAL_MSK,
338 AUDPKT_ACR_CONTROL1);
339 }
340
hdmi_match_tmds_n_table(struct dw_hdmi_qp * hdmi,unsigned long pixel_clk,unsigned long freq)341 static int hdmi_match_tmds_n_table(struct dw_hdmi_qp *hdmi,
342 unsigned long pixel_clk,
343 unsigned long freq)
344 {
345 const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;
346 const struct dw_hdmi_audio_tmds_n *tmds_n = NULL;
347 int i;
348
349 if (plat_data->tmds_n_table) {
350 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) {
351 if (pixel_clk == plat_data->tmds_n_table[i].tmds) {
352 tmds_n = &plat_data->tmds_n_table[i];
353 break;
354 }
355 }
356 }
357
358 if (tmds_n == NULL) {
359 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) {
360 if (pixel_clk == common_tmds_n_table[i].tmds) {
361 tmds_n = &common_tmds_n_table[i];
362 break;
363 }
364 }
365 }
366
367 if (tmds_n == NULL)
368 return -ENOENT;
369
370 switch (freq) {
371 case 32000:
372 return tmds_n->n_32k;
373 case 44100:
374 case 88200:
375 case 176400:
376 return (freq / 44100) * tmds_n->n_44k1;
377 case 48000:
378 case 96000:
379 case 192000:
380 return (freq / 48000) * tmds_n->n_48k;
381 default:
382 return -ENOENT;
383 }
384 }
385
hdmi_audio_math_diff(unsigned int freq,unsigned int n,unsigned int pixel_clk)386 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n,
387 unsigned int pixel_clk)
388 {
389 u64 final, diff;
390 u64 cts;
391
392 final = (u64)pixel_clk * n;
393
394 cts = final;
395 do_div(cts, 128 * freq);
396
397 diff = final - (u64)cts * (128 * freq);
398
399 return diff;
400 }
401
hdmi_compute_n(struct dw_hdmi_qp * hdmi,unsigned long pixel_clk,unsigned long freq)402 static unsigned int hdmi_compute_n(struct dw_hdmi_qp *hdmi,
403 unsigned long pixel_clk,
404 unsigned long freq)
405 {
406 unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500);
407 unsigned int max_n = (128 * freq) / 300;
408 unsigned int ideal_n = (128 * freq) / 1000;
409 unsigned int best_n_distance = ideal_n;
410 unsigned int best_n = 0;
411 u64 best_diff = U64_MAX;
412 int n;
413
414 /* If the ideal N could satisfy the audio math, then just take it */
415 if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0)
416 return ideal_n;
417
418 for (n = min_n; n <= max_n; n++) {
419 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk);
420
421 if (diff < best_diff || (diff == best_diff &&
422 abs(n - ideal_n) < best_n_distance)) {
423 best_n = n;
424 best_diff = diff;
425 best_n_distance = abs(best_n - ideal_n);
426 }
427
428 /*
429 * The best N already satisfy the audio math, and also be
430 * the closest value to ideal N, so just cut the loop.
431 */
432 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance))
433 break;
434 }
435
436 return best_n;
437 }
438
hdmi_find_n(struct dw_hdmi_qp * hdmi,unsigned long pixel_clk,unsigned long sample_rate)439 static unsigned int hdmi_find_n(struct dw_hdmi_qp *hdmi, unsigned long pixel_clk,
440 unsigned long sample_rate)
441 {
442 int n;
443
444 n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate);
445 if (n > 0)
446 return n;
447
448 dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n",
449 pixel_clk);
450
451 return hdmi_compute_n(hdmi, pixel_clk, sample_rate);
452 }
453
454 /*
455 * When transmitting IEC60958 linear PCM audio, these registers allow to
456 * configure the channel status information of all the channel status
457 * bits in the IEC60958 frame. For the moment this configuration is only
458 * used when the I2S audio interface, General Purpose Audio (GPA),
459 * or AHB audio DMA (AHBAUDDMA) interface is active
460 * (for S/PDIF interface this information comes from the stream).
461 */
dw_hdmi_qp_set_channel_status(struct dw_hdmi_qp * hdmi,u8 * channel_status)462 void dw_hdmi_qp_set_channel_status(struct dw_hdmi_qp *hdmi,
463 u8 *channel_status)
464 {
465 /* Set channel status */
466 hdmi_writel(hdmi, channel_status[3] | (channel_status[4] << 8),
467 AUDPKT_CHSTATUS_OVR1);
468 hdmi_modb(hdmi, AUDPKT_CHSTATUS_OVR_EN,
469 AUDPKT_CHSTATUS_OVR_EN_MASK, AUDPKT_CONTROL0);
470 }
471 EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_channel_status);
472
hdmi_set_clk_regenerator(struct dw_hdmi_qp * hdmi,unsigned long pixel_clk,unsigned int sample_rate)473 static void hdmi_set_clk_regenerator(struct dw_hdmi_qp *hdmi,
474 unsigned long pixel_clk, unsigned int sample_rate)
475 {
476 unsigned int n = 0, cts = 0;
477
478 n = hdmi_find_n(hdmi, pixel_clk, sample_rate);
479
480 spin_lock_irq(&hdmi->audio_lock);
481 hdmi->audio_n = n;
482 hdmi->audio_cts = cts;
483 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
484 spin_unlock_irq(&hdmi->audio_lock);
485 }
486
hdmi_init_clk_regenerator(struct dw_hdmi_qp * hdmi)487 static void hdmi_init_clk_regenerator(struct dw_hdmi_qp *hdmi)
488 {
489 mutex_lock(&hdmi->audio_mutex);
490 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
491 mutex_unlock(&hdmi->audio_mutex);
492 }
493
hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi_qp * hdmi)494 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi_qp *hdmi)
495 {
496 mutex_lock(&hdmi->audio_mutex);
497 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
498 hdmi->sample_rate);
499 mutex_unlock(&hdmi->audio_mutex);
500 }
501
dw_hdmi_qp_set_sample_rate(struct dw_hdmi_qp * hdmi,unsigned int rate)502 void dw_hdmi_qp_set_sample_rate(struct dw_hdmi_qp *hdmi, unsigned int rate)
503 {
504 mutex_lock(&hdmi->audio_mutex);
505 hdmi->sample_rate = rate;
506 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
507 hdmi->sample_rate);
508 mutex_unlock(&hdmi->audio_mutex);
509 }
510 EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_sample_rate);
511
dw_hdmi_qp_set_channel_count(struct dw_hdmi_qp * hdmi,unsigned int cnt)512 void dw_hdmi_qp_set_channel_count(struct dw_hdmi_qp *hdmi, unsigned int cnt)
513 {
514 }
515 EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_channel_count);
516
dw_hdmi_qp_set_channel_allocation(struct dw_hdmi_qp * hdmi,unsigned int ca)517 void dw_hdmi_qp_set_channel_allocation(struct dw_hdmi_qp *hdmi, unsigned int ca)
518 {
519 }
520 EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_channel_allocation);
521
hdmi_enable_audio_clk(struct dw_hdmi_qp * hdmi,bool enable)522 static void hdmi_enable_audio_clk(struct dw_hdmi_qp *hdmi, bool enable)
523 {
524 if (enable)
525 hdmi_modb(hdmi, 0,
526 AVP_DATAPATH_PACKET_AUDIO_SWDISABLE, GLOBAL_SWDISABLE);
527 else
528 hdmi_modb(hdmi, AVP_DATAPATH_PACKET_AUDIO_SWDISABLE,
529 AVP_DATAPATH_PACKET_AUDIO_SWDISABLE, GLOBAL_SWDISABLE);
530 }
531
dw_hdmi_i2s_audio_enable(struct dw_hdmi_qp * hdmi)532 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi_qp *hdmi)
533 {
534 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
535 hdmi_enable_audio_clk(hdmi, true);
536 }
537
dw_hdmi_i2s_audio_disable(struct dw_hdmi_qp * hdmi)538 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi_qp *hdmi)
539 {
540 hdmi_enable_audio_clk(hdmi, false);
541 }
542
dw_hdmi_qp_audio_enable(struct dw_hdmi_qp * hdmi)543 void dw_hdmi_qp_audio_enable(struct dw_hdmi_qp *hdmi)
544 {
545 unsigned long flags;
546
547 spin_lock_irqsave(&hdmi->audio_lock, flags);
548 hdmi->audio_enable = true;
549 if (hdmi->enable_audio)
550 hdmi->enable_audio(hdmi);
551 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
552 }
553 EXPORT_SYMBOL_GPL(dw_hdmi_qp_audio_enable);
554
dw_hdmi_qp_audio_disable(struct dw_hdmi_qp * hdmi)555 void dw_hdmi_qp_audio_disable(struct dw_hdmi_qp *hdmi)
556 {
557 unsigned long flags;
558
559 spin_lock_irqsave(&hdmi->audio_lock, flags);
560 hdmi->audio_enable = false;
561 if (hdmi->disable_audio)
562 hdmi->disable_audio(hdmi);
563 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
564 }
565 EXPORT_SYMBOL_GPL(dw_hdmi_qp_audio_disable);
566
hdmi_bus_fmt_is_rgb(unsigned int bus_format)567 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
568 {
569 switch (bus_format) {
570 case MEDIA_BUS_FMT_RGB888_1X24:
571 case MEDIA_BUS_FMT_RGB101010_1X30:
572 case MEDIA_BUS_FMT_RGB121212_1X36:
573 case MEDIA_BUS_FMT_RGB161616_1X48:
574 return true;
575
576 default:
577 return false;
578 }
579 }
580
hdmi_bus_fmt_is_yuv444(unsigned int bus_format)581 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
582 {
583 switch (bus_format) {
584 case MEDIA_BUS_FMT_YUV8_1X24:
585 case MEDIA_BUS_FMT_YUV10_1X30:
586 case MEDIA_BUS_FMT_YUV12_1X36:
587 case MEDIA_BUS_FMT_YUV16_1X48:
588 return true;
589
590 default:
591 return false;
592 }
593 }
594
hdmi_bus_fmt_is_yuv422(unsigned int bus_format)595 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
596 {
597 switch (bus_format) {
598 case MEDIA_BUS_FMT_UYVY8_1X16:
599 case MEDIA_BUS_FMT_UYVY10_1X20:
600 case MEDIA_BUS_FMT_UYVY12_1X24:
601 return true;
602
603 default:
604 return false;
605 }
606 }
607
hdmi_bus_fmt_is_yuv420(unsigned int bus_format)608 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format)
609 {
610 switch (bus_format) {
611 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
612 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
613 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
614 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
615 return true;
616
617 default:
618 return false;
619 }
620 }
621
hdmi_bus_fmt_color_depth(unsigned int bus_format)622 static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
623 {
624 switch (bus_format) {
625 case MEDIA_BUS_FMT_RGB888_1X24:
626 case MEDIA_BUS_FMT_YUV8_1X24:
627 case MEDIA_BUS_FMT_UYVY8_1X16:
628 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
629 return 8;
630
631 case MEDIA_BUS_FMT_RGB101010_1X30:
632 case MEDIA_BUS_FMT_YUV10_1X30:
633 case MEDIA_BUS_FMT_UYVY10_1X20:
634 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
635 return 10;
636
637 case MEDIA_BUS_FMT_RGB121212_1X36:
638 case MEDIA_BUS_FMT_YUV12_1X36:
639 case MEDIA_BUS_FMT_UYVY12_1X24:
640 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
641 return 12;
642
643 case MEDIA_BUS_FMT_RGB161616_1X48:
644 case MEDIA_BUS_FMT_YUV16_1X48:
645 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
646 return 16;
647
648 default:
649 return 0;
650 }
651 }
652
dw_hdmi_i2c_init(struct dw_hdmi_qp * hdmi)653 static void dw_hdmi_i2c_init(struct dw_hdmi_qp *hdmi)
654 {
655 /* Software reset */
656 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0);
657 hdmi_writel(hdmi, 0x00, I2CM_CONTROL0);
658
659 hdmi_writel(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0);
660
661 hdmi_modb(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0);
662
663 /* Clear DONE and ERROR interrupts */
664 hdmi_writel(hdmi, I2CM_OP_DONE_CLEAR | I2CM_NACK_RCVD_CLEAR,
665 MAINUNIT_1_INT_CLEAR);
666 }
667
dw_hdmi_i2c_read(struct dw_hdmi_qp * hdmi,unsigned char * buf,unsigned int length)668 static int dw_hdmi_i2c_read(struct dw_hdmi_qp *hdmi,
669 unsigned char *buf, unsigned int length)
670 {
671 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
672 int stat;
673
674 if (!i2c->is_regaddr) {
675 dev_dbg(hdmi->dev, "set read register address to 0\n");
676 i2c->slave_reg = 0x00;
677 i2c->is_regaddr = true;
678 }
679
680 while (length--) {
681 reinit_completion(&i2c->cmp);
682
683 hdmi_modb(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR,
684 I2CM_INTERFACE_CONTROL0);
685
686 hdmi_modb(hdmi, I2CM_FM_READ, I2CM_WR_MASK,
687 I2CM_INTERFACE_CONTROL0);
688
689 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
690 if (!stat) {
691 dev_err(hdmi->dev, "i2c read time out!\n");
692 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0);
693 return -EAGAIN;
694 }
695
696 /* Check for error condition on the bus */
697 if (i2c->stat & I2CM_NACK_RCVD_IRQ) {
698 dev_err(hdmi->dev, "i2c read err!\n");
699 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0);
700 return -EIO;
701 }
702
703 *buf++ = hdmi_readl(hdmi, I2CM_INTERFACE_RDDATA_0_3) & 0xff;
704 dev_dbg(hdmi->dev, "i2c read done! i2c->stat:%02x 0x%02x\n",
705 i2c->stat, hdmi_readl(hdmi, I2CM_INTERFACE_RDDATA_0_3));
706 hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0);
707 }
708 i2c->is_segment = false;
709
710 return 0;
711 }
712
dw_hdmi_i2c_write(struct dw_hdmi_qp * hdmi,unsigned char * buf,unsigned int length)713 static int dw_hdmi_i2c_write(struct dw_hdmi_qp *hdmi,
714 unsigned char *buf, unsigned int length)
715 {
716 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
717 int stat;
718
719 if (!i2c->is_regaddr) {
720 /* Use the first write byte as register address */
721 i2c->slave_reg = buf[0];
722 length--;
723 buf++;
724 i2c->is_regaddr = true;
725 }
726
727 while (length--) {
728 reinit_completion(&i2c->cmp);
729
730 hdmi_writel(hdmi, *buf++, I2CM_INTERFACE_WRDATA_0_3);
731 hdmi_modb(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR,
732 I2CM_INTERFACE_CONTROL0);
733 hdmi_modb(hdmi, I2CM_FM_WRITE, I2CM_WR_MASK,
734 I2CM_INTERFACE_CONTROL0);
735
736 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
737 if (!stat) {
738 dev_err(hdmi->dev, "i2c write time out!\n");
739 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0);
740 return -EAGAIN;
741 }
742
743 /* Check for error condition on the bus */
744 if (i2c->stat & I2CM_NACK_RCVD_IRQ) {
745 dev_err(hdmi->dev, "i2c write nack!\n");
746 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0);
747 return -EIO;
748 }
749 hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0);
750 }
751 dev_dbg(hdmi->dev, "i2c write done!\n");
752 return 0;
753 }
754
dw_hdmi_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)755 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
756 struct i2c_msg *msgs, int num)
757 {
758 struct dw_hdmi_qp *hdmi = i2c_get_adapdata(adap);
759 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
760 u8 addr = msgs[0].addr;
761 int i, ret = 0;
762
763 if (addr == DDC_CI_ADDR)
764 /*
765 * The internal I2C controller does not support the multi-byte
766 * read and write operations needed for DDC/CI.
767 * TOFIX: Blacklist the DDC/CI address until we filter out
768 * unsupported I2C operations.
769 */
770 return -EOPNOTSUPP;
771
772 dev_dbg(hdmi->dev, "i2c xfer: num: %d, addr: %#x\n", num, addr);
773
774 for (i = 0; i < num; i++) {
775 if (msgs[i].len == 0) {
776 dev_err(hdmi->dev,
777 "unsupported transfer %d/%d, no data\n",
778 i + 1, num);
779 return -EOPNOTSUPP;
780 }
781 }
782
783 mutex_lock(&i2c->lock);
784
785 /* Unmute DONE and ERROR interrupts */
786 hdmi_modb(hdmi, I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N,
787 I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N,
788 MAINUNIT_1_INT_MASK_N);
789
790 /* Set slave device address taken from the first I2C message */
791 if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1)
792 addr = DDC_ADDR;
793
794 hdmi_modb(hdmi, addr << 5, I2CM_SLVADDR, I2CM_INTERFACE_CONTROL0);
795
796 /* Set slave device register address on transfer */
797 i2c->is_regaddr = false;
798
799 /* Set segment pointer for I2C extended read mode operation */
800 i2c->is_segment = false;
801
802 for (i = 0; i < num; i++) {
803 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
804 i + 1, num, msgs[i].len, msgs[i].flags);
805
806 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
807 i2c->is_segment = true;
808 hdmi_modb(hdmi, DDC_SEGMENT_ADDR, I2CM_SEG_ADDR,
809 I2CM_INTERFACE_CONTROL1);
810 hdmi_modb(hdmi, *msgs[i].buf, I2CM_SEG_PTR,
811 I2CM_INTERFACE_CONTROL1);
812 } else {
813 if (msgs[i].flags & I2C_M_RD)
814 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
815 msgs[i].len);
816 else
817 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
818 msgs[i].len);
819 }
820 if (ret < 0)
821 break;
822 }
823
824 if (!ret)
825 ret = num;
826
827 /* Mute DONE and ERROR interrupts */
828 hdmi_modb(hdmi, 0, I2CM_OP_DONE_MASK_N | I2CM_NACK_RCVD_MASK_N,
829 MAINUNIT_1_INT_MASK_N);
830
831 mutex_unlock(&i2c->lock);
832
833 return ret;
834 }
835
dw_hdmi_i2c_func(struct i2c_adapter * adapter)836 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
837 {
838 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
839 }
840
841 static const struct i2c_algorithm dw_hdmi_algorithm = {
842 .master_xfer = dw_hdmi_i2c_xfer,
843 .functionality = dw_hdmi_i2c_func,
844 };
845
dw_hdmi_i2c_adapter(struct dw_hdmi_qp * hdmi)846 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi_qp *hdmi)
847 {
848 struct i2c_adapter *adap;
849 struct dw_hdmi_qp_i2c *i2c;
850 int ret;
851
852 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
853 if (!i2c)
854 return ERR_PTR(-ENOMEM);
855
856 mutex_init(&i2c->lock);
857 init_completion(&i2c->cmp);
858
859 adap = &i2c->adap;
860 adap->class = I2C_CLASS_DDC;
861 adap->owner = THIS_MODULE;
862 adap->dev.parent = hdmi->dev;
863 adap->algo = &dw_hdmi_algorithm;
864 strscpy(adap->name, "ddc", sizeof(adap->name));
865 i2c_set_adapdata(adap, hdmi);
866
867 ret = i2c_add_adapter(adap);
868 if (ret) {
869 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
870 devm_kfree(hdmi->dev, i2c);
871 return ERR_PTR(ret);
872 }
873
874 hdmi->i2c = i2c;
875
876 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
877
878 return adap;
879 }
880
881 #define HDMI_PHY_EARC_MASK BIT(29)
882
dw_hdmi_qp_set_earc(struct dw_hdmi_qp * hdmi)883 int dw_hdmi_qp_set_earc(struct dw_hdmi_qp *hdmi)
884 {
885 u32 stat, ret;
886
887 /* set hdmi phy earc mode */
888 hdmi->phy.ops->set_mode(hdmi, hdmi->phy.data, HDMI_PHY_EARC_MASK,
889 true);
890
891 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data,
892 &hdmi->previous_mode);
893 if (ret)
894 return ret;
895
896 reinit_completion(&hdmi->earc_cmp);
897
898 hdmi_modb(hdmi, EARCRX_CMDC_DISCOVERY_TIMEOUT_IRQ |
899 EARCRX_CMDC_DISCOVERY_DONE_IRQ,
900 EARCRX_CMDC_DISCOVERY_TIMEOUT_IRQ |
901 EARCRX_CMDC_DISCOVERY_DONE_IRQ, EARCRX_0_INT_MASK_N);
902
903 /* start discovery */
904 hdmi_modb(hdmi, EARCRX_CMDC_DISCOVERY_EN, EARCRX_CMDC_DISCOVERY_EN,
905 EARCRX_CMDC_CONTROL);
906
907 /*
908 * The eARC TX device drives a logic-high-voltage-level
909 * pulse on the physical HPD connector pin, after
910 * at least 100 ms of low voltage level to start the
911 * eARC Discovery process.
912 */
913 hdmi_modb(hdmi, EARCRX_CONNECTOR_HPD, EARCRX_CONNECTOR_HPD,
914 EARCRX_CMDC_CONTROL);
915
916 stat = wait_for_completion_timeout(&hdmi->earc_cmp, HZ / 10);
917 if (!stat)
918 return -EAGAIN;
919
920 if (hdmi->earc_intr & EARCRX_CMDC_DISCOVERY_TIMEOUT_IRQ) {
921 dev_err(hdmi->dev, "discovery timeout\n");
922 return -ETIMEDOUT;
923 } else if (hdmi->earc_intr & EARCRX_CMDC_DISCOVERY_DONE_IRQ) {
924 dev_info(hdmi->dev, "discovery done\n");
925 } else {
926 dev_err(hdmi->dev, "discovery failed\n");
927 return -EINVAL;
928 }
929
930 hdmi_writel(hdmi, 1, EARCRX_DMAC_PHY_CONTROL);
931 hdmi_modb(hdmi, EARCRX_CMDC_SWINIT_P, EARCRX_CMDC_SWINIT_P,
932 EARCRX_CMDC_CONFIG0);
933
934 hdmi_writel(hdmi, 0xf3, EARCRX_DMAC_CONFIG);
935 hdmi_writel(hdmi, 0x63, EARCRX_DMAC_CONTROL0);
936 hdmi_writel(hdmi, 0xff, EARCRX_DMAC_CONTROL1);
937
938 hdmi_modb(hdmi, EARCRX_XACTREAD_STOP_CFG | EARCRX_XACTREAD_RETRY_CFG |
939 EARCRX_CMDC_DSCVR_EARCVALID0_TO_DISC1 | EARCRX_CMDC_XACT_RESTART_EN,
940 EARCRX_XACTREAD_STOP_CFG | EARCRX_XACTREAD_RETRY_CFG |
941 EARCRX_CMDC_DSCVR_EARCVALID0_TO_DISC1 | EARCRX_CMDC_XACT_RESTART_EN,
942 EARCRX_CMDC_CONFIG0);
943
944 hdmi_writel(hdmi, 0, EARCRX_DMAC_CHSTATUS_STREAMER0);
945 hdmi_writel(hdmi, 0x1b0e, EARCRX_DMAC_CHSTATUS_STREAMER1);
946 hdmi_writel(hdmi, 0, EARCRX_DMAC_CHSTATUS_STREAMER2);
947 hdmi_writel(hdmi, 0, EARCRX_DMAC_CHSTATUS_STREAMER3);
948 hdmi_writel(hdmi, 0xf2000000, EARCRX_DMAC_CHSTATUS_STREAMER4);
949 hdmi_writel(hdmi, 0, EARCRX_DMAC_CHSTATUS_STREAMER5);
950 hdmi_writel(hdmi, 0, EARCRX_DMAC_CHSTATUS_STREAMER6);
951 hdmi_writel(hdmi, 0, EARCRX_DMAC_CHSTATUS_STREAMER7);
952 hdmi_writel(hdmi, 0, EARCRX_DMAC_CHSTATUS_STREAMER8);
953
954 return 0;
955 }
956 EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_earc);
957
958 /* -----------------------------------------------------------------------------
959 * HDMI TX Setup
960 */
961
hdmi_config_AVI(struct dw_hdmi_qp * hdmi,const struct drm_connector * connector,const struct drm_display_mode * mode)962 static void hdmi_config_AVI(struct dw_hdmi_qp *hdmi,
963 const struct drm_connector *connector,
964 const struct drm_display_mode *mode)
965 {
966 struct hdmi_avi_infoframe frame;
967 u32 val, i, j;
968 u8 buff[17];
969 enum hdmi_quantization_range rgb_quant_range =
970 hdmi->hdmi_data.quant_range;
971
972 /* Initialise info frame from DRM mode */
973 drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
974
975 /*
976 * Ignore monitor selectable quantization, use quantization set
977 * by the user
978 */
979 drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode, rgb_quant_range);
980 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
981 frame.colorspace = HDMI_COLORSPACE_YUV444;
982 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
983 frame.colorspace = HDMI_COLORSPACE_YUV422;
984 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
985 frame.colorspace = HDMI_COLORSPACE_YUV420;
986 else
987 frame.colorspace = HDMI_COLORSPACE_RGB;
988
989 /* Set up colorimetry */
990 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
991 switch (hdmi->hdmi_data.enc_out_encoding) {
992 case V4L2_YCBCR_ENC_601:
993 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
994 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
995 else
996 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
997 frame.extended_colorimetry =
998 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
999 break;
1000 case V4L2_YCBCR_ENC_709:
1001 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1002 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1003 else
1004 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1005 frame.extended_colorimetry =
1006 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1007 break;
1008 case V4L2_YCBCR_ENC_BT2020:
1009 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_BT2020)
1010 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1011 else
1012 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1013 frame.extended_colorimetry =
1014 HDMI_EXTENDED_COLORIMETRY_BT2020;
1015 break;
1016 default: /* Carries no data */
1017 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1018 frame.extended_colorimetry =
1019 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1020 break;
1021 }
1022 } else {
1023 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1024 frame.extended_colorimetry =
1025 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1026 }
1027
1028 frame.scan_mode = HDMI_SCAN_MODE_NONE;
1029
1030 hdmi_avi_infoframe_pack_only(&frame, buff, 17);
1031
1032 /*
1033 * The Designware IP uses a different byte format from standard
1034 * AVI info frames, though generally the bits are in the correct
1035 * bytes.
1036 */
1037
1038 val = (frame.version << 8) | (frame.length << 16);
1039 hdmi_writel(hdmi, val, PKT_AVI_CONTENTS0);
1040
1041 for (i = 0; i < 4; i++) {
1042 for (j = 0; j < 4; j++) {
1043 if (i * 4 + j >= 14)
1044 break;
1045 if (!j)
1046 val = buff[i * 4 + j + 3];
1047 val |= buff[i * 4 + j + 3] << (8 * j);
1048 }
1049
1050 hdmi_writel(hdmi, val, PKT_AVI_CONTENTS1 + i * 4);
1051 }
1052
1053 hdmi_modb(hdmi, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN,
1054 PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN,
1055 PKTSCHED_PKT_EN);
1056 }
1057
hdmi_config_CVTEM(struct dw_hdmi_qp * hdmi)1058 static void hdmi_config_CVTEM(struct dw_hdmi_qp *hdmi)
1059 {
1060 u8 ds_type = 0;
1061 u8 sync = 1;
1062 u8 vfr = 1;
1063 u8 afr = 0;
1064 u8 new = 1;
1065 u8 end = 0;
1066 u8 data_set_length = 136;
1067 u8 hb1[6] = { 0x80, 0, 0, 0, 0, 0x40 };
1068 u8 *pps_body;
1069 u32 val, i, reg;
1070 struct drm_display_mode *mode = &hdmi->previous_mode;
1071 int hsync, hfront, hback;
1072 struct dw_hdmi_link_config *link_cfg;
1073 void *data = hdmi->plat_data->phy_data;
1074
1075 hdmi_modb(hdmi, 0, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_PKT_EN);
1076
1077 if (hdmi->plat_data->get_link_cfg) {
1078 link_cfg = hdmi->plat_data->get_link_cfg(data);
1079 } else {
1080 dev_err(hdmi->dev, "can't get frl link cfg\n");
1081 return;
1082 }
1083
1084 if (!link_cfg->dsc_mode) {
1085 dev_info(hdmi->dev, "don't use dsc mode\n");
1086 return;
1087 }
1088
1089 pps_body = link_cfg->pps_payload;
1090
1091 hsync = mode->hsync_end - mode->hsync_start;
1092 hback = mode->htotal - mode->hsync_end;
1093 hfront = mode->hsync_start - mode->hdisplay;
1094
1095 for (i = 0; i < 6; i++) {
1096 val = i << 16 | hb1[i] << 8;
1097 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS0 + i * 0x20);
1098 }
1099
1100 val = new << 7 | end << 6 | ds_type << 4 | afr << 3 |
1101 vfr << 2 | sync << 1;
1102 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS1);
1103
1104 val = data_set_length << 16 | pps_body[0] << 24;
1105 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS2);
1106
1107 reg = PKT0_EMP_CVTEM_CONTENTS3;
1108 for (i = 1; i < 125; i++) {
1109 if (reg == PKT1_EMP_CVTEM_CONTENTS0 ||
1110 reg == PKT2_EMP_CVTEM_CONTENTS0 ||
1111 reg == PKT3_EMP_CVTEM_CONTENTS0 ||
1112 reg == PKT4_EMP_CVTEM_CONTENTS0 ||
1113 reg == PKT5_EMP_CVTEM_CONTENTS0) {
1114 reg += 4;
1115 i--;
1116 continue;
1117 }
1118 if (i % 4 == 1)
1119 val = pps_body[i];
1120 if (i % 4 == 2)
1121 val |= pps_body[i] << 8;
1122 if (i % 4 == 3)
1123 val |= pps_body[i] << 16;
1124 if (!(i % 4)) {
1125 val |= pps_body[i] << 24;
1126 hdmi_writel(hdmi, val, reg);
1127 reg += 4;
1128 }
1129 }
1130
1131 val = (hfront & 0xff) << 24 | pps_body[127] << 16 |
1132 pps_body[126] << 8 | pps_body[125];
1133 hdmi_writel(hdmi, val, PKT4_EMP_CVTEM_CONTENTS6);
1134
1135 val = (hback & 0xff) << 24 | ((hsync >> 8) & 0xff) << 16 |
1136 (hsync & 0xff) << 8 | ((hfront >> 8) & 0xff);
1137 hdmi_writel(hdmi, val, PKT4_EMP_CVTEM_CONTENTS7);
1138
1139 val = link_cfg->hcactive << 8 | ((hback >> 8) & 0xff);
1140 hdmi_writel(hdmi, val, PKT5_EMP_CVTEM_CONTENTS1);
1141
1142 for (i = PKT5_EMP_CVTEM_CONTENTS2; i <= PKT5_EMP_CVTEM_CONTENTS7; i += 4)
1143 hdmi_writel(hdmi, 0, i);
1144
1145 hdmi_modb(hdmi, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_EMP_CVTEM_TX_EN,
1146 PKTSCHED_PKT_EN);
1147 }
1148
hdmi_config_drm_infoframe(struct dw_hdmi_qp * hdmi,const struct drm_connector * connector)1149 static void hdmi_config_drm_infoframe(struct dw_hdmi_qp *hdmi,
1150 const struct drm_connector *connector)
1151 {
1152 const struct drm_connector_state *conn_state = connector->state;
1153 struct hdr_output_metadata *hdr_metadata;
1154 struct hdmi_drm_infoframe frame;
1155 u8 buffer[30];
1156 ssize_t err;
1157 int i;
1158 u32 val;
1159
1160 if (!hdmi->plat_data->use_drm_infoframe)
1161 return;
1162
1163 hdmi_modb(hdmi, 0, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN);
1164
1165 if (!hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf) {
1166 DRM_DEBUG("No need to set HDR metadata in infoframe\n");
1167 return;
1168 }
1169
1170 if (!conn_state->hdr_output_metadata) {
1171 DRM_DEBUG("source metadata not set yet\n");
1172 return;
1173 }
1174
1175 hdr_metadata = (struct hdr_output_metadata *)
1176 conn_state->hdr_output_metadata->data;
1177
1178 if (!(hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf &
1179 BIT(hdr_metadata->hdmi_metadata_type1.eotf))) {
1180 DRM_ERROR("Not support EOTF %d\n",
1181 hdr_metadata->hdmi_metadata_type1.eotf);
1182 return;
1183 }
1184
1185 err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state);
1186 if (err < 0)
1187 return;
1188
1189 err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer));
1190 if (err < 0) {
1191 dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err);
1192 return;
1193 }
1194
1195 val = (frame.version << 8) | (frame.length << 16);
1196 hdmi_writel(hdmi, val, PKT_DRMI_CONTENTS0);
1197
1198 for (i = 0; i <= frame.length; i++) {
1199 if (i % 4 == 0)
1200 val = buffer[3 + i];
1201 val |= buffer[3 + i] << ((i % 4) * 8);
1202
1203 if (i % 4 == 3 || (i == (frame.length)))
1204 hdmi_writel(hdmi, val, PKT_DRMI_CONTENTS1 + ((i / 4) * 4));
1205 }
1206
1207 hdmi_modb(hdmi, PKTSCHED_DRMI_TX_EN, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN);
1208
1209 DRM_DEBUG("%s eotf %d end\n", __func__,
1210 hdr_metadata->hdmi_metadata_type1.eotf);
1211 }
1212
1213 /* Filter out invalid setups to avoid configuring SCDC and scrambling */
dw_hdmi_support_scdc(struct dw_hdmi_qp * hdmi,const struct drm_display_info * display)1214 static bool dw_hdmi_support_scdc(struct dw_hdmi_qp *hdmi,
1215 const struct drm_display_info *display)
1216 {
1217 /* Disable if no DDC bus */
1218 if (!hdmi->ddc)
1219 return false;
1220
1221 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
1222 if (!display->hdmi.scdc.supported ||
1223 !display->hdmi.scdc.scrambling.supported)
1224 return false;
1225
1226 /*
1227 * Disable if display only support low TMDS rates and scrambling
1228 * for low rates is not supported either
1229 */
1230 if (!display->hdmi.scdc.scrambling.low_rates &&
1231 display->max_tmds_clock <= 340000)
1232 return false;
1233
1234 return true;
1235 }
1236
hdmi_set_frl_mask(int frl_rate)1237 static int hdmi_set_frl_mask(int frl_rate)
1238 {
1239 switch (frl_rate) {
1240 case 48:
1241 return FRL_12GBPS_4LANE;
1242 case 40:
1243 return FRL_10GBPS_4LANE;
1244 case 32:
1245 return FRL_8GBPS_4LANE;
1246 case 24:
1247 return FRL_6GBPS_4LANE;
1248 case 18:
1249 return FRL_6GBPS_3LANE;
1250 case 9:
1251 return FRL_3GBPS_3LANE;
1252 }
1253
1254 return 0;
1255 }
1256
hdmi_start_flt(struct dw_hdmi_qp * hdmi,u8 rate)1257 static int hdmi_start_flt(struct dw_hdmi_qp *hdmi, u8 rate)
1258 {
1259 u8 val;
1260 u8 ffe_lv = 0;
1261 int i = 0, stat;
1262
1263 /* FLT_READY & FFE_LEVELS read */
1264 for (i = 0; i < 20; i++) {
1265 drm_scdc_readb(hdmi->ddc, SCDC_STATUS_FLAGS_0, &val);
1266 if (val & BIT(6))
1267 break;
1268 msleep(20);
1269 }
1270
1271 if (i == 20) {
1272 dev_err(hdmi->dev, "sink flt isn't ready\n");
1273 return -EINVAL;
1274 }
1275
1276 hdmi_modb(hdmi, SCDC_UPD_FLAGS_RD_IRQ, SCDC_UPD_FLAGS_RD_IRQ,
1277 MAINUNIT_1_INT_MASK_N);
1278 hdmi_modb(hdmi, SCDC_UPD_FLAGS_POLL_EN | SCDC_UPD_FLAGS_AUTO_CLR,
1279 SCDC_UPD_FLAGS_POLL_EN | SCDC_UPD_FLAGS_AUTO_CLR,
1280 SCDC_CONFIG0);
1281
1282 /* max ffe level 3 */
1283 val = 3 << 4 | hdmi_set_frl_mask(rate);
1284 drm_scdc_writeb(hdmi->ddc, 0x31, val);
1285
1286 /* select FRL_RATE & FFE_LEVELS */
1287 hdmi_writel(hdmi, ffe_lv, FLT_CONFIG0);
1288
1289 /* Start LTS_3 state in source DUT */
1290 reinit_completion(&hdmi->flt_cmp);
1291 hdmi_modb(hdmi, FLT_EXIT_TO_LTSP_IRQ, FLT_EXIT_TO_LTSP_IRQ,
1292 MAINUNIT_1_INT_MASK_N);
1293 hdmi_writel(hdmi, 1, FLT_CONTROL0);
1294
1295 /* wait for completed link training at source side */
1296 stat = wait_for_completion_timeout(&hdmi->flt_cmp, HZ * 2);
1297 if (!stat) {
1298 dev_err(hdmi->dev, "wait lts3 finish time out\n");
1299 hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_POLL_EN |
1300 SCDC_UPD_FLAGS_AUTO_CLR, SCDC_CONFIG0);
1301 hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_RD_IRQ,
1302 MAINUNIT_1_INT_MASK_N);
1303 return -EAGAIN;
1304 }
1305
1306 if (!(hdmi->flt_intr & FLT_EXIT_TO_LTSP_IRQ)) {
1307 dev_err(hdmi->dev, "not to ltsp\n");
1308 hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_POLL_EN |
1309 SCDC_UPD_FLAGS_AUTO_CLR, SCDC_CONFIG0);
1310 hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_RD_IRQ,
1311 MAINUNIT_1_INT_MASK_N);
1312 return -EINVAL;
1313 }
1314
1315 return 0;
1316 }
1317
1318 #define HDMI_MODE_FRL_MASK BIT(30)
1319
hdmi_set_op_mode(struct dw_hdmi_qp * hdmi,struct dw_hdmi_link_config * link_cfg,const struct drm_connector * connector)1320 static void hdmi_set_op_mode(struct dw_hdmi_qp *hdmi,
1321 struct dw_hdmi_link_config *link_cfg,
1322 const struct drm_connector *connector)
1323 {
1324 int frl_rate;
1325
1326 /* set sink frl mode disable and wait sink ready */
1327 hdmi_writel(hdmi, 0, FLT_CONFIG0);
1328 if (dw_hdmi_support_scdc(hdmi, &connector->display_info))
1329 drm_scdc_writeb(hdmi->ddc, 0x31, 0);
1330 /*
1331 * some TVs must wait a while before switching frl mode resolution,
1332 * or the signal may not be recognized.
1333 */
1334 msleep(200);
1335 if (!link_cfg->frl_mode) {
1336 dev_info(hdmi->dev, "dw hdmi qp use tmds mode\n");
1337 hdmi_modb(hdmi, 0, OPMODE_FRL, LINK_CONFIG0);
1338 hdmi_modb(hdmi, 0, OPMODE_FRL_4LANES, LINK_CONFIG0);
1339 return;
1340 }
1341
1342 if (link_cfg->frl_lanes == 4)
1343 hdmi_modb(hdmi, OPMODE_FRL_4LANES, OPMODE_FRL_4LANES,
1344 LINK_CONFIG0);
1345 else
1346 hdmi_modb(hdmi, 0, OPMODE_FRL_4LANES, LINK_CONFIG0);
1347
1348 hdmi_modb(hdmi, 1, OPMODE_FRL, LINK_CONFIG0);
1349
1350 frl_rate = link_cfg->frl_lanes * link_cfg->rate_per_lane;
1351 hdmi_start_flt(hdmi, frl_rate);
1352 }
1353
1354 static unsigned long
hdmi_get_tmdsclock(struct dw_hdmi_qp * hdmi,unsigned long mpixelclock)1355 hdmi_get_tmdsclock(struct dw_hdmi_qp *hdmi, unsigned long mpixelclock)
1356 {
1357 unsigned long tmdsclock = mpixelclock;
1358 unsigned int depth =
1359 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format);
1360
1361 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1362 switch (depth) {
1363 case 16:
1364 tmdsclock = mpixelclock * 2;
1365 break;
1366 case 12:
1367 tmdsclock = mpixelclock * 3 / 2;
1368 break;
1369 case 10:
1370 tmdsclock = mpixelclock * 5 / 4;
1371 break;
1372 default:
1373 break;
1374 }
1375 }
1376
1377 return tmdsclock;
1378 }
1379
dw_hdmi_qp_setup(struct dw_hdmi_qp * hdmi,const struct drm_connector * connector,const struct drm_display_mode * mode)1380 static int dw_hdmi_qp_setup(struct dw_hdmi_qp *hdmi,
1381 const struct drm_connector *connector,
1382 const struct drm_display_mode *mode)
1383 {
1384 int ret;
1385 void *data = hdmi->plat_data->phy_data;
1386 struct hdmi_vmode_qp *vmode = &hdmi->hdmi_data.video_mode;
1387 struct dw_hdmi_link_config *link_cfg;
1388 u8 bytes = 0;
1389
1390 hdmi->vic = drm_match_cea_mode(mode);
1391 if (!hdmi->vic)
1392 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1393 else
1394 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1395
1396 if (hdmi->plat_data->get_enc_out_encoding)
1397 hdmi->hdmi_data.enc_out_encoding =
1398 hdmi->plat_data->get_enc_out_encoding(data);
1399 else if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1400 (hdmi->vic == 21) || (hdmi->vic == 22) ||
1401 (hdmi->vic == 2) || (hdmi->vic == 3) ||
1402 (hdmi->vic == 17) || (hdmi->vic == 18))
1403 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
1404 else
1405 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
1406
1407 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1408 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1409 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1;
1410 } else {
1411 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1412 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1413 }
1414 /* Get input format from plat data or fallback to RGB888 */
1415 if (hdmi->plat_data->get_input_bus_format)
1416 hdmi->hdmi_data.enc_in_bus_format =
1417 hdmi->plat_data->get_input_bus_format(data);
1418 else if (hdmi->plat_data->input_bus_format)
1419 hdmi->hdmi_data.enc_in_bus_format =
1420 hdmi->plat_data->input_bus_format;
1421 else
1422 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1423
1424 /* Default to RGB888 output format */
1425 if (hdmi->plat_data->get_output_bus_format)
1426 hdmi->hdmi_data.enc_out_bus_format =
1427 hdmi->plat_data->get_output_bus_format(data);
1428 else
1429 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1430
1431 /* Get input encoding from plat data or fallback to none */
1432 if (hdmi->plat_data->get_enc_in_encoding)
1433 hdmi->hdmi_data.enc_in_encoding =
1434 hdmi->plat_data->get_enc_in_encoding(data);
1435 else if (hdmi->plat_data->input_bus_encoding)
1436 hdmi->hdmi_data.enc_in_encoding =
1437 hdmi->plat_data->input_bus_encoding;
1438 else
1439 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
1440
1441 if (hdmi->plat_data->get_quant_range)
1442 hdmi->hdmi_data.quant_range =
1443 hdmi->plat_data->get_quant_range(data);
1444 else
1445 hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
1446
1447 if (hdmi->plat_data->get_link_cfg)
1448 link_cfg = hdmi->plat_data->get_link_cfg(data);
1449 else
1450 return -EINVAL;
1451
1452 hdmi->phy.ops->set_mode(hdmi, hdmi->phy.data, HDMI_MODE_FRL_MASK,
1453 link_cfg->frl_mode);
1454
1455 /*
1456 * According to the dw-hdmi specification 6.4.2
1457 * vp_pr_cd[3:0]:
1458 * 0000b: No pixel repetition (pixel sent only once)
1459 * 0001b: Pixel sent two times (pixel repeated once)
1460 */
1461 hdmi->hdmi_data.pix_repet_factor =
1462 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0;
1463 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1464
1465 vmode->previous_pixelclock = vmode->mpixelclock;
1466 vmode->mpixelclock = mode->crtc_clock * 1000;
1467 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1468 vmode->mpixelclock *= 2;
1469 dev_dbg(hdmi->dev, "final pixclk = %ld\n", vmode->mpixelclock);
1470 vmode->previous_tmdsclock = vmode->mtmdsclock;
1471 vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock);
1472 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1473 vmode->mtmdsclock /= 2;
1474 dev_info(hdmi->dev, "final tmdsclk = %d\n", vmode->mtmdsclock);
1475
1476 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode);
1477 if (ret)
1478 return ret;
1479
1480 if (hdmi->plat_data->set_grf_cfg)
1481 hdmi->plat_data->set_grf_cfg(data);
1482
1483 if (hdmi->sink_has_audio) {
1484 dev_dbg(hdmi->dev, "sink has audio support\n");
1485
1486 /* HDMI Initialization Step E - Configure audio */
1487 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1488 hdmi_enable_audio_clk(hdmi, hdmi->audio_enable);
1489 }
1490
1491 /* not for DVI mode */
1492 if (hdmi->sink_is_hdmi) {
1493 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1494 hdmi_modb(hdmi, 0, OPMODE_DVI, LINK_CONFIG0);
1495 hdmi_modb(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0);
1496 if (!link_cfg->frl_mode) {
1497 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK) {
1498 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION, &bytes);
1499 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION,
1500 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION));
1501 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1);
1502 drm_scdc_set_scrambling(hdmi->ddc, 1);
1503 hdmi_writel(hdmi, 1, SCRAMB_CONFIG0);
1504 } else {
1505 if (dw_hdmi_support_scdc(hdmi, &connector->display_info)) {
1506 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0);
1507 drm_scdc_set_scrambling(hdmi->ddc, 0);
1508 }
1509 hdmi_writel(hdmi, 0, SCRAMB_CONFIG0);
1510 }
1511 }
1512 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1513 hdmi_config_AVI(hdmi, connector, mode);
1514 hdmi_config_CVTEM(hdmi);
1515 hdmi_config_drm_infoframe(hdmi, connector);
1516 hdmi_set_op_mode(hdmi, link_cfg, connector);
1517 } else {
1518 hdmi_modb(hdmi, OPMODE_DVI, OPMODE_DVI, LINK_CONFIG0);
1519 dev_info(hdmi->dev, "%s DVI mode\n", __func__);
1520 }
1521
1522 return 0;
1523 }
1524
1525 static enum drm_connector_status
dw_hdmi_connector_detect(struct drm_connector * connector,bool force)1526 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1527 {
1528 struct dw_hdmi_qp *hdmi =
1529 container_of(connector, struct dw_hdmi_qp, connector);
1530
1531 mutex_lock(&hdmi->mutex);
1532 hdmi->force = DRM_FORCE_UNSPECIFIED;
1533 mutex_unlock(&hdmi->mutex);
1534
1535 return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
1536 }
1537
1538 static int
dw_hdmi_update_hdr_property(struct drm_connector * connector)1539 dw_hdmi_update_hdr_property(struct drm_connector *connector)
1540 {
1541 struct drm_device *dev = connector->dev;
1542 struct dw_hdmi_qp *hdmi = container_of(connector, struct dw_hdmi_qp,
1543 connector);
1544 void *data = hdmi->plat_data->phy_data;
1545 const struct hdr_static_metadata *metadata =
1546 &connector->hdr_sink_metadata.hdmi_type1;
1547 size_t size = sizeof(*metadata);
1548 struct drm_property *property;
1549 struct drm_property_blob *blob;
1550 int ret;
1551
1552 if (hdmi->plat_data->get_hdr_property)
1553 property = hdmi->plat_data->get_hdr_property(data);
1554 else
1555 return -EINVAL;
1556
1557 if (hdmi->plat_data->get_hdr_blob)
1558 blob = hdmi->plat_data->get_hdr_blob(data);
1559 else
1560 return -EINVAL;
1561
1562 ret = drm_property_replace_global_blob(dev, &blob, size, metadata,
1563 &connector->base, property);
1564 return ret;
1565 }
1566
dw_hdmi_connector_get_modes(struct drm_connector * connector)1567 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1568 {
1569 struct dw_hdmi_qp *hdmi =
1570 container_of(connector, struct dw_hdmi_qp, connector);
1571 struct hdr_static_metadata *metedata =
1572 &connector->hdr_sink_metadata.hdmi_type1;
1573 struct edid *edid;
1574 struct drm_display_mode *mode;
1575 struct drm_display_info *info = &connector->display_info;
1576 void *data = hdmi->plat_data->phy_data;
1577 int i, ret = 0;
1578
1579 if (!hdmi->ddc)
1580 return 0;
1581
1582 memset(metedata, 0, sizeof(*metedata));
1583 edid = drm_get_edid(connector, hdmi->ddc);
1584 if (edid) {
1585 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1586 edid->width_cm, edid->height_cm);
1587
1588 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1589 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1590 drm_connector_update_edid_property(connector, edid);
1591 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
1592 if (hdmi->plat_data->get_edid_dsc_info)
1593 hdmi->plat_data->get_edid_dsc_info(data, edid);
1594 ret = drm_add_edid_modes(connector, edid);
1595 dw_hdmi_update_hdr_property(connector);
1596 kfree(edid);
1597 } else {
1598 hdmi->sink_is_hdmi = true;
1599 hdmi->sink_has_audio = true;
1600
1601 for (i = 0; i < ARRAY_SIZE(dw_hdmi_default_modes); i++) {
1602 const struct drm_display_mode *ptr =
1603 &dw_hdmi_default_modes[i];
1604
1605 mode = drm_mode_duplicate(connector->dev, ptr);
1606 if (mode) {
1607 if (!i) {
1608 mode->type = DRM_MODE_TYPE_PREFERRED;
1609 mode->picture_aspect_ratio =
1610 HDMI_PICTURE_ASPECT_NONE;
1611 }
1612 drm_mode_probed_add(connector, mode);
1613 ret++;
1614 }
1615 }
1616 info->edid_hdmi_dc_modes = 0;
1617 info->hdmi.y420_dc_modes = 0;
1618 info->color_formats = 0;
1619
1620 dev_info(hdmi->dev, "failed to get edid\n");
1621 }
1622
1623 return ret;
1624 }
1625
1626 static int
dw_hdmi_atomic_connector_set_property(struct drm_connector * connector,struct drm_connector_state * state,struct drm_property * property,uint64_t val)1627 dw_hdmi_atomic_connector_set_property(struct drm_connector *connector,
1628 struct drm_connector_state *state,
1629 struct drm_property *property,
1630 uint64_t val)
1631 {
1632 struct dw_hdmi_qp *hdmi =
1633 container_of(connector, struct dw_hdmi_qp, connector);
1634 const struct dw_hdmi_property_ops *ops = hdmi->plat_data->property_ops;
1635
1636 if (ops && ops->set_property)
1637 return ops->set_property(connector, state, property,
1638 val, hdmi->plat_data->phy_data);
1639 else
1640 return -EINVAL;
1641 }
1642
1643 static int
dw_hdmi_atomic_connector_get_property(struct drm_connector * connector,const struct drm_connector_state * state,struct drm_property * property,uint64_t * val)1644 dw_hdmi_atomic_connector_get_property(struct drm_connector *connector,
1645 const struct drm_connector_state *state,
1646 struct drm_property *property,
1647 uint64_t *val)
1648 {
1649 struct dw_hdmi_qp *hdmi =
1650 container_of(connector, struct dw_hdmi_qp, connector);
1651 const struct dw_hdmi_property_ops *ops = hdmi->plat_data->property_ops;
1652
1653 if (ops && ops->get_property)
1654 return ops->get_property(connector, state, property,
1655 val, hdmi->plat_data->phy_data);
1656 else
1657 return -EINVAL;
1658 }
1659
1660 static int
dw_hdmi_connector_set_property(struct drm_connector * connector,struct drm_property * property,uint64_t val)1661 dw_hdmi_connector_set_property(struct drm_connector *connector,
1662 struct drm_property *property, uint64_t val)
1663 {
1664 return dw_hdmi_atomic_connector_set_property(connector, NULL,
1665 property, val);
1666 }
1667
dw_hdmi_attach_properties(struct dw_hdmi_qp * hdmi)1668 static void dw_hdmi_attach_properties(struct dw_hdmi_qp *hdmi)
1669 {
1670 unsigned int color = MEDIA_BUS_FMT_RGB888_1X24;
1671 const struct dw_hdmi_property_ops *ops =
1672 hdmi->plat_data->property_ops;
1673
1674 if (ops && ops->attach_properties)
1675 return ops->attach_properties(&hdmi->connector, color, 0,
1676 hdmi->plat_data->phy_data);
1677 }
1678
dw_hdmi_destroy_properties(struct dw_hdmi_qp * hdmi)1679 static void dw_hdmi_destroy_properties(struct dw_hdmi_qp *hdmi)
1680 {
1681 const struct dw_hdmi_property_ops *ops =
1682 hdmi->plat_data->property_ops;
1683
1684 if (ops && ops->destroy_properties)
1685 return ops->destroy_properties(&hdmi->connector,
1686 hdmi->plat_data->phy_data);
1687 }
1688
1689 static struct drm_encoder *
dw_hdmi_connector_best_encoder(struct drm_connector * connector)1690 dw_hdmi_connector_best_encoder(struct drm_connector *connector)
1691 {
1692 struct dw_hdmi_qp *hdmi =
1693 container_of(connector, struct dw_hdmi_qp, connector);
1694
1695 return hdmi->bridge.encoder;
1696 }
1697
dw_hdmi_color_changed(struct drm_connector * connector)1698 static bool dw_hdmi_color_changed(struct drm_connector *connector)
1699 {
1700 struct dw_hdmi_qp *hdmi =
1701 container_of(connector, struct dw_hdmi_qp, connector);
1702 void *data = hdmi->plat_data->phy_data;
1703 bool ret = false;
1704
1705 if (hdmi->plat_data->get_color_changed)
1706 ret = hdmi->plat_data->get_color_changed(data);
1707
1708 return ret;
1709 }
1710
hdr_metadata_equal(const struct drm_connector_state * old_state,const struct drm_connector_state * new_state)1711 static bool hdr_metadata_equal(const struct drm_connector_state *old_state,
1712 const struct drm_connector_state *new_state)
1713 {
1714 struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
1715 struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
1716
1717 if (!old_blob || !new_blob)
1718 return old_blob == new_blob;
1719
1720 if (old_blob->length != new_blob->length)
1721 return false;
1722
1723 return !memcmp(old_blob->data, new_blob->data, old_blob->length);
1724 }
1725
dw_hdmi_connector_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)1726 static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,
1727 struct drm_atomic_state *state)
1728 {
1729 struct drm_connector_state *old_state =
1730 drm_atomic_get_old_connector_state(state, connector);
1731 struct drm_connector_state *new_state =
1732 drm_atomic_get_new_connector_state(state, connector);
1733 struct drm_crtc *crtc = new_state->crtc;
1734 struct drm_crtc_state *crtc_state;
1735 struct dw_hdmi_qp *hdmi =
1736 container_of(connector, struct dw_hdmi_qp, connector);
1737 struct drm_display_mode *mode = NULL;
1738 void *data = hdmi->plat_data->phy_data;
1739 struct hdmi_vmode_qp *vmode = &hdmi->hdmi_data.video_mode;
1740 unsigned int in_bus_format = hdmi->hdmi_data.enc_in_bus_format;
1741 unsigned int out_bus_format = hdmi->hdmi_data.enc_out_bus_format;
1742 bool color_changed = false;
1743
1744 if (!crtc)
1745 return 0;
1746
1747 crtc_state = drm_atomic_get_crtc_state(state, crtc);
1748 if (IS_ERR(crtc_state))
1749 return PTR_ERR(crtc_state);
1750
1751 /*
1752 * If HDMI is enabled in uboot, it's need to record
1753 * drm_display_mode and set phy status to enabled.
1754 */
1755 if (!vmode->mpixelclock) {
1756 crtc_state = drm_atomic_get_crtc_state(state, crtc);
1757 if (hdmi->plat_data->get_enc_in_encoding)
1758 hdmi->hdmi_data.enc_in_encoding =
1759 hdmi->plat_data->get_enc_in_encoding(data);
1760 if (hdmi->plat_data->get_enc_out_encoding)
1761 hdmi->hdmi_data.enc_out_encoding =
1762 hdmi->plat_data->get_enc_out_encoding(data);
1763 if (hdmi->plat_data->get_input_bus_format)
1764 hdmi->hdmi_data.enc_in_bus_format =
1765 hdmi->plat_data->get_input_bus_format(data);
1766 if (hdmi->plat_data->get_output_bus_format)
1767 hdmi->hdmi_data.enc_out_bus_format =
1768 hdmi->plat_data->get_output_bus_format(data);
1769
1770 mode = &crtc_state->mode;
1771 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1772 vmode->mpixelclock = mode->crtc_clock * 1000;
1773 vmode->previous_pixelclock = mode->clock;
1774 vmode->previous_tmdsclock = mode->clock;
1775 vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi,
1776 vmode->mpixelclock);
1777 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1778 vmode->mtmdsclock /= 2;
1779
1780 if (in_bus_format != hdmi->hdmi_data.enc_in_bus_format ||
1781 out_bus_format != hdmi->hdmi_data.enc_out_bus_format)
1782 color_changed = true;
1783 }
1784
1785 if (!hdr_metadata_equal(old_state, new_state) ||
1786 dw_hdmi_color_changed(connector) || color_changed) {
1787 crtc_state = drm_atomic_get_crtc_state(state, crtc);
1788 if (IS_ERR(crtc_state))
1789 return PTR_ERR(crtc_state);
1790
1791 crtc_state->mode_changed = true;
1792 }
1793
1794 return 0;
1795 }
1796
dw_hdmi_connector_force(struct drm_connector * connector)1797 static void dw_hdmi_connector_force(struct drm_connector *connector)
1798 {
1799 struct dw_hdmi_qp *hdmi =
1800 container_of(connector, struct dw_hdmi_qp, connector);
1801
1802 mutex_lock(&hdmi->mutex);
1803
1804 if (hdmi->force != connector->force) {
1805 if (!hdmi->disabled && connector->force == DRM_FORCE_OFF)
1806 extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI,
1807 false);
1808 else if (hdmi->disabled && connector->force == DRM_FORCE_ON)
1809 extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI,
1810 true);
1811 }
1812
1813 hdmi->force = connector->force;
1814 mutex_unlock(&hdmi->mutex);
1815 }
1816
dw_hdmi_qp_fill_modes(struct drm_connector * connector,u32 max_x,u32 max_y)1817 static int dw_hdmi_qp_fill_modes(struct drm_connector *connector, u32 max_x,
1818 u32 max_y)
1819 {
1820 return drm_helper_probe_single_connector_modes(connector, 9000, 9000);
1821 }
1822
1823 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
1824 .fill_modes = dw_hdmi_qp_fill_modes,
1825 .detect = dw_hdmi_connector_detect,
1826 .destroy = drm_connector_cleanup,
1827 .force = dw_hdmi_connector_force,
1828 .reset = drm_atomic_helper_connector_reset,
1829 .set_property = dw_hdmi_connector_set_property,
1830 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1831 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1832 .atomic_set_property = dw_hdmi_atomic_connector_set_property,
1833 .atomic_get_property = dw_hdmi_atomic_connector_get_property,
1834 };
1835
1836 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1837 .get_modes = dw_hdmi_connector_get_modes,
1838 .best_encoder = dw_hdmi_connector_best_encoder,
1839 .atomic_check = dw_hdmi_connector_atomic_check,
1840 };
1841
dw_hdmi_qp_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)1842 static int dw_hdmi_qp_bridge_attach(struct drm_bridge *bridge,
1843 enum drm_bridge_attach_flags flags)
1844 {
1845 struct dw_hdmi_qp *hdmi = bridge->driver_private;
1846 struct drm_encoder *encoder = bridge->encoder;
1847 struct drm_connector *connector = &hdmi->connector;
1848 struct cec_connector_info conn_info;
1849 struct cec_notifier *notifier;
1850
1851 connector->interlace_allowed = 1;
1852 connector->polled = DRM_CONNECTOR_POLL_HPD;
1853
1854 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
1855
1856 drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs,
1857 DRM_MODE_CONNECTOR_HDMIA);
1858
1859 drm_connector_attach_encoder(connector, encoder);
1860 dw_hdmi_attach_properties(hdmi);
1861
1862 cec_fill_conn_info_from_drm(&conn_info, connector);
1863 notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info);
1864 if (!notifier)
1865 return -ENOMEM;
1866
1867 mutex_lock(&hdmi->cec_notifier_mutex);
1868 hdmi->cec_notifier = notifier;
1869 mutex_unlock(&hdmi->cec_notifier_mutex);
1870
1871 return 0;
1872 }
1873
dw_hdmi_qp_bridge_detach(struct drm_bridge * bridge)1874 static void dw_hdmi_qp_bridge_detach(struct drm_bridge *bridge)
1875 {
1876 struct dw_hdmi_qp *hdmi = bridge->driver_private;
1877
1878 mutex_lock(&hdmi->cec_notifier_mutex);
1879 cec_notifier_conn_unregister(hdmi->cec_notifier);
1880 hdmi->cec_notifier = NULL;
1881 mutex_unlock(&hdmi->cec_notifier_mutex);
1882 }
1883
1884 static enum drm_mode_status
dw_hdmi_qp_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)1885 dw_hdmi_qp_bridge_mode_valid(struct drm_bridge *bridge,
1886 const struct drm_display_info *info,
1887 const struct drm_display_mode *mode)
1888 {
1889 struct dw_hdmi_qp *hdmi = bridge->driver_private;
1890 struct drm_connector *connector = &hdmi->connector;
1891 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1892 enum drm_mode_status mode_status = MODE_OK;
1893
1894 if (pdata->mode_valid)
1895 mode_status = pdata->mode_valid(connector, pdata->priv_data,
1896 info, mode);
1897
1898 return mode_status;
1899 }
1900
dw_hdmi_qp_bridge_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * orig_mode,const struct drm_display_mode * mode)1901 static void dw_hdmi_qp_bridge_mode_set(struct drm_bridge *bridge,
1902 const struct drm_display_mode *orig_mode,
1903 const struct drm_display_mode *mode)
1904 {
1905 struct dw_hdmi_qp *hdmi = bridge->driver_private;
1906
1907 mutex_lock(&hdmi->mutex);
1908
1909 /* Store the display mode for plugin/DKMS poweron events */
1910 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1911
1912 mutex_unlock(&hdmi->mutex);
1913 }
1914
dw_hdmi_qp_bridge_atomic_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_state)1915 static void dw_hdmi_qp_bridge_atomic_disable(struct drm_bridge *bridge,
1916 struct drm_bridge_state *old_state)
1917 {
1918 struct dw_hdmi_qp *hdmi = bridge->driver_private;
1919
1920 extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, false);
1921 handle_plugged_change(hdmi, false);
1922 mutex_lock(&hdmi->mutex);
1923 hdmi->disabled = true;
1924 hdmi->curr_conn = NULL;
1925 if (hdmi->phy.ops->disable)
1926 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
1927 mutex_unlock(&hdmi->mutex);
1928 }
1929
dw_hdmi_qp_bridge_atomic_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_state)1930 static void dw_hdmi_qp_bridge_atomic_enable(struct drm_bridge *bridge,
1931 struct drm_bridge_state *old_state)
1932 {
1933 struct dw_hdmi_qp *hdmi = bridge->driver_private;
1934 struct drm_atomic_state *state = old_state->base.state;
1935 struct drm_connector *connector;
1936
1937 connector = drm_atomic_get_new_connector_for_encoder(state,
1938 bridge->encoder);
1939
1940 mutex_lock(&hdmi->mutex);
1941 hdmi->disabled = false;
1942 hdmi->curr_conn = connector;
1943 dw_hdmi_qp_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
1944 mutex_unlock(&hdmi->mutex);
1945 extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, true);
1946 handle_plugged_change(hdmi, true);
1947 }
1948
1949 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1950 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1951 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1952 .atomic_reset = drm_atomic_helper_bridge_reset,
1953 .attach = dw_hdmi_qp_bridge_attach,
1954 .detach = dw_hdmi_qp_bridge_detach,
1955 .mode_set = dw_hdmi_qp_bridge_mode_set,
1956 .mode_valid = dw_hdmi_qp_bridge_mode_valid,
1957 .atomic_enable = dw_hdmi_qp_bridge_atomic_enable,
1958 .atomic_disable = dw_hdmi_qp_bridge_atomic_disable,
1959 };
1960
dw_hdmi_qp_set_cec_adap(struct dw_hdmi_qp * hdmi,struct cec_adapter * adap)1961 void dw_hdmi_qp_set_cec_adap(struct dw_hdmi_qp *hdmi, struct cec_adapter *adap)
1962 {
1963 hdmi->cec_adap = adap;
1964 }
1965 EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_cec_adap);
1966
dw_hdmi_qp_main_hardirq(int irq,void * dev_id)1967 static irqreturn_t dw_hdmi_qp_main_hardirq(int irq, void *dev_id)
1968 {
1969 struct dw_hdmi_qp *hdmi = dev_id;
1970 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
1971 u32 stat;
1972
1973 stat = hdmi_readl(hdmi, MAINUNIT_1_INT_STATUS);
1974
1975 i2c->stat = stat & (I2CM_OP_DONE_IRQ | I2CM_READ_REQUEST_IRQ |
1976 I2CM_NACK_RCVD_IRQ);
1977 hdmi->scdc_intr = stat & (SCDC_UPD_FLAGS_RD_IRQ |
1978 SCDC_UPD_FLAGS_CHG_IRQ |
1979 SCDC_UPD_FLAGS_CLR_IRQ |
1980 SCDC_RR_REPLY_STOP_IRQ |
1981 SCDC_NACK_RCVD_IRQ);
1982 hdmi->flt_intr = stat & (FLT_EXIT_TO_LTSP_IRQ |
1983 FLT_EXIT_TO_LTS4_IRQ |
1984 FLT_EXIT_TO_LTSL_IRQ);
1985
1986 dev_dbg(hdmi->dev, "i2c main unit irq:%#x\n", stat);
1987 if (i2c->stat) {
1988 hdmi_writel(hdmi, i2c->stat, MAINUNIT_1_INT_CLEAR);
1989 complete(&i2c->cmp);
1990 }
1991
1992 if (hdmi->flt_intr) {
1993 dev_dbg(hdmi->dev, "i2c flt irq:%#x\n", hdmi->flt_intr);
1994 hdmi_writel(hdmi, hdmi->flt_intr, MAINUNIT_1_INT_CLEAR);
1995 complete(&hdmi->flt_cmp);
1996 }
1997
1998 if (hdmi->scdc_intr) {
1999 u8 val;
2000
2001 dev_dbg(hdmi->dev, "i2c scdc irq:%#x\n", hdmi->scdc_intr);
2002 hdmi_writel(hdmi, hdmi->scdc_intr, MAINUNIT_1_INT_CLEAR);
2003 val = hdmi_readl(hdmi, SCDC_STATUS0);
2004
2005 /* frl start */
2006 if (val & BIT(4)) {
2007 hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_POLL_EN |
2008 SCDC_UPD_FLAGS_AUTO_CLR, SCDC_CONFIG0);
2009 hdmi_modb(hdmi, 0, SCDC_UPD_FLAGS_RD_IRQ,
2010 MAINUNIT_1_INT_MASK_N);
2011 dev_info(hdmi->dev, "frl start\n");
2012 }
2013
2014 }
2015
2016 if (stat)
2017 return IRQ_HANDLED;
2018
2019 return IRQ_NONE;
2020 }
2021
dw_hdmi_qp_avp_hardirq(int irq,void * dev_id)2022 static irqreturn_t dw_hdmi_qp_avp_hardirq(int irq, void *dev_id)
2023 {
2024 struct dw_hdmi_qp *hdmi = dev_id;
2025 u32 stat;
2026
2027 stat = hdmi_readl(hdmi, AVP_1_INT_STATUS);
2028 if (stat) {
2029 dev_dbg(hdmi->dev, "HDCP irq %#x\n", stat);
2030 stat &= ~stat;
2031 hdmi_writel(hdmi, stat, AVP_1_INT_MASK_N);
2032 return IRQ_WAKE_THREAD;
2033 }
2034
2035 return IRQ_NONE;
2036 }
2037
dw_hdmi_qp_earc_hardirq(int irq,void * dev_id)2038 static irqreturn_t dw_hdmi_qp_earc_hardirq(int irq, void *dev_id)
2039 {
2040 struct dw_hdmi_qp *hdmi = dev_id;
2041 u32 stat;
2042
2043 stat = hdmi_readl(hdmi, EARCRX_0_INT_STATUS);
2044 if (stat) {
2045 dev_dbg(hdmi->dev, "earc irq %#x\n", stat);
2046 stat &= ~stat;
2047 hdmi_writel(hdmi, stat, EARCRX_0_INT_MASK_N);
2048 return IRQ_WAKE_THREAD;
2049 }
2050
2051 return IRQ_NONE;
2052 }
2053
dw_hdmi_qp_avp_irq(int irq,void * dev_id)2054 static irqreturn_t dw_hdmi_qp_avp_irq(int irq, void *dev_id)
2055 {
2056 struct dw_hdmi_qp *hdmi = dev_id;
2057 u32 stat;
2058
2059 stat = hdmi_readl(hdmi, AVP_1_INT_STATUS);
2060
2061 if (!stat)
2062 return IRQ_NONE;
2063
2064 hdmi_writel(hdmi, stat, AVP_1_INT_CLEAR);
2065
2066 return IRQ_HANDLED;
2067 }
2068
dw_hdmi_qp_earc_irq(int irq,void * dev_id)2069 static irqreturn_t dw_hdmi_qp_earc_irq(int irq, void *dev_id)
2070 {
2071 struct dw_hdmi_qp *hdmi = dev_id;
2072 u32 stat;
2073
2074 stat = hdmi_readl(hdmi, EARCRX_0_INT_STATUS);
2075
2076 if (!stat)
2077 return IRQ_NONE;
2078
2079 hdmi_writel(hdmi, stat, EARCRX_0_INT_CLEAR);
2080
2081 hdmi->earc_intr = stat;
2082 complete(&hdmi->earc_cmp);
2083
2084 return IRQ_HANDLED;
2085 }
2086
dw_hdmi_detect_phy(struct dw_hdmi_qp * hdmi)2087 static int dw_hdmi_detect_phy(struct dw_hdmi_qp *hdmi)
2088 {
2089 u8 phy_type;
2090
2091 phy_type = hdmi->plat_data->phy_force_vendor ?
2092 DW_HDMI_PHY_VENDOR_PHY : 0;
2093
2094 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
2095 /* Vendor PHYs require support from the glue layer. */
2096 if (!hdmi->plat_data->qp_phy_ops || !hdmi->plat_data->phy_name) {
2097 dev_err(hdmi->dev,
2098 "Vendor HDMI PHY not supported by glue layer\n");
2099 return -ENODEV;
2100 }
2101
2102 hdmi->phy.ops = hdmi->plat_data->qp_phy_ops;
2103 hdmi->phy.data = hdmi->plat_data->phy_data;
2104 hdmi->phy.name = hdmi->plat_data->phy_name;
2105 }
2106
2107 return 0;
2108 }
2109
dw_hdmi_qp_cec_set_hpd(struct dw_hdmi_qp * hdmi,bool plug_in,bool change)2110 void dw_hdmi_qp_cec_set_hpd(struct dw_hdmi_qp *hdmi, bool plug_in, bool change)
2111 {
2112 enum drm_connector_status status = plug_in ?
2113 connector_status_connected : connector_status_disconnected;
2114
2115 if (!plug_in)
2116 cec_notifier_set_phys_addr(hdmi->cec_notifier,
2117 CEC_PHYS_ADDR_INVALID);
2118
2119 if (hdmi->bridge.dev) {
2120 if (change && hdmi->cec_adap &&
2121 hdmi->cec_adap->devnode.registered)
2122 cec_queue_pin_hpd_event(hdmi->cec_adap,
2123 hdmi->hpd_state,
2124 ktime_get());
2125 drm_bridge_hpd_notify(&hdmi->bridge, status);
2126 }
2127 }
2128 EXPORT_SYMBOL_GPL(dw_hdmi_qp_cec_set_hpd);
2129
2130 static const struct regmap_config hdmi_regmap_config = {
2131 .reg_bits = 32,
2132 .val_bits = 32,
2133 .reg_stride = 4,
2134 .max_register = EARCRX_1_INT_FORCE,
2135 };
2136
2137 static struct dw_hdmi_qp *
__dw_hdmi_probe(struct platform_device * pdev,const struct dw_hdmi_plat_data * plat_data)2138 __dw_hdmi_probe(struct platform_device *pdev,
2139 const struct dw_hdmi_plat_data *plat_data)
2140 {
2141 struct device *dev = &pdev->dev;
2142 struct device_node *np = dev->of_node;
2143 struct device_node *ddc_node;
2144 struct dw_hdmi_qp *hdmi;
2145 struct dw_hdmi_qp_i2s_audio_data audio;
2146 struct platform_device_info pdevinfo;
2147 struct resource *iores = NULL;
2148 int irq;
2149 int ret;
2150
2151 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2152 if (!hdmi)
2153 return ERR_PTR(-ENOMEM);
2154
2155 hdmi->connector.stereo_allowed = 1;
2156 hdmi->plat_data = plat_data;
2157 hdmi->dev = dev;
2158 hdmi->sample_rate = 48000;
2159 hdmi->disabled = true;
2160
2161 mutex_init(&hdmi->mutex);
2162 mutex_init(&hdmi->audio_mutex);
2163 mutex_init(&hdmi->cec_notifier_mutex);
2164 spin_lock_init(&hdmi->audio_lock);
2165
2166 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2167 if (ddc_node) {
2168 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
2169 of_node_put(ddc_node);
2170 if (!hdmi->ddc) {
2171 dev_dbg(hdmi->dev, "failed to read ddc node\n");
2172 return ERR_PTR(-EPROBE_DEFER);
2173 }
2174
2175 } else {
2176 dev_dbg(hdmi->dev, "no ddc property found\n");
2177 }
2178
2179 if (!plat_data->regm) {
2180 const struct regmap_config *reg_config;
2181
2182 reg_config = &hdmi_regmap_config;
2183
2184 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2185 hdmi->regs = devm_ioremap_resource(dev, iores);
2186 if (IS_ERR(hdmi->regs)) {
2187 ret = PTR_ERR(hdmi->regs);
2188 goto err_res;
2189 }
2190
2191 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
2192 if (IS_ERR(hdmi->regm)) {
2193 dev_err(dev, "Failed to configure regmap\n");
2194 ret = PTR_ERR(hdmi->regm);
2195 goto err_res;
2196 }
2197 } else {
2198 hdmi->regm = plat_data->regm;
2199 }
2200
2201 ret = dw_hdmi_detect_phy(hdmi);
2202 if (ret < 0)
2203 goto err_res;
2204
2205 hdmi_writel(hdmi, 0, MAINUNIT_0_INT_MASK_N);
2206 hdmi_writel(hdmi, 0, MAINUNIT_1_INT_MASK_N);
2207 hdmi_writel(hdmi, 428571429, TIMER_BASE_CONFIG0);
2208
2209 irq = platform_get_irq(pdev, 0);
2210 if (irq < 0) {
2211 ret = irq;
2212 goto err_res;
2213 }
2214
2215 hdmi->avp_irq = irq;
2216 ret = devm_request_threaded_irq(dev, hdmi->avp_irq,
2217 dw_hdmi_qp_avp_hardirq,
2218 dw_hdmi_qp_avp_irq, IRQF_SHARED,
2219 dev_name(dev), hdmi);
2220 if (ret)
2221 goto err_res;
2222
2223 irq = platform_get_irq(pdev, 2);
2224 if (irq < 0) {
2225 ret = irq;
2226 goto err_res;
2227 }
2228
2229 hdmi->earc_irq = irq;
2230 ret = devm_request_threaded_irq(dev, hdmi->earc_irq,
2231 dw_hdmi_qp_earc_hardirq,
2232 dw_hdmi_qp_earc_irq, IRQF_SHARED,
2233 dev_name(dev), hdmi);
2234 if (ret)
2235 goto err_res;
2236
2237 irq = platform_get_irq(pdev, 3);
2238 if (irq < 0) {
2239 ret = irq;
2240 goto err_res;
2241 }
2242
2243 hdmi->main_irq = irq;
2244 ret = devm_request_threaded_irq(dev, hdmi->main_irq,
2245 dw_hdmi_qp_main_hardirq, NULL,
2246 IRQF_SHARED, dev_name(dev), hdmi);
2247 if (ret)
2248 goto err_res;
2249
2250 hdmi_init_clk_regenerator(hdmi);
2251
2252 /* If DDC bus is not specified, try to register HDMI I2C bus */
2253 if (!hdmi->ddc) {
2254 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2255 if (IS_ERR(hdmi->ddc))
2256 hdmi->ddc = NULL;
2257 /*
2258 * Read high and low time from device tree. If not available use
2259 * the default timing scl clock rate is about 99.6KHz.
2260 */
2261 if (of_property_read_u32(np, "ddc-i2c-scl-high-time-ns",
2262 &hdmi->i2c->scl_high_ns))
2263 hdmi->i2c->scl_high_ns = 4708;
2264 if (of_property_read_u32(np, "ddc-i2c-scl-low-time-ns",
2265 &hdmi->i2c->scl_low_ns))
2266 hdmi->i2c->scl_low_ns = 4916;
2267 }
2268
2269 hdmi->bridge.driver_private = hdmi;
2270 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
2271 #ifdef CONFIG_OF
2272 hdmi->bridge.of_node = pdev->dev.of_node;
2273 #endif
2274
2275 if (hdmi->phy.ops->setup_hpd)
2276 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
2277
2278 hdmi->connector.ycbcr_420_allowed = hdmi->plat_data->ycbcr_420_allowed;
2279
2280 audio.hdmi = hdmi;
2281 audio.eld = hdmi->connector.eld;
2282 audio.write = hdmi_writel;
2283 audio.read = hdmi_readl;
2284 audio.mod = hdmi_modb;
2285 hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
2286 hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
2287
2288 memset(&pdevinfo, 0, sizeof(pdevinfo));
2289 pdevinfo.parent = dev;
2290 pdevinfo.id = PLATFORM_DEVID_AUTO;
2291 pdevinfo.name = "dw-hdmi-qp-i2s-audio";
2292 pdevinfo.data = &audio;
2293 pdevinfo.size_data = sizeof(audio);
2294 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2295 hdmi->audio = platform_device_register_full(&pdevinfo);
2296
2297 hdmi->extcon = devm_extcon_dev_allocate(hdmi->dev, dw_hdmi_cable);
2298 if (IS_ERR(hdmi->extcon)) {
2299 dev_err(hdmi->dev, "allocate extcon failed\n");
2300 ret = PTR_ERR(hdmi->extcon);
2301 goto err_res;
2302 }
2303
2304 ret = devm_extcon_dev_register(hdmi->dev, hdmi->extcon);
2305 if (ret) {
2306 dev_err(hdmi->dev, "failed to register extcon: %d\n", ret);
2307 goto err_res;
2308 }
2309
2310 ret = extcon_set_property_capability(hdmi->extcon, EXTCON_DISP_HDMI,
2311 EXTCON_PROP_DISP_HPD);
2312 if (ret) {
2313 dev_err(hdmi->dev,
2314 "failed to set USB property capability: %d\n", ret);
2315 goto err_res;
2316 }
2317
2318 /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */
2319 if (hdmi->i2c)
2320 dw_hdmi_i2c_init(hdmi);
2321
2322 init_completion(&hdmi->flt_cmp);
2323 init_completion(&hdmi->earc_cmp);
2324
2325 if (of_property_read_bool(np, "scramble-low-rates"))
2326 hdmi->scramble_low_rates = true;
2327
2328 return hdmi;
2329
2330 err_res:
2331 if (hdmi->i2c)
2332 i2c_del_adapter(&hdmi->i2c->adap);
2333 else
2334 i2c_put_adapter(hdmi->ddc);
2335
2336 return ERR_PTR(ret);
2337 }
2338
__dw_hdmi_remove(struct dw_hdmi_qp * hdmi)2339 static void __dw_hdmi_remove(struct dw_hdmi_qp *hdmi)
2340 {
2341 if (hdmi->avp_irq)
2342 disable_irq(hdmi->avp_irq);
2343
2344 if (hdmi->main_irq)
2345 disable_irq(hdmi->main_irq);
2346
2347 if (hdmi->earc_irq)
2348 disable_irq(hdmi->earc_irq);
2349
2350 dw_hdmi_destroy_properties(hdmi);
2351 hdmi->connector.funcs->destroy(&hdmi->connector);
2352
2353 if (hdmi->audio && !IS_ERR(hdmi->audio))
2354 platform_device_unregister(hdmi->audio);
2355
2356 if (hdmi->bridge.encoder)
2357 hdmi->bridge.encoder->funcs->destroy(hdmi->bridge.encoder);
2358
2359 if (hdmi->i2c)
2360 i2c_del_adapter(&hdmi->i2c->adap);
2361 else
2362 i2c_put_adapter(hdmi->ddc);
2363 }
2364
2365 /* -----------------------------------------------------------------------------
2366 * Bind/unbind API, used from platforms based on the component framework.
2367 */
dw_hdmi_qp_bind(struct platform_device * pdev,struct drm_encoder * encoder,struct dw_hdmi_plat_data * plat_data)2368 struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev,
2369 struct drm_encoder *encoder,
2370 struct dw_hdmi_plat_data *plat_data)
2371 {
2372 struct dw_hdmi_qp *hdmi;
2373 int ret;
2374
2375 hdmi = __dw_hdmi_probe(pdev, plat_data);
2376 if (IS_ERR(hdmi))
2377 return hdmi;
2378
2379 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0);
2380 if (ret) {
2381 __dw_hdmi_remove(hdmi);
2382 dev_err(hdmi->dev, "Failed to initialize bridge with drm\n");
2383 return ERR_PTR(ret);
2384 }
2385
2386 plat_data->connector = &hdmi->connector;
2387
2388 return hdmi;
2389 }
2390 EXPORT_SYMBOL_GPL(dw_hdmi_qp_bind);
2391
dw_hdmi_qp_unbind(struct dw_hdmi_qp * hdmi)2392 void dw_hdmi_qp_unbind(struct dw_hdmi_qp *hdmi)
2393 {
2394 __dw_hdmi_remove(hdmi);
2395 }
2396 EXPORT_SYMBOL_GPL(dw_hdmi_qp_unbind);
2397
dw_hdmi_qp_suspend(struct device * dev,struct dw_hdmi_qp * hdmi)2398 void dw_hdmi_qp_suspend(struct device *dev, struct dw_hdmi_qp *hdmi)
2399 {
2400 if (!hdmi) {
2401 dev_warn(dev, "Hdmi has not been initialized\n");
2402 return;
2403 }
2404
2405 mutex_lock(&hdmi->mutex);
2406
2407 /*
2408 * When system shutdown, hdmi should be disabled.
2409 * When system suspend, dw_hdmi_qp_bridge_disable will disable hdmi first.
2410 * To prevent duplicate operation, we should determine whether hdmi
2411 * has been disabled.
2412 */
2413 if (!hdmi->disabled)
2414 hdmi->disabled = true;
2415 mutex_unlock(&hdmi->mutex);
2416
2417 if (hdmi->avp_irq)
2418 disable_irq(hdmi->avp_irq);
2419
2420 if (hdmi->main_irq)
2421 disable_irq(hdmi->main_irq);
2422
2423 if (hdmi->earc_irq)
2424 disable_irq(hdmi->earc_irq);
2425
2426 pinctrl_pm_select_sleep_state(dev);
2427 }
2428 EXPORT_SYMBOL_GPL(dw_hdmi_qp_suspend);
2429
dw_hdmi_qp_resume(struct device * dev,struct dw_hdmi_qp * hdmi)2430 void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi)
2431 {
2432 if (!hdmi) {
2433 dev_warn(dev, "Hdmi has not been initialized\n");
2434 return;
2435 }
2436
2437 hdmi_writel(hdmi, 0, MAINUNIT_0_INT_MASK_N);
2438 hdmi_writel(hdmi, 0, MAINUNIT_1_INT_MASK_N);
2439 hdmi_writel(hdmi, 428571429, TIMER_BASE_CONFIG0);
2440
2441 pinctrl_pm_select_default_state(dev);
2442 mutex_lock(&hdmi->mutex);
2443 if (hdmi->i2c)
2444 dw_hdmi_i2c_init(hdmi);
2445 if (hdmi->avp_irq)
2446 enable_irq(hdmi->avp_irq);
2447
2448 if (hdmi->main_irq)
2449 enable_irq(hdmi->main_irq);
2450
2451 if (hdmi->earc_irq)
2452 enable_irq(hdmi->earc_irq);
2453
2454 mutex_unlock(&hdmi->mutex);
2455 }
2456 EXPORT_SYMBOL_GPL(dw_hdmi_qp_resume);
2457
2458 MODULE_AUTHOR("Algea Cao <algea.cao@rock-chips.com>");
2459 MODULE_DESCRIPTION("DW HDMI QP transmitter driver");
2460 MODULE_LICENSE("GPL");
2461 MODULE_ALIAS("platform:dw-hdmi-qp");
2462