1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) Rockchip Electronics Co.Ltd 4 * Author: 5 * Algea Cao <algea.cao@rock-chips.com> 6 */ 7 #ifndef __DW_HDMI_QP_H__ 8 #define __DW_HDMI_QP_H__ 9 /* Main Unit Registers */ 10 #define CORE_ID 0x0 11 #define VER_NUMBER 0x4 12 #define VER_TYPE 0x8 13 #define CONFIG_REG 0xc 14 #define CONFIG_CEC BIT(28) 15 #define CONFIG_AUD_UD BIT(23) 16 #define CORE_TIMESTAMP_HHMM 0x14 17 #define CORE_TIMESTAMP_MMDD 0x18 18 #define CORE_TIMESTAMP_YYYY 0x1c 19 /* Reset Manager Registers */ 20 #define GLOBAL_SWRESET_REQUEST 0x40 21 #define EARCRX_CMDC_SWINIT_P BIT(27) 22 #define AVP_DATAPATH_PACKET_AUDIO_SWINIT_P BIT(10) 23 #define GLOBAL_SWDISABLE 0x44 24 #define CEC_SWDISABLE BIT(17) 25 #define AVP_DATAPATH_PACKET_AUDIO_SWDISABLE BIT(10) 26 #define AVP_DATAPATH_VIDEO_SWDISABLE BIT(6) 27 #define RESET_MANAGER_CONFIG0 0x48 28 #define RESET_MANAGER_STATUS0 0x50 29 #define RESET_MANAGER_STATUS1 0x54 30 #define RESET_MANAGER_STATUS2 0x58 31 /* Timer Base Registers */ 32 #define TIMER_BASE_CONFIG0 0x80 33 #define TIMER_BASE_STATUS0 0x84 34 /* CMU Registers */ 35 #define CMU_CONFIG0 0xa0 36 #define CMU_CONFIG1 0xa4 37 #define CMU_CONFIG2 0xa8 38 #define CMU_CONFIG3 0xac 39 #define CMU_STATUS 0xb0 40 #define EARC_BPCLK_OFF BIT(9) 41 #define AUDCLK_OFF BIT(7) 42 #define LINKQPCLK_OFF BIT(5) 43 #define VIDQPCLK_OFF BIT(3) 44 #define IPI_CLK_OFF BIT(1) 45 #define CMU_IPI_CLK_FREQ 0xb4 46 #define CMU_VIDQPCLK_FREQ 0xb8 47 #define CMU_LINKQPCLK_FREQ 0xbc 48 #define CMU_AUDQPCLK_FREQ 0xc0 49 #define CMU_EARC_BPCLK_FREQ 0xc4 50 /* I2CM Registers */ 51 #define I2CM_SM_SCL_CONFIG0 0xe0 52 #define I2CM_FM_SCL_CONFIG0 0xe4 53 #define I2CM_CONFIG0 0xe8 54 #define I2CM_CONTROL0 0xec 55 #define I2CM_STATUS0 0xf0 56 #define I2CM_INTERFACE_CONTROL0 0xf4 57 #define I2CM_ADDR 0xff000 58 #define I2CM_SLVADDR 0xfe0 59 #define I2CM_WR_MASK 0x1e 60 #define I2CM_EXT_READ BIT(4) 61 #define I2CM_SHORT_READ BIT(3) 62 #define I2CM_FM_READ BIT(2) 63 #define I2CM_FM_WRITE BIT(1) 64 #define I2CM_FM_EN BIT(0) 65 #define I2CM_INTERFACE_CONTROL1 0xf8 66 #define I2CM_SEG_PTR 0x7f80 67 #define I2CM_SEG_ADDR 0x7f 68 #define I2CM_INTERFACE_WRDATA_0_3 0xfc 69 #define I2CM_INTERFACE_WRDATA_4_7 0x100 70 #define I2CM_INTERFACE_WRDATA_8_11 0x104 71 #define I2CM_INTERFACE_WRDATA_12_15 0x108 72 #define I2CM_INTERFACE_RDDATA_0_3 0x10c 73 #define I2CM_INTERFACE_RDDATA_4_7 0x110 74 #define I2CM_INTERFACE_RDDATA_8_11 0x114 75 #define I2CM_INTERFACE_RDDATA_12_15 0x118 76 /* SCDC Registers */ 77 #define SCDC_CONFIG0 0x140 78 #define SCDC_I2C_FM_EN BIT(12) 79 #define SCDC_UPD_FLAGS_AUTO_CLR BIT(6) 80 #define SCDC_UPD_FLAGS_POLL_EN BIT(4) 81 #define SCDC_CONTROL0 0x148 82 #define SCDC_STATUS0 0x150 83 #define STATUS_UPDATE BIT(0) 84 #define FRL_START BIT(4) 85 #define FLT_UPDATE BIT(5) 86 /* FLT Registers */ 87 #define FLT_CONFIG0 0x160 88 #define FLT_CONFIG1 0x164 89 #define FLT_CONFIG2 0x168 90 #define FLT_CONTROL0 0x170 91 /* Main Unit 2 Registers */ 92 #define MAINUNIT_STATUS0 0x180 93 /* Video Interface Registers */ 94 #define VIDEO_INTERFACE_CONFIG0 0x800 95 #define VIDEO_INTERFACE_CONFIG1 0x804 96 #define VIDEO_INTERFACE_CONFIG2 0x808 97 #define VIDEO_INTERFACE_CONTROL0 0x80c 98 #define VIDEO_INTERFACE_STATUS0 0x814 99 /* Video Packing Registers */ 100 #define VIDEO_PACKING_CONFIG0 0x81c 101 /* Audio Interface Registers */ 102 #define AUDIO_INTERFACE_CONFIG0 0x820 103 #define AUD_IF_SEL_MSK 0x3 104 #define AUD_IF_SPDIF 0x2 105 #define AUD_IF_I2S 0x1 106 #define AUD_IF_PAI 0x0 107 #define AUD_FIFO_INIT_ON_OVF_MSK BIT(2) 108 #define AUD_FIFO_INIT_ON_OVF_EN BIT(2) 109 #define I2S_LINES_EN_MSK GENMASK(7, 4) 110 #define I2S_LINES_EN(x) BIT(x + 4) 111 #define I2S_BPCUV_RCV_MSK BIT(12) 112 #define I2S_BPCUV_RCV_EN BIT(12) 113 #define I2S_BPCUV_RCV_DIS 0 114 #define SPDIF_LINES_EN GENMASK(19, 16) 115 #define AUD_FORMAT_MSK GENMASK(26, 24) 116 #define AUD_3DOBA (0x7 << 24) 117 #define AUD_3DASP (0x6 << 24) 118 #define AUD_MSOBA (0x5 << 24) 119 #define AUD_MSASP (0x4 << 24) 120 #define AUD_HBR (0x3 << 24) 121 #define AUD_DST (0x2 << 24) 122 #define AUD_OBA (0x1 << 24) 123 #define AUD_ASP (0x0 << 24) 124 #define AUDIO_INTERFACE_CONFIG1 0x824 125 #define AUDIO_INTERFACE_CONTROL0 0x82c 126 #define AUDIO_FIFO_CLR_P BIT(0) 127 #define AUDIO_INTERFACE_STATUS0 0x834 128 /* Frame Composer Registers */ 129 #define FRAME_COMPOSER_CONFIG0 0x840 130 #define FRAME_COMPOSER_CONFIG1 0x844 131 #define FRAME_COMPOSER_CONFIG2 0x848 132 #define FRAME_COMPOSER_CONFIG3 0x84c 133 #define FRAME_COMPOSER_CONFIG4 0x850 134 #define FRAME_COMPOSER_CONFIG5 0x854 135 #define FRAME_COMPOSER_CONFIG6 0x858 136 #define FRAME_COMPOSER_CONFIG7 0x85c 137 #define FRAME_COMPOSER_CONFIG8 0x860 138 #define FRAME_COMPOSER_CONFIG9 0x864 139 #define FRAME_COMPOSER_CONTROL0 0x86c 140 /* Video Monitor Registers */ 141 #define VIDEO_MONITOR_CONFIG0 0x880 142 #define VIDEO_MONITOR_STATUS0 0x884 143 #define VIDEO_MONITOR_STATUS1 0x888 144 #define VIDEO_MONITOR_STATUS2 0x88c 145 #define VIDEO_MONITOR_STATUS3 0x890 146 #define VIDEO_MONITOR_STATUS4 0x894 147 #define VIDEO_MONITOR_STATUS5 0x898 148 #define VIDEO_MONITOR_STATUS6 0x89c 149 /* HDCP2 Logic Registers */ 150 #define HDCP2LOGIC_CONFIG0 0x8e0 151 #define HDCP2_BYPASS BIT(0) 152 #define HDCP2LOGIC_ESM_GPIO_IN 0x8e4 153 #define HDCP2LOGIC_ESM_GPIO_OUT 0x8e8 154 /* HDCP14 Registers */ 155 #define HDCP14_CONFIG0 0x900 156 #define HDCP14_CONFIG1 0x904 157 #define HDCP14_CONFIG2 0x908 158 #define HDCP14_CONFIG3 0x90c 159 #define HDCP14_KEY_SEED 0x914 160 #define HDCP14_KEY_H 0x918 161 #define HDCP14_KEY_L 0x91c 162 #define HDCP14_KEY_STATUS 0x920 163 #define HDCP14_AKSV_H 0x924 164 #define HDCP14_AKSV_L 0x928 165 #define HDCP14_AN_H 0x92c 166 #define HDCP14_AN_L 0x930 167 #define HDCP14_STATUS0 0x934 168 #define HDCP14_STATUS1 0x938 169 /* Scrambler Registers */ 170 #define SCRAMB_CONFIG0 0x960 171 /* Video Configuration Registers */ 172 #define LINK_CONFIG0 0x968 173 #define OPMODE_FRL_4LANES BIT(8) 174 #define OPMODE_DVI BIT(4) 175 #define OPMODE_FRL BIT(0) 176 /* TMDS FIFO Registers */ 177 #define TMDS_FIFO_CONFIG0 0x970 178 #define TMDS_FIFO_CONTROL0 0x974 179 /* FRL RSFEC Registers */ 180 #define FRL_RSFEC_CONFIG0 0xa20 181 #define FRL_RSFEC_STATUS0 0xa30 182 /* FRL Packetizer Registers */ 183 #define FRL_PKTZ_CONFIG0 0xa40 184 #define FRL_PKTZ_CONTROL0 0xa44 185 #define FRL_PKTZ_CONTROL1 0xa50 186 #define FRL_PKTZ_STATUS1 0xa54 187 /* Packet Scheduler Registers */ 188 #define PKTSCHED_CONFIG0 0xa80 189 #define PKTSCHED_PRQUEUE0_CONFIG0 0xa84 190 #define PKTSCHED_PRQUEUE1_CONFIG0 0xa88 191 #define PKTSCHED_PRQUEUE2_CONFIG0 0xa8c 192 #define PKTSCHED_PRQUEUE2_CONFIG1 0xa90 193 #define PKTSCHED_PRQUEUE2_CONFIG2 0xa94 194 #define PKTSCHED_PKT_CONFIG0 0xa98 195 #define PKTSCHED_PKT_CONFIG1 0xa9c 196 #define PKTSCHED_PKT_CONFIG2 0xaa0 197 #define PKTSCHED_PKT_CONFIG3 0xaa4 198 #define PKTSCHED_PKT_EN 0xaa8 199 #define PKTSCHED_DRMI_TX_EN BIT(17) 200 #define PKTSCHED_AUDI_TX_EN BIT(15) 201 #define PKTSCHED_AVI_TX_EN BIT(13) 202 #define PKTSCHED_EMP_CVTEM_TX_EN BIT(10) 203 #define PKTSCHED_AMD_TX_EN BIT(8) 204 #define PKTSCHED_GCP_TX_EN BIT(3) 205 #define PKTSCHED_AUDS_TX_EN BIT(2) 206 #define PKTSCHED_ACR_TX_EN BIT(1) 207 #define PKTSCHED_PKT_CONTROL0 0xaac 208 #define PKTSCHED_PKT_SEND 0xab0 209 #define PKTSCHED_PKT_STATUS0 0xab4 210 #define PKTSCHED_PKT_STATUS1 0xab8 211 #define PKT_NULL_CONTENTS0 0xb00 212 #define PKT_NULL_CONTENTS1 0xb04 213 #define PKT_NULL_CONTENTS2 0xb08 214 #define PKT_NULL_CONTENTS3 0xb0c 215 #define PKT_NULL_CONTENTS4 0xb10 216 #define PKT_NULL_CONTENTS5 0xb14 217 #define PKT_NULL_CONTENTS6 0xb18 218 #define PKT_NULL_CONTENTS7 0xb1c 219 #define PKT_ACP_CONTENTS0 0xb20 220 #define PKT_ACP_CONTENTS1 0xb24 221 #define PKT_ACP_CONTENTS2 0xb28 222 #define PKT_ACP_CONTENTS3 0xb2c 223 #define PKT_ACP_CONTENTS4 0xb30 224 #define PKT_ACP_CONTENTS5 0xb34 225 #define PKT_ACP_CONTENTS6 0xb38 226 #define PKT_ACP_CONTENTS7 0xb3c 227 #define PKT_ISRC1_CONTENTS0 0xb40 228 #define PKT_ISRC1_CONTENTS1 0xb44 229 #define PKT_ISRC1_CONTENTS2 0xb48 230 #define PKT_ISRC1_CONTENTS3 0xb4c 231 #define PKT_ISRC1_CONTENTS4 0xb50 232 #define PKT_ISRC1_CONTENTS5 0xb54 233 #define PKT_ISRC1_CONTENTS6 0xb58 234 #define PKT_ISRC1_CONTENTS7 0xb5c 235 #define PKT_ISRC2_CONTENTS0 0xb60 236 #define PKT_ISRC2_CONTENTS1 0xb64 237 #define PKT_ISRC2_CONTENTS2 0xb68 238 #define PKT_ISRC2_CONTENTS3 0xb6c 239 #define PKT_ISRC2_CONTENTS4 0xb70 240 #define PKT_ISRC2_CONTENTS5 0xb74 241 #define PKT_ISRC2_CONTENTS6 0xb78 242 #define PKT_ISRC2_CONTENTS7 0xb7c 243 #define PKT_GMD_CONTENTS0 0xb80 244 #define PKT_GMD_CONTENTS1 0xb84 245 #define PKT_GMD_CONTENTS2 0xb88 246 #define PKT_GMD_CONTENTS3 0xb8c 247 #define PKT_GMD_CONTENTS4 0xb90 248 #define PKT_GMD_CONTENTS5 0xb94 249 #define PKT_GMD_CONTENTS6 0xb98 250 #define PKT_GMD_CONTENTS7 0xb9c 251 #define PKT_AMD_CONTENTS0 0xba0 252 #define PKT_AMD_CONTENTS1 0xba4 253 #define PKT_AMD_CONTENTS2 0xba8 254 #define PKT_AMD_CONTENTS3 0xbac 255 #define PKT_AMD_CONTENTS4 0xbb0 256 #define PKT_AMD_CONTENTS5 0xbb4 257 #define PKT_AMD_CONTENTS6 0xbb8 258 #define PKT_AMD_CONTENTS7 0xbbc 259 #define PKT_VSI_CONTENTS0 0xbc0 260 #define PKT_VSI_CONTENTS1 0xbc4 261 #define PKT_VSI_CONTENTS2 0xbc8 262 #define PKT_VSI_CONTENTS3 0xbcc 263 #define PKT_VSI_CONTENTS4 0xbd0 264 #define PKT_VSI_CONTENTS5 0xbd4 265 #define PKT_VSI_CONTENTS6 0xbd8 266 #define PKT_VSI_CONTENTS7 0xbdc 267 #define PKT_AVI_CONTENTS0 0xbe0 268 #define HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT BIT(4) 269 #define HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR 0x04 270 #define HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR 0x08 271 #define HDMI_FC_AVICONF2_IT_CONTENT_VALID 0x80 272 #define PKT_AVI_CONTENTS1 0xbe4 273 #define PKT_AVI_CONTENTS2 0xbe8 274 #define PKT_AVI_CONTENTS3 0xbec 275 #define PKT_AVI_CONTENTS4 0xbf0 276 #define PKT_AVI_CONTENTS5 0xbf4 277 #define PKT_AVI_CONTENTS6 0xbf8 278 #define PKT_AVI_CONTENTS7 0xbfc 279 #define PKT_SPDI_CONTENTS0 0xc00 280 #define PKT_SPDI_CONTENTS1 0xc04 281 #define PKT_SPDI_CONTENTS2 0xc08 282 #define PKT_SPDI_CONTENTS3 0xc0c 283 #define PKT_SPDI_CONTENTS4 0xc10 284 #define PKT_SPDI_CONTENTS5 0xc14 285 #define PKT_SPDI_CONTENTS6 0xc18 286 #define PKT_SPDI_CONTENTS7 0xc1c 287 #define PKT_AUDI_CONTENTS0 0xc20 288 #define PKT_AUDI_CONTENTS1 0xc24 289 #define PKT_AUDI_CONTENTS2 0xc28 290 #define PKT_AUDI_CONTENTS3 0xc2c 291 #define PKT_AUDI_CONTENTS4 0xc30 292 #define PKT_AUDI_CONTENTS5 0xc34 293 #define PKT_AUDI_CONTENTS6 0xc38 294 #define PKT_AUDI_CONTENTS7 0xc3c 295 #define PKT_NVI_CONTENTS0 0xc40 296 #define PKT_NVI_CONTENTS1 0xc44 297 #define PKT_NVI_CONTENTS2 0xc48 298 #define PKT_NVI_CONTENTS3 0xc4c 299 #define PKT_NVI_CONTENTS4 0xc50 300 #define PKT_NVI_CONTENTS5 0xc54 301 #define PKT_NVI_CONTENTS6 0xc58 302 #define PKT_NVI_CONTENTS7 0xc5c 303 #define PKT_DRMI_CONTENTS0 0xc60 304 #define PKT_DRMI_CONTENTS1 0xc64 305 #define PKT_DRMI_CONTENTS2 0xc68 306 #define PKT_DRMI_CONTENTS3 0xc6c 307 #define PKT_DRMI_CONTENTS4 0xc70 308 #define PKT_DRMI_CONTENTS5 0xc74 309 #define PKT_DRMI_CONTENTS6 0xc78 310 #define PKT_DRMI_CONTENTS7 0xc7c 311 #define PKT_GHDMI1_CONTENTS0 0xc80 312 #define PKT_GHDMI1_CONTENTS1 0xc84 313 #define PKT_GHDMI1_CONTENTS2 0xc88 314 #define PKT_GHDMI1_CONTENTS3 0xc8c 315 #define PKT_GHDMI1_CONTENTS4 0xc90 316 #define PKT_GHDMI1_CONTENTS5 0xc94 317 #define PKT_GHDMI1_CONTENTS6 0xc98 318 #define PKT_GHDMI1_CONTENTS7 0xc9c 319 #define PKT_GHDMI2_CONTENTS0 0xca0 320 #define PKT_GHDMI2_CONTENTS1 0xca4 321 #define PKT_GHDMI2_CONTENTS2 0xca8 322 #define PKT_GHDMI2_CONTENTS3 0xcac 323 #define PKT_GHDMI2_CONTENTS4 0xcb0 324 #define PKT_GHDMI2_CONTENTS5 0xcb4 325 #define PKT_GHDMI2_CONTENTS6 0xcb8 326 #define PKT_GHDMI2_CONTENTS7 0xcbc 327 /* EMP Packetizer Registers */ 328 #define PKT_EMP_CONFIG0 0xce0 329 #define PKT_EMP_CONTROL0 0xcec 330 #define PKT_EMP_CONTROL1 0xcf0 331 #define PKT_EMP_CONTROL2 0xcf4 332 #define PKT_EMP_VTEM_CONTENTS0 0xd00 333 #define PKT_EMP_VTEM_CONTENTS1 0xd04 334 #define PKT_EMP_VTEM_CONTENTS2 0xd08 335 #define PKT_EMP_VTEM_CONTENTS3 0xd0c 336 #define PKT_EMP_VTEM_CONTENTS4 0xd10 337 #define PKT_EMP_VTEM_CONTENTS5 0xd14 338 #define PKT_EMP_VTEM_CONTENTS6 0xd18 339 #define PKT_EMP_VTEM_CONTENTS7 0xd1c 340 #define PKT0_EMP_CVTEM_CONTENTS0 0xd20 341 #define PKT0_EMP_CVTEM_CONTENTS1 0xd24 342 #define PKT0_EMP_CVTEM_CONTENTS2 0xd28 343 #define PKT0_EMP_CVTEM_CONTENTS3 0xd2c 344 #define PKT0_EMP_CVTEM_CONTENTS4 0xd30 345 #define PKT0_EMP_CVTEM_CONTENTS5 0xd34 346 #define PKT0_EMP_CVTEM_CONTENTS6 0xd38 347 #define PKT0_EMP_CVTEM_CONTENTS7 0xd3c 348 #define PKT1_EMP_CVTEM_CONTENTS0 0xd40 349 #define PKT1_EMP_CVTEM_CONTENTS1 0xd44 350 #define PKT1_EMP_CVTEM_CONTENTS2 0xd48 351 #define PKT1_EMP_CVTEM_CONTENTS3 0xd4c 352 #define PKT1_EMP_CVTEM_CONTENTS4 0xd50 353 #define PKT1_EMP_CVTEM_CONTENTS5 0xd54 354 #define PKT1_EMP_CVTEM_CONTENTS6 0xd58 355 #define PKT1_EMP_CVTEM_CONTENTS7 0xd5c 356 #define PKT2_EMP_CVTEM_CONTENTS0 0xd60 357 #define PKT2_EMP_CVTEM_CONTENTS1 0xd64 358 #define PKT2_EMP_CVTEM_CONTENTS2 0xd68 359 #define PKT2_EMP_CVTEM_CONTENTS3 0xd6c 360 #define PKT2_EMP_CVTEM_CONTENTS4 0xd70 361 #define PKT2_EMP_CVTEM_CONTENTS5 0xd74 362 #define PKT2_EMP_CVTEM_CONTENTS6 0xd78 363 #define PKT2_EMP_CVTEM_CONTENTS7 0xd7c 364 #define PKT3_EMP_CVTEM_CONTENTS0 0xd80 365 #define PKT3_EMP_CVTEM_CONTENTS1 0xd84 366 #define PKT3_EMP_CVTEM_CONTENTS2 0xd88 367 #define PKT3_EMP_CVTEM_CONTENTS3 0xd8c 368 #define PKT3_EMP_CVTEM_CONTENTS4 0xd90 369 #define PKT3_EMP_CVTEM_CONTENTS5 0xd94 370 #define PKT3_EMP_CVTEM_CONTENTS6 0xd98 371 #define PKT3_EMP_CVTEM_CONTENTS7 0xd9c 372 #define PKT4_EMP_CVTEM_CONTENTS0 0xda0 373 #define PKT4_EMP_CVTEM_CONTENTS1 0xda4 374 #define PKT4_EMP_CVTEM_CONTENTS2 0xda8 375 #define PKT4_EMP_CVTEM_CONTENTS3 0xdac 376 #define PKT4_EMP_CVTEM_CONTENTS4 0xdb0 377 #define PKT4_EMP_CVTEM_CONTENTS5 0xdb4 378 #define PKT4_EMP_CVTEM_CONTENTS6 0xdb8 379 #define PKT4_EMP_CVTEM_CONTENTS7 0xdbc 380 #define PKT5_EMP_CVTEM_CONTENTS0 0xdc0 381 #define PKT5_EMP_CVTEM_CONTENTS1 0xdc4 382 #define PKT5_EMP_CVTEM_CONTENTS2 0xdc8 383 #define PKT5_EMP_CVTEM_CONTENTS3 0xdcc 384 #define PKT5_EMP_CVTEM_CONTENTS4 0xdd0 385 #define PKT5_EMP_CVTEM_CONTENTS5 0xdd4 386 #define PKT5_EMP_CVTEM_CONTENTS6 0xdd8 387 #define PKT5_EMP_CVTEM_CONTENTS7 0xddc 388 /* Audio Packetizer Registers */ 389 #define AUDPKT_CONTROL0 0xe20 390 #define AUDPKT_CHSTATUS_OVR_EN_MASK BIT(0) 391 #define AUDPKT_CHSTATUS_OVR_EN BIT(0) 392 #define AUDPKT_CONTROL1 0xe24 393 #define AUDPKT_ACR_CONTROL0 0xe40 394 #define AUDPKT_ACR_N_VALUE 0xfffff 395 #define AUDPKT_ACR_CONTROL1 0xe44 396 #define AUDPKT_ACR_CTS_OVR_VAL_MSK GENMASK(23, 4) 397 #define AUDPKT_ACR_CTS_OVR_VAL(x) ((x) << 4) 398 #define AUDPKT_ACR_CTS_OVR_EN_MSK BIT(1) 399 #define AUDPKT_ACR_CTS_OVR_EN BIT(1) 400 #define AUDPKT_ACR_STATUS0 0xe4c 401 #define AUDPKT_CHSTATUS_OVR0 0xe60 402 #define AUDPKT_CHSTATUS_OVR1 0xe64 403 /* IEC60958 Byte 3: Sampleing frenuency Bits 24 to 27 */ 404 #define AUDPKT_CHSTATUS_SR_MASK GENMASK(3, 0) 405 #define AUDPKT_CHSTATUS_SR_22050 0x4 406 #define AUDPKT_CHSTATUS_SR_24000 0x6 407 #define AUDPKT_CHSTATUS_SR_32000 0x3 408 #define AUDPKT_CHSTATUS_SR_44100 0x0 409 #define AUDPKT_CHSTATUS_SR_48000 0x2 410 #define AUDPKT_CHSTATUS_SR_88200 0x8 411 #define AUDPKT_CHSTATUS_SR_96000 0xa 412 #define AUDPKT_CHSTATUS_SR_176400 0xc 413 #define AUDPKT_CHSTATUS_SR_192000 0xe 414 #define AUDPKT_CHSTATUS_SR_768000 0x9 415 #define AUDPKT_CHSTATUS_SR_NOT_INDICATED 0x1 416 /* IEC60958 Byte 4: Original Sampleing frenuency Bits 36 to 39 */ 417 #define AUDPKT_CHSTATUS_0SR_MASK GENMASK(15, 12) 418 #define AUDPKT_CHSTATUS_OSR_8000 0x6 419 #define AUDPKT_CHSTATUS_OSR_11025 0xa 420 #define AUDPKT_CHSTATUS_OSR_12000 0x2 421 #define AUDPKT_CHSTATUS_OSR_16000 0x8 422 #define AUDPKT_CHSTATUS_OSR_22050 0xb 423 #define AUDPKT_CHSTATUS_OSR_24000 0x9 424 #define AUDPKT_CHSTATUS_OSR_32000 0xc 425 #define AUDPKT_CHSTATUS_OSR_44100 0xf 426 #define AUDPKT_CHSTATUS_OSR_48000 0xd 427 #define AUDPKT_CHSTATUS_OSR_88200 0x7 428 #define AUDPKT_CHSTATUS_OSR_96000 0x5 429 #define AUDPKT_CHSTATUS_OSR_176400 0x3 430 #define AUDPKT_CHSTATUS_OSR_192000 0x1 431 #define AUDPKT_CHSTATUS_OSR_NOT_INDICATED 0x0 432 #define AUDPKT_CHSTATUS_OVR2 0xe68 433 #define AUDPKT_CHSTATUS_OVR3 0xe6c 434 #define AUDPKT_CHSTATUS_OVR4 0xe70 435 #define AUDPKT_CHSTATUS_OVR5 0xe74 436 #define AUDPKT_CHSTATUS_OVR6 0xe78 437 #define AUDPKT_CHSTATUS_OVR7 0xe7c 438 #define AUDPKT_CHSTATUS_OVR8 0xe80 439 #define AUDPKT_CHSTATUS_OVR9 0xe84 440 #define AUDPKT_CHSTATUS_OVR10 0xe88 441 #define AUDPKT_CHSTATUS_OVR11 0xe8c 442 #define AUDPKT_CHSTATUS_OVR12 0xe90 443 #define AUDPKT_CHSTATUS_OVR13 0xe94 444 #define AUDPKT_CHSTATUS_OVR14 0xe98 445 #define AUDPKT_USRDATA_OVR_MSG_GENERIC0 0xea0 446 #define AUDPKT_USRDATA_OVR_MSG_GENERIC1 0xea4 447 #define AUDPKT_USRDATA_OVR_MSG_GENERIC2 0xea8 448 #define AUDPKT_USRDATA_OVR_MSG_GENERIC3 0xeac 449 #define AUDPKT_USRDATA_OVR_MSG_GENERIC4 0xeb0 450 #define AUDPKT_USRDATA_OVR_MSG_GENERIC5 0xeb4 451 #define AUDPKT_USRDATA_OVR_MSG_GENERIC6 0xeb8 452 #define AUDPKT_USRDATA_OVR_MSG_GENERIC7 0xebc 453 #define AUDPKT_USRDATA_OVR_MSG_GENERIC8 0xec0 454 #define AUDPKT_USRDATA_OVR_MSG_GENERIC9 0xec4 455 #define AUDPKT_USRDATA_OVR_MSG_GENERIC10 0xec8 456 #define AUDPKT_USRDATA_OVR_MSG_GENERIC11 0xecc 457 #define AUDPKT_USRDATA_OVR_MSG_GENERIC12 0xed0 458 #define AUDPKT_USRDATA_OVR_MSG_GENERIC13 0xed4 459 #define AUDPKT_USRDATA_OVR_MSG_GENERIC14 0xed8 460 #define AUDPKT_USRDATA_OVR_MSG_GENERIC15 0xedc 461 #define AUDPKT_USRDATA_OVR_MSG_GENERIC16 0xee0 462 #define AUDPKT_USRDATA_OVR_MSG_GENERIC17 0xee4 463 #define AUDPKT_USRDATA_OVR_MSG_GENERIC18 0xee8 464 #define AUDPKT_USRDATA_OVR_MSG_GENERIC19 0xeec 465 #define AUDPKT_USRDATA_OVR_MSG_GENERIC20 0xef0 466 #define AUDPKT_USRDATA_OVR_MSG_GENERIC21 0xef4 467 #define AUDPKT_USRDATA_OVR_MSG_GENERIC22 0xef8 468 #define AUDPKT_USRDATA_OVR_MSG_GENERIC23 0xefc 469 #define AUDPKT_USRDATA_OVR_MSG_GENERIC24 0xf00 470 #define AUDPKT_USRDATA_OVR_MSG_GENERIC25 0xf04 471 #define AUDPKT_USRDATA_OVR_MSG_GENERIC26 0xf08 472 #define AUDPKT_USRDATA_OVR_MSG_GENERIC27 0xf0c 473 #define AUDPKT_USRDATA_OVR_MSG_GENERIC28 0xf10 474 #define AUDPKT_USRDATA_OVR_MSG_GENERIC29 0xf14 475 #define AUDPKT_USRDATA_OVR_MSG_GENERIC30 0xf18 476 #define AUDPKT_USRDATA_OVR_MSG_GENERIC31 0xf1c 477 #define AUDPKT_USRDATA_OVR_MSG_GENERIC32 0xf20 478 #define AUDPKT_VBIT_OVR0 0xf24 479 /* CEC Registers */ 480 #define CEC_TX_CONTROL 0x1000 481 #define CEC_STATUS 0x1004 482 #define CEC_CONFIG 0x1008 483 #define CEC_ADDR 0x100c 484 #define CEC_TX_COUNT 0x1020 485 #define CEC_TX_DATA3_0 0x1024 486 #define CEC_TX_DATA7_4 0x1028 487 #define CEC_TX_DATA11_8 0x102c 488 #define CEC_TX_DATA15_12 0x1030 489 #define CEC_RX_COUNT_STATUS 0x1040 490 #define CEC_RX_DATA3_0 0x1044 491 #define CEC_RX_DATA7_4 0x1048 492 #define CEC_RX_DATA11_8 0x104c 493 #define CEC_RX_DATA15_12 0x1050 494 #define CEC_LOCK_CONTROL 0x1054 495 #define CEC_RXQUAL_BITTIME_CONFIG 0x1060 496 #define CEC_RX_BITTIME_CONFIG 0x1064 497 #define CEC_TX_BITTIME_CONFIG 0x1068 498 /* eARC RX CMDC Registers */ 499 #define EARCRX_CMDC_CONFIG0 0x1800 500 #define EARCRX_XACTREAD_STOP_CFG BIT(26) 501 #define EARCRX_XACTREAD_RETRY_CFG BIT(25) 502 #define EARCRX_CMDC_DSCVR_EARCVALID0_TO_DISC1 BIT(24) 503 #define EARCRX_CMDC_XACT_RESTART_EN BIT(18) 504 #define EARCRX_CMDC_CONFIG1 0x1804 505 #define EARCRX_CMDC_CONTROL 0x1808 506 #define EARCRX_CMDC_HEARTBEAT_LOSS_EN BIT(4) 507 #define EARCRX_CMDC_DISCOVERY_EN BIT(3) 508 #define EARCRX_CONNECTOR_HPD BIT(1) 509 #define EARCRX_CMDC_WHITELIST0_CONFIG 0x180c 510 #define EARCRX_CMDC_WHITELIST1_CONFIG 0x1810 511 #define EARCRX_CMDC_WHITELIST2_CONFIG 0x1814 512 #define EARCRX_CMDC_WHITELIST3_CONFIG 0x1818 513 #define EARCRX_CMDC_STATUS 0x181c 514 #define EARCRX_CMDC_XACT_INFO 0x1820 515 #define EARCRX_CMDC_XACT_ACTION 0x1824 516 #define EARCRX_CMDC_HEARTBEAT_RXSTAT_SE 0x1828 517 #define EARCRX_CMDC_HEARTBEAT_STATUS 0x182c 518 #define EARCRX_CMDC_XACT_WR0 0x1840 519 #define EARCRX_CMDC_XACT_WR1 0x1844 520 #define EARCRX_CMDC_XACT_WR2 0x1848 521 #define EARCRX_CMDC_XACT_WR3 0x184c 522 #define EARCRX_CMDC_XACT_WR4 0x1850 523 #define EARCRX_CMDC_XACT_WR5 0x1854 524 #define EARCRX_CMDC_XACT_WR6 0x1858 525 #define EARCRX_CMDC_XACT_WR7 0x185c 526 #define EARCRX_CMDC_XACT_WR8 0x1860 527 #define EARCRX_CMDC_XACT_WR9 0x1864 528 #define EARCRX_CMDC_XACT_WR10 0x1868 529 #define EARCRX_CMDC_XACT_WR11 0x186c 530 #define EARCRX_CMDC_XACT_WR12 0x1870 531 #define EARCRX_CMDC_XACT_WR13 0x1874 532 #define EARCRX_CMDC_XACT_WR14 0x1878 533 #define EARCRX_CMDC_XACT_WR15 0x187c 534 #define EARCRX_CMDC_XACT_WR16 0x1880 535 #define EARCRX_CMDC_XACT_WR17 0x1884 536 #define EARCRX_CMDC_XACT_WR18 0x1888 537 #define EARCRX_CMDC_XACT_WR19 0x188c 538 #define EARCRX_CMDC_XACT_WR20 0x1890 539 #define EARCRX_CMDC_XACT_WR21 0x1894 540 #define EARCRX_CMDC_XACT_WR22 0x1898 541 #define EARCRX_CMDC_XACT_WR23 0x189c 542 #define EARCRX_CMDC_XACT_WR24 0x18a0 543 #define EARCRX_CMDC_XACT_WR25 0x18a4 544 #define EARCRX_CMDC_XACT_WR26 0x18a8 545 #define EARCRX_CMDC_XACT_WR27 0x18ac 546 #define EARCRX_CMDC_XACT_WR28 0x18b0 547 #define EARCRX_CMDC_XACT_WR29 0x18b4 548 #define EARCRX_CMDC_XACT_WR30 0x18b8 549 #define EARCRX_CMDC_XACT_WR31 0x18bc 550 #define EARCRX_CMDC_XACT_WR32 0x18c0 551 #define EARCRX_CMDC_XACT_WR33 0x18c4 552 #define EARCRX_CMDC_XACT_WR34 0x18c8 553 #define EARCRX_CMDC_XACT_WR35 0x18cc 554 #define EARCRX_CMDC_XACT_WR36 0x18d0 555 #define EARCRX_CMDC_XACT_WR37 0x18d4 556 #define EARCRX_CMDC_XACT_WR38 0x18d8 557 #define EARCRX_CMDC_XACT_WR39 0x18dc 558 #define EARCRX_CMDC_XACT_WR40 0x18e0 559 #define EARCRX_CMDC_XACT_WR41 0x18e4 560 #define EARCRX_CMDC_XACT_WR42 0x18e8 561 #define EARCRX_CMDC_XACT_WR43 0x18ec 562 #define EARCRX_CMDC_XACT_WR44 0x18f0 563 #define EARCRX_CMDC_XACT_WR45 0x18f4 564 #define EARCRX_CMDC_XACT_WR46 0x18f8 565 #define EARCRX_CMDC_XACT_WR47 0x18fc 566 #define EARCRX_CMDC_XACT_WR48 0x1900 567 #define EARCRX_CMDC_XACT_WR49 0x1904 568 #define EARCRX_CMDC_XACT_WR50 0x1908 569 #define EARCRX_CMDC_XACT_WR51 0x190c 570 #define EARCRX_CMDC_XACT_WR52 0x1910 571 #define EARCRX_CMDC_XACT_WR53 0x1914 572 #define EARCRX_CMDC_XACT_WR54 0x1918 573 #define EARCRX_CMDC_XACT_WR55 0x191c 574 #define EARCRX_CMDC_XACT_WR56 0x1920 575 #define EARCRX_CMDC_XACT_WR57 0x1924 576 #define EARCRX_CMDC_XACT_WR58 0x1928 577 #define EARCRX_CMDC_XACT_WR59 0x192c 578 #define EARCRX_CMDC_XACT_WR60 0x1930 579 #define EARCRX_CMDC_XACT_WR61 0x1934 580 #define EARCRX_CMDC_XACT_WR62 0x1938 581 #define EARCRX_CMDC_XACT_WR63 0x193c 582 #define EARCRX_CMDC_XACT_WR64 0x1940 583 #define EARCRX_CMDC_XACT_RD0 0x1960 584 #define EARCRX_CMDC_XACT_RD1 0x1964 585 #define EARCRX_CMDC_XACT_RD2 0x1968 586 #define EARCRX_CMDC_XACT_RD3 0x196c 587 #define EARCRX_CMDC_XACT_RD4 0x1970 588 #define EARCRX_CMDC_XACT_RD5 0x1974 589 #define EARCRX_CMDC_XACT_RD6 0x1978 590 #define EARCRX_CMDC_XACT_RD7 0x197c 591 #define EARCRX_CMDC_XACT_RD8 0x1980 592 #define EARCRX_CMDC_XACT_RD9 0x1984 593 #define EARCRX_CMDC_XACT_RD10 0x1988 594 #define EARCRX_CMDC_XACT_RD11 0x198c 595 #define EARCRX_CMDC_XACT_RD12 0x1990 596 #define EARCRX_CMDC_XACT_RD13 0x1994 597 #define EARCRX_CMDC_XACT_RD14 0x1998 598 #define EARCRX_CMDC_XACT_RD15 0x199c 599 #define EARCRX_CMDC_XACT_RD16 0x19a0 600 #define EARCRX_CMDC_XACT_RD17 0x19a4 601 #define EARCRX_CMDC_XACT_RD18 0x19a8 602 #define EARCRX_CMDC_XACT_RD19 0x19ac 603 #define EARCRX_CMDC_XACT_RD20 0x19b0 604 #define EARCRX_CMDC_XACT_RD21 0x19b4 605 #define EARCRX_CMDC_XACT_RD22 0x19b8 606 #define EARCRX_CMDC_XACT_RD23 0x19bc 607 #define EARCRX_CMDC_XACT_RD24 0x19c0 608 #define EARCRX_CMDC_XACT_RD25 0x19c4 609 #define EARCRX_CMDC_XACT_RD26 0x19c8 610 #define EARCRX_CMDC_XACT_RD27 0x19cc 611 #define EARCRX_CMDC_XACT_RD28 0x19d0 612 #define EARCRX_CMDC_XACT_RD29 0x19d4 613 #define EARCRX_CMDC_XACT_RD30 0x19d8 614 #define EARCRX_CMDC_XACT_RD31 0x19dc 615 #define EARCRX_CMDC_XACT_RD32 0x19e0 616 #define EARCRX_CMDC_XACT_RD33 0x19e4 617 #define EARCRX_CMDC_XACT_RD34 0x19e8 618 #define EARCRX_CMDC_XACT_RD35 0x19ec 619 #define EARCRX_CMDC_XACT_RD36 0x19f0 620 #define EARCRX_CMDC_XACT_RD37 0x19f4 621 #define EARCRX_CMDC_XACT_RD38 0x19f8 622 #define EARCRX_CMDC_XACT_RD39 0x19fc 623 #define EARCRX_CMDC_XACT_RD40 0x1a00 624 #define EARCRX_CMDC_XACT_RD41 0x1a04 625 #define EARCRX_CMDC_XACT_RD42 0x1a08 626 #define EARCRX_CMDC_XACT_RD43 0x1a0c 627 #define EARCRX_CMDC_XACT_RD44 0x1a10 628 #define EARCRX_CMDC_XACT_RD45 0x1a14 629 #define EARCRX_CMDC_XACT_RD46 0x1a18 630 #define EARCRX_CMDC_XACT_RD47 0x1a1c 631 #define EARCRX_CMDC_XACT_RD48 0x1a20 632 #define EARCRX_CMDC_XACT_RD49 0x1a24 633 #define EARCRX_CMDC_XACT_RD50 0x1a28 634 #define EARCRX_CMDC_XACT_RD51 0x1a2c 635 #define EARCRX_CMDC_XACT_RD52 0x1a30 636 #define EARCRX_CMDC_XACT_RD53 0x1a34 637 #define EARCRX_CMDC_XACT_RD54 0x1a38 638 #define EARCRX_CMDC_XACT_RD55 0x1a3c 639 #define EARCRX_CMDC_XACT_RD56 0x1a40 640 #define EARCRX_CMDC_XACT_RD57 0x1a44 641 #define EARCRX_CMDC_XACT_RD58 0x1a48 642 #define EARCRX_CMDC_XACT_RD59 0x1a4c 643 #define EARCRX_CMDC_XACT_RD60 0x1a50 644 #define EARCRX_CMDC_XACT_RD61 0x1a54 645 #define EARCRX_CMDC_XACT_RD62 0x1a58 646 #define EARCRX_CMDC_XACT_RD63 0x1a5c 647 #define EARCRX_CMDC_XACT_RD64 0x1a60 648 #define EARCRX_CMDC_SYNC_CONFIG 0x1b00 649 /* eARC RX DMAC Registers */ 650 #define EARCRX_DMAC_PHY_CONTROL 0x1c00 651 #define EARCRX_DMAC_CONFIG 0x1c08 652 #define EARCRX_DMAC_CONTROL0 0x1c0c 653 #define EARCRX_DMAC_AUDIO_EN BIT(1) 654 #define EARCRX_DMAC_EN BIT(0) 655 #define EARCRX_DMAC_CONTROL1 0x1c10 656 #define EARCRX_DMAC_STATUS 0x1c14 657 #define EARCRX_DMAC_CHSTATUS0 0x1c18 658 #define EARCRX_DMAC_CHSTATUS1 0x1c1c 659 #define EARCRX_DMAC_CHSTATUS2 0x1c20 660 #define EARCRX_DMAC_CHSTATUS3 0x1c24 661 #define EARCRX_DMAC_CHSTATUS4 0x1c28 662 #define EARCRX_DMAC_CHSTATUS5 0x1c2c 663 #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC0 0x1c30 664 #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC1 0x1c34 665 #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC2 0x1c38 666 #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC3 0x1c3c 667 #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC4 0x1c40 668 #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC5 0x1c44 669 #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC6 0x1c48 670 #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC7 0x1c4c 671 #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC8 0x1c50 672 #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC9 0x1c54 673 #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC10 0x1c58 674 #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC11 0x1c5c 675 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT0 0x1c60 676 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT1 0x1c64 677 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT2 0x1c68 678 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT3 0x1c6c 679 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT4 0x1c70 680 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT5 0x1c74 681 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT6 0x1c78 682 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT7 0x1c7c 683 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT8 0x1c80 684 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT9 0x1c84 685 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT10 0x1c88 686 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT11 0x1c8c 687 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT0 0x1c90 688 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT1 0x1c94 689 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT2 0x1c98 690 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT3 0x1c9c 691 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT4 0x1ca0 692 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT5 0x1ca4 693 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT6 0x1ca8 694 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT7 0x1cac 695 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT8 0x1cb0 696 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT9 0x1cb4 697 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT10 0x1cb8 698 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT11 0x1cbc 699 #define EARCRX_DMAC_USRDATA_MSG_GENERIC0 0x1cc0 700 #define EARCRX_DMAC_USRDATA_MSG_GENERIC1 0x1cc4 701 #define EARCRX_DMAC_USRDATA_MSG_GENERIC2 0x1cc8 702 #define EARCRX_DMAC_USRDATA_MSG_GENERIC3 0x1ccc 703 #define EARCRX_DMAC_USRDATA_MSG_GENERIC4 0x1cd0 704 #define EARCRX_DMAC_USRDATA_MSG_GENERIC5 0x1cd4 705 #define EARCRX_DMAC_USRDATA_MSG_GENERIC6 0x1cd8 706 #define EARCRX_DMAC_USRDATA_MSG_GENERIC7 0x1cdc 707 #define EARCRX_DMAC_USRDATA_MSG_GENERIC8 0x1ce0 708 #define EARCRX_DMAC_USRDATA_MSG_GENERIC9 0x1ce4 709 #define EARCRX_DMAC_USRDATA_MSG_GENERIC10 0x1ce8 710 #define EARCRX_DMAC_USRDATA_MSG_GENERIC11 0x1cec 711 #define EARCRX_DMAC_USRDATA_MSG_GENERIC12 0x1cf0 712 #define EARCRX_DMAC_USRDATA_MSG_GENERIC13 0x1cf4 713 #define EARCRX_DMAC_USRDATA_MSG_GENERIC14 0x1cf8 714 #define EARCRX_DMAC_USRDATA_MSG_GENERIC15 0x1cfc 715 #define EARCRX_DMAC_USRDATA_MSG_GENERIC16 0x1d00 716 #define EARCRX_DMAC_USRDATA_MSG_GENERIC17 0x1d04 717 #define EARCRX_DMAC_USRDATA_MSG_GENERIC18 0x1d08 718 #define EARCRX_DMAC_USRDATA_MSG_GENERIC19 0x1d0c 719 #define EARCRX_DMAC_USRDATA_MSG_GENERIC20 0x1d10 720 #define EARCRX_DMAC_USRDATA_MSG_GENERIC21 0x1d14 721 #define EARCRX_DMAC_USRDATA_MSG_GENERIC22 0x1d18 722 #define EARCRX_DMAC_USRDATA_MSG_GENERIC23 0x1d1c 723 #define EARCRX_DMAC_USRDATA_MSG_GENERIC24 0x1d20 724 #define EARCRX_DMAC_USRDATA_MSG_GENERIC25 0x1d24 725 #define EARCRX_DMAC_USRDATA_MSG_GENERIC26 0x1d28 726 #define EARCRX_DMAC_USRDATA_MSG_GENERIC27 0x1d2c 727 #define EARCRX_DMAC_USRDATA_MSG_GENERIC28 0x1d30 728 #define EARCRX_DMAC_USRDATA_MSG_GENERIC29 0x1d34 729 #define EARCRX_DMAC_USRDATA_MSG_GENERIC30 0x1d38 730 #define EARCRX_DMAC_USRDATA_MSG_GENERIC31 0x1d3c 731 #define EARCRX_DMAC_USRDATA_MSG_GENERIC32 0x1d40 732 #define EARCRX_DMAC_CHSTATUS_STREAMER0 0x1d44 733 #define EARCRX_DMAC_CHSTATUS_STREAMER1 0x1d48 734 #define EARCRX_DMAC_CHSTATUS_STREAMER2 0x1d4c 735 #define EARCRX_DMAC_CHSTATUS_STREAMER3 0x1d50 736 #define EARCRX_DMAC_CHSTATUS_STREAMER4 0x1d54 737 #define EARCRX_DMAC_CHSTATUS_STREAMER5 0x1d58 738 #define EARCRX_DMAC_CHSTATUS_STREAMER6 0x1d5c 739 #define EARCRX_DMAC_CHSTATUS_STREAMER7 0x1d60 740 #define EARCRX_DMAC_CHSTATUS_STREAMER8 0x1d64 741 #define EARCRX_DMAC_CHSTATUS_STREAMER9 0x1d68 742 #define EARCRX_DMAC_CHSTATUS_STREAMER10 0x1d6c 743 #define EARCRX_DMAC_CHSTATUS_STREAMER11 0x1d70 744 #define EARCRX_DMAC_CHSTATUS_STREAMER12 0x1d74 745 #define EARCRX_DMAC_CHSTATUS_STREAMER13 0x1d78 746 #define EARCRX_DMAC_CHSTATUS_STREAMER14 0x1d7c 747 #define EARCRX_DMAC_USRDATA_STREAMER0 0x1d80 748 /* Main Unit Interrupt Registers */ 749 #define MAIN_INTVEC_INDEX 0x3000 750 #define MAINUNIT_0_INT_STATUS 0x3010 751 #define MAINUNIT_0_INT_MASK_N 0x3014 752 #define MAINUNIT_0_INT_CLEAR 0x3018 753 #define MAINUNIT_0_INT_FORCE 0x301c 754 #define MAINUNIT_1_INT_STATUS 0x3020 755 #define FLT_EXIT_TO_LTSL_IRQ BIT(22) 756 #define FLT_EXIT_TO_LTS4_IRQ BIT(21) 757 #define FLT_EXIT_TO_LTSP_IRQ BIT(20) 758 #define SCDC_NACK_RCVD_IRQ BIT(12) 759 #define SCDC_RR_REPLY_STOP_IRQ BIT(11) 760 #define SCDC_UPD_FLAGS_CLR_IRQ BIT(10) 761 #define SCDC_UPD_FLAGS_CHG_IRQ BIT(9) 762 #define SCDC_UPD_FLAGS_RD_IRQ BIT(8) 763 #define I2CM_NACK_RCVD_IRQ BIT(2) 764 #define I2CM_READ_REQUEST_IRQ BIT(1) 765 #define I2CM_OP_DONE_IRQ BIT(0) 766 #define MAINUNIT_1_INT_MASK_N 0x3024 767 #define I2CM_NACK_RCVD_MASK_N BIT(2) 768 #define I2CM_READ_REQUEST_MASK_N BIT(1) 769 #define I2CM_OP_DONE_MASK_N BIT(0) 770 #define MAINUNIT_1_INT_CLEAR 0x3028 771 #define I2CM_NACK_RCVD_CLEAR BIT(2) 772 #define I2CM_READ_REQUEST_CLEAR BIT(1) 773 #define I2CM_OP_DONE_CLEAR BIT(0) 774 #define MAINUNIT_1_INT_FORCE 0x302c 775 /* AVPUNIT Interrupt Registers */ 776 #define AVP_INTVEC_INDEX 0x3800 777 #define AVP_0_INT_STATUS 0x3810 778 #define AVP_0_INT_MASK_N 0x3814 779 #define AVP_0_INT_CLEAR 0x3818 780 #define AVP_0_INT_FORCE 0x381c 781 #define AVP_1_INT_STATUS 0x3820 782 #define AVP_1_INT_MASK_N 0x3824 783 #define HDCP14_AUTH_CHG_MASK_N BIT(6) 784 #define AVP_1_INT_CLEAR 0x3828 785 #define AVP_1_INT_FORCE 0x382c 786 #define AVP_2_INT_STATUS 0x3830 787 #define AVP_2_INT_MASK_N 0x3834 788 #define AVP_2_INT_CLEAR 0x3838 789 #define AVP_2_INT_FORCE 0x383c 790 #define AVP_3_INT_STATUS 0x3840 791 #define AVP_3_INT_MASK_N 0x3844 792 #define AVP_3_INT_CLEAR 0x3848 793 #define AVP_3_INT_FORCE 0x384c 794 #define AVP_4_INT_STATUS 0x3850 795 #define AVP_4_INT_MASK_N 0x3854 796 #define AVP_4_INT_CLEAR 0x3858 797 #define AVP_4_INT_FORCE 0x385c 798 #define AVP_5_INT_STATUS 0x3860 799 #define AVP_5_INT_MASK_N 0x3864 800 #define AVP_5_INT_CLEAR 0x3868 801 #define AVP_5_INT_FORCE 0x386c 802 #define AVP_6_INT_STATUS 0x3870 803 #define AVP_6_INT_MASK_N 0x3874 804 #define AVP_6_INT_CLEAR 0x3878 805 #define AVP_6_INT_FORCE 0x387c 806 /* CEC Interrupt Registers */ 807 #define CEC_INT_STATUS 0x4000 808 #define CEC_INT_MASK_N 0x4004 809 #define CEC_INT_CLEAR 0x4008 810 #define CEC_INT_FORCE 0x400c 811 /* eARC RX Interrupt Registers */ 812 #define EARCRX_INTVEC_INDEX 0x4800 813 #define EARCRX_0_INT_STATUS 0x4810 814 #define EARCRX_CMDC_DISCOVERY_TIMEOUT_IRQ BIT(9) 815 #define EARCRX_CMDC_DISCOVERY_DONE_IRQ BIT(8) 816 #define EARCRX_0_INT_MASK_N 0x4814 817 #define EARCRX_0_INT_CLEAR 0x4818 818 #define EARCRX_0_INT_FORCE 0x481c 819 #define EARCRX_1_INT_STATUS 0x4820 820 #define EARCRX_1_INT_MASK_N 0x4824 821 #define EARCRX_1_INT_CLEAR 0x4828 822 #define EARCRX_1_INT_FORCE 0x482c 823 824 #endif /* __DW_HDMI_QP_H__ */ 825