1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __ROCKCHIP_PSCI_H
3 #define __ROCKCHIP_PSCI_H
4
5 #define SEC_REG_RD (0x0)
6 #define SEC_REG_WR (0x1)
7
8 /*
9 * trust firmware verison
10 */
11 #define RKTF_VER_MAJOR(ver) (((ver) >> 16) & 0xffff)
12 #define RKTF_VER_MINOR(ver) ((ver) & 0xffff)
13
14 /*
15 * pcsi smc funciton id
16 */
17 #define PSCI_SIP_RKTF_VER (0x82000001)
18 #define PSCI_SIP_ACCESS_REG (0x82000002)
19 #define PSCI_SIP_ACCESS_REG64 (0xc2000002)
20 #define PSCI_SIP_SUSPEND_WR_CTRBITS (0x82000003)
21 #define PSCI_SIP_PENDING_CPUS (0x82000004)
22 #define PSCI_SIP_UARTDBG_CFG (0x82000005)
23 #define PSCI_SIP_UARTDBG_CFG64 (0xc2000005)
24 #define PSCI_SIP_EL3FIQ_CFG (0x82000006)
25 #define PSCI_SIP_SMEM_CONFIG (0x82000007)
26
27 /*
28 * pcsi smc funciton err code
29 */
30 #define PSCI_SMC_FUNC_UNK 0xffffffff
31
32 /*
33 * define PSCI_SIP_UARTDBG_CFG call type
34 */
35 #define UARTDBG_CFG_INIT 0xf0
36 #define UARTDBG_CFG_OSHDL_TO_OS 0xf1
37 #define UARTDBG_CFG_OSHDL_CPUSW 0xf3
38 #define UARTDBG_CFG_OSHDL_DEBUG_ENABLE 0xf4
39 #define UARTDBG_CFG_OSHDL_DEBUG_DISABLE 0xf5
40
41 /*
42 * rockchip psci function call interface
43 */
44
45 u32 rockchip_psci_smc_read(u32 function_id, u32 arg0, u32 arg1, u32 arg2,
46 u32 *val);
47 u32 rockchip_psci_smc_write(u32 function_id, u32 arg0, u32 arg1, u32 arg2);
48
49 u32 rockchip_psci_smc_get_tf_ver(void);
50 u32 rockchip_secure_reg_read(u32 addr_phy);
51 u32 rockchip_secure_reg_write(u32 addr_phy, u32 val);
52
53 #ifdef CONFIG_ARM64
54 u32 rockchip_psci_smc_write64(u64 function_id, u64 arg0, u64 arg1, u64 arg2);
55 u32 rockchip_psci_smc_read64(u64 function_id, u64 arg0, u64 arg1, u64 arg2,
56 u64 *val);
57 u64 rockchip_secure_reg_read64(u64 addr_phy);
58 u32 rockchip_secure_reg_write64(u64 addr_phy, u64 val);
59
60 void psci_fiq_debugger_uart_irq_tf_cb(u64 sp_el1, u64 offset);
61 #endif
62
63 u32 psci_fiq_debugger_switch_cpu(u32 cpu);
64 void psci_fiq_debugger_uart_irq_tf_init(u32 irq_id, void *callback);
65 void psci_fiq_debugger_enable_debug(bool val);
66
67 #if defined(CONFIG_ARM_PSCI) || defined(CONFIG_ARM64)
68 u32 psci_set_memory_secure(bool val);
69 #else
psci_set_memory_secure(bool val)70 static inline u32 psci_set_memory_secure(bool val)
71 {
72 return 0;
73 }
74 #endif
75
76 #endif /* __ROCKCHIP_PSCI_H */
77