1 /* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR MIT) */ 2 /* 3 * Rockchip module information 4 * Copyright (C) 2018-2019 Rockchip Electronics Co., Ltd. 5 */ 6 7 #ifndef _UAPI_RKMODULE_CAMERA_H 8 #define _UAPI_RKMODULE_CAMERA_H 9 10 #include <linux/types.h> 11 #include <linux/rk-video-format.h> 12 13 #define RKMODULE_API_VERSION KERNEL_VERSION(0, 1, 0x2) 14 15 /* using for rk3588 dual isp unite */ 16 #define RKMOUDLE_UNITE_EXTEND_PIXEL 128 17 /* using for rv1109 and rv1126 */ 18 #define RKMODULE_EXTEND_LINE 24 19 20 #define RKMODULE_NAME_LEN 32 21 #define RKMODULE_LSCDATA_LEN 289 22 23 #define RKMODULE_MAX_VC_CH 4 24 25 #define RKMODULE_PADF_GAINMAP_LEN 1024 26 #define RKMODULE_PDAF_DCCMAP_LEN 256 27 #define RKMODULE_AF_OTP_MAX_LEN 3 28 29 #define RKMODULE_CAMERA_MODULE_INDEX "rockchip,camera-module-index" 30 #define RKMODULE_CAMERA_MODULE_FACING "rockchip,camera-module-facing" 31 #define RKMODULE_CAMERA_MODULE_NAME "rockchip,camera-module-name" 32 #define RKMODULE_CAMERA_LENS_NAME "rockchip,camera-module-lens-name" 33 34 #define RKMODULE_CAMERA_SYNC_MODE "rockchip,camera-module-sync-mode" 35 #define RKMODULE_INTERNAL_MASTER_MODE "internal_master" 36 #define RKMODULE_EXTERNAL_MASTER_MODE "external_master" 37 #define RKMODULE_SLAVE_MODE "slave" 38 39 /* BT.656 & BT.1120 multi channel 40 * On which channels it can send video data 41 * related with struct rkmodule_bt656_mbus_info 42 */ 43 #define RKMODULE_CAMERA_BT656_ID_EN_BITS_1 (0x1) 44 #define RKMODULE_CAMERA_BT656_ID_EN_BITS_2 (0x3) 45 #define RKMODULE_CAMERA_BT656_ID_EN_BITS_3 (0x7) 46 #define RKMODULE_CAMERA_BT656_ID_EN_BITS_4 (0xf) 47 #define RKMODULE_CAMERA_BT656_PARSE_ID_LSB BIT(0) 48 #define RKMODULE_CAMERA_BT656_PARSE_ID_MSB BIT(1) 49 #define RKMODULE_CAMERA_BT656_CHANNEL_0 BIT(2) 50 #define RKMODULE_CAMERA_BT656_CHANNEL_1 BIT(3) 51 #define RKMODULE_CAMERA_BT656_CHANNEL_2 BIT(4) 52 #define RKMODULE_CAMERA_BT656_CHANNEL_3 BIT(5) 53 #define RKMODULE_CAMERA_BT656_CHANNELS (RKMODULE_CAMERA_BT656_CHANNEL_0 | \ 54 RKMODULE_CAMERA_BT656_CHANNEL_1 | \ 55 RKMODULE_CAMERA_BT656_CHANNEL_2 | \ 56 RKMODULE_CAMERA_BT656_CHANNEL_3) 57 58 #define DPHY_MAX_LANE 4 59 60 #define RKMODULE_GET_MODULE_INFO \ 61 _IOR('V', BASE_VIDIOC_PRIVATE + 0, struct rkmodule_inf) 62 63 #define RKMODULE_AWB_CFG \ 64 _IOW('V', BASE_VIDIOC_PRIVATE + 1, struct rkmodule_awb_cfg) 65 66 #define RKMODULE_AF_CFG \ 67 _IOW('V', BASE_VIDIOC_PRIVATE + 2, struct rkmodule_af_cfg) 68 69 #define RKMODULE_LSC_CFG \ 70 _IOW('V', BASE_VIDIOC_PRIVATE + 3, struct rkmodule_lsc_cfg) 71 72 #define RKMODULE_GET_HDR_CFG \ 73 _IOR('V', BASE_VIDIOC_PRIVATE + 4, struct rkmodule_hdr_cfg) 74 75 #define RKMODULE_SET_HDR_CFG \ 76 _IOW('V', BASE_VIDIOC_PRIVATE + 5, struct rkmodule_hdr_cfg) 77 78 #define RKMODULE_SET_CONVERSION_GAIN \ 79 _IOW('V', BASE_VIDIOC_PRIVATE + 6, __u32) 80 81 #define RKMODULE_GET_LVDS_CFG \ 82 _IOR('V', BASE_VIDIOC_PRIVATE + 7, struct rkmodule_lvds_cfg) 83 84 #define RKMODULE_SET_DPCC_CFG \ 85 _IOW('V', BASE_VIDIOC_PRIVATE + 8, struct rkmodule_dpcc_cfg) 86 87 #define RKMODULE_GET_NR_SWITCH_THRESHOLD \ 88 _IOR('V', BASE_VIDIOC_PRIVATE + 9, struct rkmodule_nr_switch_threshold) 89 90 #define RKMODULE_SET_QUICK_STREAM \ 91 _IOW('V', BASE_VIDIOC_PRIVATE + 10, __u32) 92 93 #define RKMODULE_GET_BT656_INTF_TYPE \ 94 _IOR('V', BASE_VIDIOC_PRIVATE + 11, __u32) 95 96 #define RKMODULE_GET_VC_FMT_INFO \ 97 _IOR('V', BASE_VIDIOC_PRIVATE + 12, struct rkmodule_vc_fmt_info) 98 99 #define RKMODULE_GET_VC_HOTPLUG_INFO \ 100 _IOR('V', BASE_VIDIOC_PRIVATE + 13, struct rkmodule_vc_hotplug_info) 101 102 #define RKMODULE_GET_START_STREAM_SEQ \ 103 _IOR('V', BASE_VIDIOC_PRIVATE + 14, __u32) 104 105 #define RKMODULE_GET_VICAP_RST_INFO \ 106 _IOR('V', BASE_VIDIOC_PRIVATE + 15, struct rkmodule_vicap_reset_info) 107 108 #define RKMODULE_SET_VICAP_RST_INFO \ 109 _IOW('V', BASE_VIDIOC_PRIVATE + 16, struct rkmodule_vicap_reset_info) 110 111 #define RKMODULE_GET_BT656_MBUS_INFO \ 112 _IOR('V', BASE_VIDIOC_PRIVATE + 17, struct rkmodule_bt656_mbus_info) 113 114 #define RKMODULE_GET_DCG_RATIO \ 115 _IOR('V', BASE_VIDIOC_PRIVATE + 18, struct rkmodule_dcg_ratio) 116 117 #define RKMODULE_GET_SONY_BRL \ 118 _IOR('V', BASE_VIDIOC_PRIVATE + 19, __u32) 119 120 #define RKMODULE_GET_CHANNEL_INFO \ 121 _IOWR('V', BASE_VIDIOC_PRIVATE + 20, struct rkmodule_channel_info) 122 123 #define RKMODULE_GET_SYNC_MODE \ 124 _IOR('V', BASE_VIDIOC_PRIVATE + 21, __u32) 125 126 #define RKMODULE_SET_SYNC_MODE \ 127 _IOW('V', BASE_VIDIOC_PRIVATE + 22, __u32) 128 129 #define RKMODULE_SET_MCLK \ 130 _IOW('V', BASE_VIDIOC_PRIVATE + 23, struct rkmodule_mclk_data) 131 132 #define RKMODULE_SET_LINK_FREQ \ 133 _IOW('V', BASE_VIDIOC_PRIVATE + 24, __s64) 134 135 #define RKMODULE_SET_BUS_CONFIG \ 136 _IOW('V', BASE_VIDIOC_PRIVATE + 25, struct rkmodule_bus_config) 137 138 #define RKMODULE_GET_BUS_CONFIG \ 139 _IOR('V', BASE_VIDIOC_PRIVATE + 26, struct rkmodule_bus_config) 140 141 #define RKMODULE_SET_REGISTER \ 142 _IOW('V', BASE_VIDIOC_PRIVATE + 27, struct rkmodule_reg) 143 144 #define RKMODULE_SYNC_I2CDEV \ 145 _IOW('V', BASE_VIDIOC_PRIVATE + 28, __u8) 146 147 #define RKMODULE_SYNC_I2CDEV_COMPLETE \ 148 _IOW('V', BASE_VIDIOC_PRIVATE + 29, __u8) 149 150 #define RKMODULE_SET_DEV_INFO \ 151 _IOW('V', BASE_VIDIOC_PRIVATE + 30, struct rkmodule_dev_info) 152 153 #define RKMODULE_SET_CSI_DPHY_PARAM \ 154 _IOW('V', BASE_VIDIOC_PRIVATE + 31, struct rkmodule_csi_dphy_param) 155 156 #define RKMODULE_GET_CSI_DPHY_PARAM \ 157 _IOWR('V', BASE_VIDIOC_PRIVATE + 32, struct rkmodule_csi_dphy_param) 158 159 struct rkmodule_i2cdev_info { 160 u8 slave_addr; 161 } __attribute__ ((packed)); 162 163 struct rkmodule_dev_info { 164 union { 165 struct rkmodule_i2cdev_info i2c_dev; 166 u32 reserved[8]; 167 }; 168 } __attribute__ ((packed)); 169 170 /* csi0/csi1 phy support full/split mode */ 171 enum rkmodule_phy_mode { 172 PHY_FULL_MODE, 173 PHY_SPLIT_01, 174 PHY_SPLIT_23, 175 }; 176 177 struct rkmodule_mipi_lvds_bus { 178 __u32 bus_type; 179 __u32 lanes; 180 __u32 phy_mode; /* data type enum rkmodule_phy_mode */ 181 }; 182 183 struct rkmodule_bus_config { 184 union { 185 struct rkmodule_mipi_lvds_bus bus; 186 __u32 reserved[32]; 187 }; 188 } __attribute__ ((packed)); 189 190 struct rkmodule_reg { 191 __u64 num_regs; 192 __u64 preg_addr; 193 __u64 preg_value; 194 __u64 preg_addr_bytes; 195 __u64 preg_value_bytes; 196 } __attribute__ ((packed)); 197 198 /** 199 * struct rkmodule_base_inf - module base information 200 * 201 */ 202 struct rkmodule_base_inf { 203 char sensor[RKMODULE_NAME_LEN]; 204 char module[RKMODULE_NAME_LEN]; 205 char lens[RKMODULE_NAME_LEN]; 206 } __attribute__ ((packed)); 207 208 /** 209 * struct rkmodule_fac_inf - module factory information 210 * 211 */ 212 struct rkmodule_fac_inf { 213 __u32 flag; 214 215 char module[RKMODULE_NAME_LEN]; 216 char lens[RKMODULE_NAME_LEN]; 217 __u32 year; 218 __u32 month; 219 __u32 day; 220 } __attribute__ ((packed)); 221 222 /** 223 * struct rkmodule_awb_inf - module awb information 224 * 225 */ 226 struct rkmodule_awb_inf { 227 __u32 flag; 228 229 __u32 r_value; 230 __u32 b_value; 231 __u32 gr_value; 232 __u32 gb_value; 233 234 __u32 golden_r_value; 235 __u32 golden_b_value; 236 __u32 golden_gr_value; 237 __u32 golden_gb_value; 238 } __attribute__ ((packed)); 239 240 /** 241 * struct rkmodule_lsc_inf - module lsc information 242 * 243 */ 244 struct rkmodule_lsc_inf { 245 __u32 flag; 246 247 __u16 lsc_w; 248 __u16 lsc_h; 249 __u16 decimal_bits; 250 251 __u16 lsc_r[RKMODULE_LSCDATA_LEN]; 252 __u16 lsc_b[RKMODULE_LSCDATA_LEN]; 253 __u16 lsc_gr[RKMODULE_LSCDATA_LEN]; 254 __u16 lsc_gb[RKMODULE_LSCDATA_LEN]; 255 256 __u16 width; 257 __u16 height; 258 __u16 table_size; 259 } __attribute__ ((packed)); 260 261 /** 262 * enum rkmodule_af_dir - enum of module af otp direction 263 */ 264 enum rkmodele_af_otp_dir { 265 AF_OTP_DIR_HORIZONTAL = 0, 266 AF_OTP_DIR_UP = 1, 267 AF_OTP_DIR_DOWN = 2, 268 }; 269 270 /** 271 * struct rkmodule_af_otp - module af otp in one direction 272 */ 273 struct rkmodule_af_otp { 274 __u32 vcm_start; 275 __u32 vcm_end; 276 __u32 vcm_dir; 277 }; 278 279 /** 280 * struct rkmodule_af_inf - module af information 281 * 282 */ 283 struct rkmodule_af_inf { 284 __u32 flag; 285 __u32 dir_cnt; 286 struct rkmodule_af_otp af_otp[RKMODULE_AF_OTP_MAX_LEN]; 287 } __attribute__ ((packed)); 288 289 /** 290 * struct rkmodule_pdaf_inf - module pdaf information 291 * 292 */ 293 struct rkmodule_pdaf_inf { 294 __u32 flag; 295 296 __u32 gainmap_width; 297 __u32 gainmap_height; 298 __u32 dccmap_width; 299 __u32 dccmap_height; 300 __u32 dcc_mode; 301 __u32 dcc_dir; 302 __u16 gainmap[RKMODULE_PADF_GAINMAP_LEN]; 303 __u16 dccmap[RKMODULE_PDAF_DCCMAP_LEN]; 304 } __attribute__ ((packed)); 305 306 /** 307 * struct rkmodule_otp_module_inf - otp module info 308 * 309 */ 310 struct rkmodule_otp_module_inf { 311 __u32 flag; 312 __u8 vendor[8]; 313 __u32 module_id; 314 __u16 version; 315 __u16 full_width; 316 __u16 full_height; 317 __u8 supplier_id; 318 __u8 year; 319 __u8 mouth; 320 __u8 day; 321 __u8 sensor_id; 322 __u8 lens_id; 323 __u8 vcm_id; 324 __u8 drv_id; 325 __u8 flip; 326 } __attribute__ ((packed)); 327 328 /** 329 * struct rkmodule_inf - module information 330 * 331 */ 332 struct rkmodule_inf { 333 struct rkmodule_base_inf base; 334 struct rkmodule_fac_inf fac; 335 struct rkmodule_awb_inf awb; 336 struct rkmodule_lsc_inf lsc; 337 struct rkmodule_af_inf af; 338 struct rkmodule_pdaf_inf pdaf; 339 struct rkmodule_otp_module_inf module_inf; 340 } __attribute__ ((packed)); 341 342 /** 343 * struct rkmodule_awb_inf - module awb information 344 * 345 */ 346 struct rkmodule_awb_cfg { 347 __u32 enable; 348 __u32 golden_r_value; 349 __u32 golden_b_value; 350 __u32 golden_gr_value; 351 __u32 golden_gb_value; 352 } __attribute__ ((packed)); 353 354 /** 355 * struct rkmodule_af_cfg 356 * 357 */ 358 struct rkmodule_af_cfg { 359 __u32 enable; 360 __u32 vcm_start; 361 __u32 vcm_end; 362 __u32 vcm_dir; 363 } __attribute__ ((packed)); 364 365 /** 366 * struct rkmodule_lsc_cfg 367 * 368 */ 369 struct rkmodule_lsc_cfg { 370 __u32 enable; 371 } __attribute__ ((packed)); 372 373 /** 374 * NO_HDR: linear mode 375 * HDR_X2: hdr two frame or line mode 376 * HDR_X3: hdr three or line mode 377 * HDR_COMPR: linearised and compressed data for hdr 378 */ 379 enum rkmodule_hdr_mode { 380 NO_HDR = 0, 381 HDR_X2 = 5, 382 HDR_X3 = 6, 383 HDR_COMPR, 384 }; 385 386 enum rkmodule_hdr_compr_segment { 387 HDR_COMPR_SEGMENT_4 = 4, 388 HDR_COMPR_SEGMENT_12 = 12, 389 HDR_COMPR_SEGMENT_16 = 16, 390 }; 391 392 /* rkmodule_hdr_compr 393 * linearised and compressed data for hdr: data_src = K * data_compr + XX 394 * 395 * bit: bit of src data, max 20 bit. 396 * segment: linear segment, support 4, 6 or 16. 397 * k_shift: left shift bit of slop amplification factor, 2^k_shift, [0 15]. 398 * slope_k: K * 2^k_shift. 399 * data_src_shitf: left shift bit of source data, data_src = 2^data_src_shitf 400 * data_compr: compressed data. 401 */ 402 struct rkmodule_hdr_compr { 403 enum rkmodule_hdr_compr_segment segment; 404 __u8 bit; 405 __u8 k_shift; 406 __u8 data_src_shitf[HDR_COMPR_SEGMENT_16]; 407 __u16 data_compr[HDR_COMPR_SEGMENT_16]; 408 __u32 slope_k[HDR_COMPR_SEGMENT_16]; 409 }; 410 411 /** 412 * HDR_NORMAL_VC: hdr frame with diff virtual channels 413 * HDR_LINE_CNT: hdr frame with line counter 414 * HDR_ID_CODE: hdr frame with identification code 415 */ 416 enum hdr_esp_mode { 417 HDR_NORMAL_VC = 0, 418 HDR_LINE_CNT, 419 HDR_ID_CODE, 420 }; 421 422 /** 423 * lcnt: line counter 424 * padnum: the pixels of padding row 425 * padpix: the payload of padding 426 * idcd: identification code 427 * efpix: identification code of Effective line 428 * obpix: identification code of OB line 429 */ 430 struct rkmodule_hdr_esp { 431 enum hdr_esp_mode mode; 432 union { 433 struct { 434 __u32 padnum; 435 __u32 padpix; 436 } lcnt; 437 struct { 438 __u32 efpix; 439 __u32 obpix; 440 } idcd; 441 } val; 442 }; 443 444 struct rkmodule_hdr_cfg { 445 __u32 hdr_mode; 446 struct rkmodule_hdr_esp esp; 447 struct rkmodule_hdr_compr compr; 448 } __attribute__ ((packed)); 449 450 /* sensor lvds sync code 451 * sav: start of active video codes 452 * eav: end of active video codes 453 */ 454 struct rkmodule_sync_code { 455 __u16 sav; 456 __u16 eav; 457 }; 458 459 /* sensor lvds difference sync code mode 460 * LS_FIRST: valid line ls-le or sav-eav 461 * invalid line fs-fe or sav-eav 462 * FS_FIRST: valid line fs-le 463 * invalid line ls-fe 464 * ls: line start 465 * le: line end 466 * fs: frame start 467 * fe: frame end 468 * SONY_DOL_HDR_1: sony dol hdr pattern 1 469 * SONY_DOL_HDR_2: sony dol hdr pattern 2 470 */ 471 enum rkmodule_lvds_mode { 472 LS_FIRST = 0, 473 FS_FIRST, 474 SONY_DOL_HDR_1, 475 SONY_DOL_HDR_2 476 }; 477 478 /* sync code of different frame type (hdr or linear) for lvds 479 * act: valid line sync code 480 * blk: invalid line sync code 481 */ 482 struct rkmodule_lvds_frm_sync_code { 483 struct rkmodule_sync_code act; 484 struct rkmodule_sync_code blk; 485 }; 486 487 /* sync code for lvds of sensor 488 * odd_sync_code: sync code of odd frame id for lvds of sony sensor 489 * even_sync_code: sync code of even frame id for lvds of sony sensor 490 */ 491 struct rkmodule_lvds_frame_sync_code { 492 struct rkmodule_lvds_frm_sync_code odd_sync_code; 493 struct rkmodule_lvds_frm_sync_code even_sync_code; 494 }; 495 496 /* lvds sync code category of sensor for different operation */ 497 enum rkmodule_lvds_sync_code_group { 498 LVDS_CODE_GRP_LINEAR = 0x0, 499 LVDS_CODE_GRP_LONG, 500 LVDS_CODE_GRP_MEDIUM, 501 LVDS_CODE_GRP_SHORT, 502 LVDS_CODE_GRP_MAX 503 }; 504 505 /* struct rkmodule_lvds_cfg 506 * frm_sync_code[index]: 507 * index == LVDS_CODE_GRP_LONG: 508 * sync code for frame of linear mode or for long frame of hdr mode 509 * index == LVDS_CODE_GRP_MEDIUM: 510 * sync code for medium long frame of hdr mode 511 * index == LVDS_CODE_GRP_SHOR: 512 * sync code for short long frame of hdr mode 513 */ 514 struct rkmodule_lvds_cfg { 515 enum rkmodule_lvds_mode mode; 516 struct rkmodule_lvds_frame_sync_code frm_sync_code[LVDS_CODE_GRP_MAX]; 517 } __attribute__ ((packed)); 518 519 /** 520 * struct rkmodule_dpcc_cfg 521 * enable: 0 -> disable dpcc, 1 -> enable multiple, 522 * 2 -> enable single, 3 -> enable all; 523 * cur_single_dpcc: the strength of single dpcc; 524 * cur_multiple_dpcc: the strength of multiple dpcc; 525 * total_dpcc: the max strength; 526 */ 527 struct rkmodule_dpcc_cfg { 528 __u32 enable; 529 __u32 cur_single_dpcc; 530 __u32 cur_multiple_dpcc; 531 __u32 total_dpcc; 532 } __attribute__ ((packed)); 533 534 /** 535 * nr switch by gain 536 * direct: 0 -> up_thres LSNR to HSNR, 1 -> up_thres HSNR to LSNR 537 * up_thres: threshold of nr change from low gain to high gain 538 * down_thres: threshold of nr change from high gain to low gain; 539 * div_coeff: Coefficients converted from float to int 540 */ 541 struct rkmodule_nr_switch_threshold { 542 __u32 direct; 543 __u32 up_thres; 544 __u32 down_thres; 545 __u32 div_coeff; 546 } __attribute__ ((packed)); 547 548 /** 549 * enum rkmodule_bt656_intf_type 550 * to support sony bt656 raw 551 */ 552 enum rkmodule_bt656_intf_type { 553 BT656_STD_RAW = 0, 554 BT656_SONY_RAW, 555 }; 556 557 /** 558 * struct rkmodule_vc_fmt_info - virtual channels fmt info 559 * 560 */ 561 struct rkmodule_vc_fmt_info { 562 __u32 width[RKMODULE_MAX_VC_CH]; 563 __u32 height[RKMODULE_MAX_VC_CH]; 564 __u32 fps[RKMODULE_MAX_VC_CH]; 565 } __attribute__ ((packed)); 566 567 /** 568 * struct rkmodule_vc_hotplug_info - virtual channels hotplug status info 569 * detect_status: hotplug status 570 * bit 0~3 means channels id, value : 0 -> plug out, 1 -> plug in. 571 */ 572 struct rkmodule_vc_hotplug_info { 573 __u8 detect_status; 574 } __attribute__ ((packed)); 575 576 577 /* sensor start stream sequence 578 * RKMODULE_START_STREAM_DEFAULT: by default 579 * RKMODULE_START_STREAM_BEHIND : sensor start stream should be behind the controller 580 * RKMODULE_START_STREAM_FRONT : sensor start stream should be in front of the controller 581 */ 582 enum rkmodule_start_stream_seq { 583 RKMODULE_START_STREAM_DEFAULT = 0, 584 RKMODULE_START_STREAM_BEHIND, 585 RKMODULE_START_STREAM_FRONT, 586 }; 587 588 /* 589 * the causation to do cif reset work 590 */ 591 enum rkmodule_reset_src { 592 RKCIF_RESET_SRC_NON = 0x0, 593 RKCIF_RESET_SRC_ERR_CSI2, 594 RKCIF_RESET_SRC_ERR_LVDS, 595 RKICF_RESET_SRC_ERR_CUTOFF, 596 RKCIF_RESET_SRC_ERR_HOTPLUG, 597 RKCIF_RESET_SRC_ERR_APP, 598 }; 599 600 struct rkmodule_vicap_reset_info { 601 __u32 is_reset; 602 enum rkmodule_reset_src src; 603 } __attribute__ ((packed)); 604 605 struct rkmodule_bt656_mbus_info { 606 __u32 flags; 607 __u32 id_en_bits; 608 } __attribute__ ((packed)); 609 610 /* DCG ratio (float) = integer + decimal / div_coeff */ 611 struct rkmodule_dcg_ratio { 612 __u32 integer; 613 __u32 decimal; 614 __u32 div_coeff; 615 }; 616 617 struct rkmodule_channel_info { 618 __u32 index; 619 __u32 vc; 620 __u32 width; 621 __u32 height; 622 __u32 bus_fmt; 623 __u32 data_type; 624 __u32 data_bit; 625 } __attribute__ ((packed)); 626 627 /* 628 * link to vicap 629 * linear mode: pad0~pad3 for id0~id3; 630 * 631 * HDR_X2: id0 fiexd to vc0 for long frame 632 * id1 fixed to vc1 for short frame; 633 * id2~id3 reserved, can config by PAD2~PAD3 634 * 635 * HDR_X3: id0 fiexd to vc0 for long frame 636 * id1 fixed to vc1 for middle frame 637 * id2 fixed to vc2 for short frame; 638 * id3 reserved, can config by PAD3 639 * 640 * link to isp, the connection relationship is as follows 641 */ 642 enum rkmodule_max_pad { 643 PAD0, /* link to isp */ 644 PAD1, /* link to csi wr0 | hdr x2:L x3:M */ 645 PAD2, /* link to csi wr1 | hdr x3:L */ 646 PAD3, /* link to csi wr2 | hdr x2:M x3:S */ 647 PAD_MAX, 648 }; 649 650 /* 651 * sensor exposure sync mode 652 */ 653 enum rkmodule_sync_mode { 654 NO_SYNC_MODE = 0, 655 EXTERNAL_MASTER_MODE, 656 INTERNAL_MASTER_MODE, 657 SLAVE_MODE, 658 }; 659 660 struct rkmodule_mclk_data { 661 u32 enable; 662 u32 mclk_index; 663 u32 mclk_rate; 664 u32 reserved[8]; 665 }; 666 667 /* 668 * csi dphy param 669 * lp_vol_ref -> Reference voltage-645mV for LP Function control pin 670 * for rk3588 dcphy 671 * 3'b000 : 605mV 672 * 3'b001 : 625mV 673 * 3'b010 : 635mV 674 * 3'b011 : 645mV 675 * 3'b100 : 655mV 676 * 3'b101 : 665mV 677 * 3'b110 : 685mV 678 * 3'b111 : 725mV 679 * 680 * lp_hys_sw -> LP-RX Hysteresis Level Control 681 * for rk3588 dcphy 682 * 2'b00=45mV 683 * 2'b01=65mV 684 * 2'b10=85mV 685 * 2'b11=100mV 686 * 687 * lp_escclk_pol_sel -> LP ESCCLK Polarity sel 688 * for rk3588 dcphy 689 * 1'b0: normal 690 * 1'b1: swap ,Increase 1ns delay 691 * 692 * skew_data_cal_clk -> Skew Calibration Manual Data Fine Delay Control Register 693 * for rk3588 dcphy 694 * BIT[4:0] 30ps a step 695 * 696 * clk_hs_term_sel/data_hs_term_sel -> HS-RX Termination Impedance Control 697 * for rk3588 dcphy 698 * 3b'000 : 102Ω 699 * 3b'001 : 99.1Ω 700 * 3b'010 : 96.6Ω (default) 701 * 3b'011 : 94.1Ω 702 * 3b'100 : 113Ω 703 * 3b'101 : 110Ω 704 * 3b'110 : 107Ω 705 * 3b'111 : 104Ω 706 */ 707 708 enum csi2_dphy_vendor { 709 PHY_VENDOR_INNO = 0x0, 710 PHY_VENDOR_SAMSUNG = 0x01, 711 }; 712 713 struct rkmodule_csi_dphy_param { 714 u32 vendor; 715 u32 lp_vol_ref; 716 u32 lp_hys_sw[DPHY_MAX_LANE]; 717 u32 lp_escclk_pol_sel[DPHY_MAX_LANE]; 718 u32 skew_data_cal_clk[DPHY_MAX_LANE]; 719 u32 clk_hs_term_sel; 720 u32 data_hs_term_sel[DPHY_MAX_LANE]; 721 u32 reserved[32]; 722 }; 723 724 #endif /* _UAPI_RKMODULE_CAMERA_H */ 725