1 /* 2 * Copyright (c) 2024 Huawei Device Co., Ltd. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef API_RENDER_DEVICE_PIPELINE_STATE_DESC_H 17 #define API_RENDER_DEVICE_PIPELINE_STATE_DESC_H 18 19 #include <cstdint> 20 21 #include <base/containers/array_view.h> 22 #include <base/util/formats.h> 23 #include <render/namespace.h> 24 #include <render/resource_handle.h> 25 26 RENDER_BEGIN_NAMESPACE() 27 /** \addtogroup group_render_pipelinestatedesc 28 * @{ 29 */ 30 /** Size 2D */ 31 struct Size2D { 32 /** Width */ 33 uint32_t width { 0 }; 34 /** Height */ 35 uint32_t height { 0 }; 36 }; 37 38 /** Size 3D */ 39 struct Size3D { 40 /** Width */ 41 uint32_t width { 0 }; 42 /** Height */ 43 uint32_t height { 0 }; 44 /** Depth */ 45 uint32_t depth { 0 }; 46 }; 47 48 /** Offset 3D */ 49 struct Offset3D { 50 /** X offset */ 51 int32_t x { 0 }; 52 /** Y offset */ 53 int32_t y { 0 }; 54 /** Z offset */ 55 int32_t z { 0 }; 56 }; 57 58 /** Surface transform flag bits */ 59 enum SurfaceTransformFlagBits { 60 /** Identity bit */ 61 CORE_SURFACE_TRANSFORM_IDENTITY_BIT = 0x00000001, 62 /** Rotate 90 bit */ 63 CORE_SURFACE_TRANSFORM_ROTATE_90_BIT = 0x00000002, 64 /** Rotate 180 bit */ 65 CORE_SURFACE_TRANSFORM_ROTATE_180_BIT = 0x00000004, 66 /** Rotate 270 bit */ 67 CORE_SURFACE_TRANSFORM_ROTATE_270_BIT = 0x00000008, 68 }; 69 /** Container for surface transform flag bits */ 70 using SurfaceTransformFlags = uint32_t; 71 72 /** Index type */ 73 enum IndexType { 74 /** UINT16 */ 75 CORE_INDEX_TYPE_UINT16 = 0, 76 /** UINT32 */ 77 CORE_INDEX_TYPE_UINT32 = 1, 78 }; 79 80 /** Memory property flag bits */ 81 enum MemoryPropertyFlagBits { 82 /** Device local bit */ 83 CORE_MEMORY_PROPERTY_DEVICE_LOCAL_BIT = 0x00000001, 84 /** Host visible bit */ 85 CORE_MEMORY_PROPERTY_HOST_VISIBLE_BIT = 0x00000002, 86 /** Host visible bit */ 87 CORE_MEMORY_PROPERTY_HOST_COHERENT_BIT = 0x00000004, 88 /** Host cached bit, always preferred not required for allocation */ 89 CORE_MEMORY_PROPERTY_HOST_CACHED_BIT = 0x00000008, 90 /** Lazily allocated bit, always preferred not required for allocation */ 91 CORE_MEMORY_PROPERTY_LAZILY_ALLOCATED_BIT = 0x00000010, 92 /** Protected bit, always preferred not required for allocation */ 93 CORE_MEMORY_PROPERTY_PROTECTED_BIT = 0x00000020, 94 }; 95 /** Container for memory property flag bits */ 96 using MemoryPropertyFlags = uint32_t; 97 98 enum FormatFeatureFlagBits { 99 /** Sampled image bit */ 100 CORE_FORMAT_FEATURE_SAMPLED_IMAGE_BIT = 0x00000001, 101 /** Storage image bit */ 102 CORE_FORMAT_FEATURE_STORAGE_IMAGE_BIT = 0x00000002, 103 /** Image atomic bit */ 104 CORE_FORMAT_FEATURE_STORAGE_IMAGE_ATOMIC_BIT = 0x00000004, 105 /** Uniform texel buffer bit */ 106 CORE_FORMAT_FEATURE_UNIFORM_TEXEL_BUFFER_BIT = 0x00000008, 107 /** Storage texel buffer bit */ 108 CORE_FORMAT_FEATURE_STORAGE_TEXEL_BUFFER_BIT = 0x00000010, 109 /** Storage texel buffer atomic bit */ 110 CORE_FORMAT_FEATURE_STORAGE_TEXEL_BUFFER_ATOMIC_BIT = 0x00000020, 111 /** Vertex buffer bit */ 112 CORE_FORMAT_FEATURE_VERTEX_BUFFER_BIT = 0x00000040, 113 /** Color attachment bit */ 114 CORE_FORMAT_FEATURE_COLOR_ATTACHMENT_BIT = 0x00000080, 115 /** Color attachment blend bit */ 116 CORE_FORMAT_FEATURE_COLOR_ATTACHMENT_BLEND_BIT = 0x00000100, 117 /** Depth stencil attachment bit */ 118 CORE_FORMAT_FEATURE_DEPTH_STENCIL_ATTACHMENT_BIT = 0x00000200, 119 /** Blit src bit */ 120 CORE_FORMAT_FEATURE_BLIT_SRC_BIT = 0x00000400, 121 /** Blit dst bit */ 122 CORE_FORMAT_FEATURE_BLIT_DST_BIT = 0x00000800, 123 /** Sampled image filter linear bit */ 124 CORE_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_LINEAR_BIT = 0x00001000, 125 /** Transfer src bit */ 126 CORE_FORMAT_FEATURE_TRANSFER_SRC_BIT = 0x00004000, 127 /** Transfer dst bit */ 128 CORE_FORMAT_FEATURE_TRANSFER_DST_BIT = 0x00008000, 129 /** Fragment shading rate attachment bit */ 130 CORE_FORMAT_FEATURE_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT = 0x40000000, 131 }; 132 /** Format feature flags */ 133 using FormatFeatureFlags = uint32_t; 134 135 /** Format properties */ 136 struct FormatProperties { 137 /** Linear tiling feature flags */ 138 FormatFeatureFlags linearTilingFeatures { 0u }; 139 /** Optimal tiling feature flags */ 140 FormatFeatureFlags optimalTilingFeatures { 0u }; 141 /** Buffer feature flags */ 142 FormatFeatureFlags bufferFeatures { 0u }; 143 /** Bytes per pixel */ 144 uint32_t bytesPerPixel { 0u }; 145 }; 146 147 /** Fragment shading rate properties */ 148 struct FragmentShadingRateProperties { 149 /** Min fragment shading rate attachment texel size */ 150 Size2D minFragmentShadingRateAttachmentTexelSize; 151 /** Max fragment shading rate attachment texel size */ 152 Size2D maxFragmentShadingRateAttachmentTexelSize; 153 /** Max fragment size */ 154 Size2D maxFragmentSize; 155 }; 156 157 /** Image layout */ 158 enum ImageLayout { 159 /** Undefined */ 160 CORE_IMAGE_LAYOUT_UNDEFINED = 0, 161 /** General */ 162 CORE_IMAGE_LAYOUT_GENERAL = 1, 163 /** Color attachment optimal */ 164 CORE_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL = 2, 165 /** Depth stencil attachment optimal */ 166 CORE_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL = 3, 167 /** Depth stencil read only optimal */ 168 CORE_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL = 4, 169 /** Shader read only optimal */ 170 CORE_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL = 5, 171 /** Transfer source optimal */ 172 CORE_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL = 6, 173 /** Transfer destination optimal */ 174 CORE_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL = 7, 175 /** Preinitialized */ 176 CORE_IMAGE_LAYOUT_PREINITIALIZED = 8, 177 /** Depth read only stencil attachment optimal */ 178 CORE_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL = 1000117000, 179 /** Depth attachment stencil read only optimal */ 180 CORE_IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL = 1000117001, 181 /** Present source */ 182 CORE_IMAGE_LAYOUT_PRESENT_SRC = 1000001002, 183 /** Shared present source */ 184 CORE_IMAGE_LAYOUT_SHARED_PRESENT = 1000111000, 185 /** Shared present source KHR */ 186 CORE_IMAGE_LAYOUT_FRAGMENT_SHADING_RATE_ATTACHMENT_OPTIMAL = 1000164003, 187 /** Max enumeration */ 188 CORE_IMAGE_LAYOUT_MAX_ENUM = 0x7FFFFFFF 189 }; 190 191 /** Image aspect flag bits */ 192 enum ImageAspectFlagBits { 193 /** Color bit */ 194 CORE_IMAGE_ASPECT_COLOR_BIT = 0x00000001, 195 /** Depth bit */ 196 CORE_IMAGE_ASPECT_DEPTH_BIT = 0x00000002, 197 /** Stencil bit */ 198 CORE_IMAGE_ASPECT_STENCIL_BIT = 0x00000004, 199 /** Metadata bit */ 200 CORE_IMAGE_ASPECT_METADATA_BIT = 0x00000008, 201 /** Aspect plane 0 */ 202 CORE_IMAGE_ASPECT_PLANE_0_BIT = 0x00000010, 203 /** Aspect plane 1 */ 204 CORE_IMAGE_ASPECT_PLANE_1_BIT = 0x00000020, 205 /** Aspect plane 2 */ 206 CORE_IMAGE_ASPECT_PLANE_2_BIT = 0x00000040, 207 }; 208 /** Container for image aspect flag bits */ 209 using ImageAspectFlags = uint32_t; 210 211 /** Access flag bits */ 212 enum AccessFlagBits { 213 /** Indirect command read bit */ 214 CORE_ACCESS_INDIRECT_COMMAND_READ_BIT = 0x00000001, 215 /** Index read bit */ 216 CORE_ACCESS_INDEX_READ_BIT = 0x00000002, 217 /** Vertex attribute read bit */ 218 CORE_ACCESS_VERTEX_ATTRIBUTE_READ_BIT = 0x00000004, 219 /** Uniform read bit */ 220 CORE_ACCESS_UNIFORM_READ_BIT = 0x00000008, 221 /** Input attachment read bit */ 222 CORE_ACCESS_INPUT_ATTACHMENT_READ_BIT = 0x00000010, 223 /** Shader read bit */ 224 CORE_ACCESS_SHADER_READ_BIT = 0x00000020, 225 /** Shader write bit */ 226 CORE_ACCESS_SHADER_WRITE_BIT = 0x00000040, 227 /** Color attachment read bit */ 228 CORE_ACCESS_COLOR_ATTACHMENT_READ_BIT = 0x00000080, 229 /** Color attachment write bit */ 230 CORE_ACCESS_COLOR_ATTACHMENT_WRITE_BIT = 0x00000100, 231 /** Depth stencil attachment read bit */ 232 CORE_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT = 0x00000200, 233 /** Depth stencil attachment write bit */ 234 CORE_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT = 0x00000400, 235 /** Transfer read bit */ 236 CORE_ACCESS_TRANSFER_READ_BIT = 0x00000800, 237 /** Transfer write bit */ 238 CORE_ACCESS_TRANSFER_WRITE_BIT = 0x00001000, 239 /** Host read bit */ 240 CORE_ACCESS_HOST_READ_BIT = 0x00002000, 241 /** Host write bit */ 242 CORE_ACCESS_HOST_WRITE_BIT = 0x00004000, 243 /** Memory read bit */ 244 CORE_ACCESS_MEMORY_READ_BIT = 0x00008000, 245 /** Memory write bit */ 246 CORE_ACCESS_MEMORY_WRITE_BIT = 0x00010000, 247 /** Fragment shading rate attachment read bit */ 248 CORE_ACCESS_FRAGMENT_SHADING_RATE_ATTACHMENT_READ_BIT = 0x00800000, 249 }; 250 /** Container for access flag bits */ 251 using AccessFlags = uint32_t; 252 253 /** Pipeline stage flag bits */ 254 enum PipelineStageFlagBits { 255 /** Top of pipe bit */ 256 CORE_PIPELINE_STAGE_TOP_OF_PIPE_BIT = 0x00000001, 257 /** Draw indirect bit */ 258 CORE_PIPELINE_STAGE_DRAW_INDIRECT_BIT = 0x00000002, 259 /** Vertex input bit */ 260 CORE_PIPELINE_STAGE_VERTEX_INPUT_BIT = 0x00000004, 261 /** Vertex shader bit */ 262 CORE_PIPELINE_STAGE_VERTEX_SHADER_BIT = 0x00000008, 263 /** Fragment shader bit */ 264 CORE_PIPELINE_STAGE_FRAGMENT_SHADER_BIT = 0x00000080, 265 /** Early fragment tests bit */ 266 CORE_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT = 0x00000100, 267 /** Late fragment tests bit */ 268 CORE_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT = 0x00000200, 269 /** Color attachment output bit */ 270 CORE_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT = 0x00000400, 271 /** Compute shader bit */ 272 CORE_PIPELINE_STAGE_COMPUTE_SHADER_BIT = 0x00000800, 273 /** Transfer bit */ 274 CORE_PIPELINE_STAGE_TRANSFER_BIT = 0x00001000, 275 /** Bottom of pipe bit */ 276 CORE_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT = 0x00002000, 277 /** Host bit */ 278 CORE_PIPELINE_STAGE_HOST_BIT = 0x00004000, 279 /** All graphics bit */ 280 CORE_PIPELINE_STAGE_ALL_GRAPHICS_BIT = 0x00008000, 281 /** All commands bit */ 282 CORE_PIPELINE_STAGE_ALL_COMMANDS_BIT = 0x00010000, 283 /** Fragment shading rate attacchment bit */ 284 CORE_PIPELINE_STAGE_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT = 0x00400000, 285 }; 286 /** Container for pipeline stage flag bits */ 287 using PipelineStageFlags = uint32_t; 288 289 /** GPU queue */ 290 struct GpuQueue { 291 /** Queue type */ 292 enum class QueueType { 293 /** Undefined queue type */ 294 UNDEFINED = 0x0, 295 /** Graphics */ 296 GRAPHICS = 0x1, 297 /** Compute */ 298 COMPUTE = 0x2, 299 /** Transfer */ 300 TRANSFER = 0x4, 301 }; 302 303 /** Type of queue */ 304 QueueType type { QueueType::UNDEFINED }; 305 /** Index of queue */ 306 uint32_t index { 0 }; 307 }; 308 309 /** Descriptor type */ 310 enum DescriptorType { 311 /** Sampler */ 312 CORE_DESCRIPTOR_TYPE_SAMPLER = 0, 313 /** Combined image sampler */ 314 CORE_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER = 1, 315 /** Sampled image */ 316 CORE_DESCRIPTOR_TYPE_SAMPLED_IMAGE = 2, 317 /** Storage image */ 318 CORE_DESCRIPTOR_TYPE_STORAGE_IMAGE = 3, 319 /** Uniform texel buffer */ 320 CORE_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER = 4, 321 /** Storage texel buffer */ 322 CORE_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER = 5, 323 /** Uniform buffer */ 324 CORE_DESCRIPTOR_TYPE_UNIFORM_BUFFER = 6, 325 /** Storage buffer */ 326 CORE_DESCRIPTOR_TYPE_STORAGE_BUFFER = 7, 327 /** Dynamic uniform buffer */ 328 CORE_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC = 8, 329 /** Dynamic storage buffer */ 330 CORE_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC = 9, 331 /** Input attachment */ 332 CORE_DESCRIPTOR_TYPE_INPUT_ATTACHMENT = 10, 333 /** Acceleration structure */ 334 CORE_DESCRIPTOR_TYPE_ACCELERATION_STRUCTURE = 1000150000, 335 /** Max enumeration */ 336 CORE_DESCRIPTOR_TYPE_MAX_ENUM = 0x7FFFFFFF 337 }; 338 339 /** Additional descriptor flag bits */ 340 enum AdditionalDescriptorFlagBits { 341 /** Immutable sampler is used */ 342 CORE_ADDITIONAL_DESCRIPTOR_IMMUTABLE_SAMPLER_BIT = 0x00000001, 343 }; 344 /** Container for sampler descriptor flag bits */ 345 using AdditionalDescriptorFlags = uint32_t; 346 347 /** Shader stage flag bits */ 348 enum ShaderStageFlagBits { 349 /** Vertex bit */ 350 CORE_SHADER_STAGE_VERTEX_BIT = 0x00000001, 351 /** Fragment bit */ 352 CORE_SHADER_STAGE_FRAGMENT_BIT = 0x00000010, 353 /** Compute bit */ 354 CORE_SHADER_STAGE_COMPUTE_BIT = 0x00000020, 355 /** All graphics */ 356 CORE_SHADER_STAGE_ALL_GRAPHICS = 0x0000001F, 357 /** All */ 358 CORE_SHADER_STAGE_ALL = 0x7FFFFFFF, 359 }; 360 /** Shader stage flags */ 361 using ShaderStageFlags = uint32_t; 362 363 /** Pipeline bind point */ 364 enum PipelineBindPoint { 365 /** Bind point graphics */ 366 CORE_PIPELINE_BIND_POINT_GRAPHICS = 0, 367 /** Bind point compute */ 368 CORE_PIPELINE_BIND_POINT_COMPUTE = 1, 369 /** Max enumeration */ 370 CORE_PIPELINE_BIND_POINT_MAX_ENUM = 0x7FFFFFFF 371 }; 372 373 /** Query pipeline statistic flag bits */ 374 enum QueryPipelineStatisticFlagBits { 375 /** Input assembly vertices bit */ 376 CORE_QUERY_PIPELINE_STATISTIC_INPUT_ASSEMBLY_VERTICES_BIT = 0x00000001, 377 /** Input assembly primitives bit */ 378 CORE_QUERY_PIPELINE_STATISTIC_INPUT_ASSEMBLY_PRIMITIVES_BIT = 0x00000002, 379 /** Vertex shader invocations bit */ 380 CORE_QUERY_PIPELINE_STATISTIC_VERTEX_SHADER_INVOCATIONS_BIT = 0x00000004, 381 /* Geometry shader invocations bit */ 382 CORE_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_INVOCATIONS_BIT = 0x00000008, 383 /* Geometry shader primitives bit */ 384 CORE_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT = 0x00000010, 385 /** Clipping invocations bit */ 386 CORE_QUERY_PIPELINE_STATISTIC_CLIPPING_INVOCATIONS_BIT = 0x00000020, 387 /** Clipping primitives bit */ 388 CORE_QUERY_PIPELINE_STATISTIC_CLIPPING_PRIMITIVES_BIT = 0x00000040, 389 /** Fragment shader invocations bit */ 390 CORE_QUERY_PIPELINE_STATISTIC_FRAGMENT_SHADER_INVOCATIONS_BIT = 0x00000080, 391 /* Tesselation control shader patches bit */ 392 CORE_QUERY_PIPELINE_STATISTIC_TESSELLATION_CONTROL_SHADER_PATCHES_BIT = 0x00000100, 393 /* Tesselation evaluation shader invocations bit */ 394 CORE_QUERY_PIPELINE_STATISTIC_TESSELLATION_EVALUATION_SHADER_INVOCATIONS_BIT = 0x00000200, 395 /** Compute shader invocations bit */ 396 CORE_QUERY_PIPELINE_STATISTIC_COMPUTE_SHADER_INVOCATIONS_BIT = 0x00000400, 397 }; 398 /** Query pipeline statistic flags */ 399 using QueryPipelineStatisticFlags = uint32_t; 400 401 /** Query type */ 402 enum QueryType { 403 /** Timestamp */ 404 CORE_QUERY_TYPE_TIMESTAMP = 2, 405 /** Max enumeration */ 406 CORE_QUERY_TYPE_MAX_ENUM = 0x7FFFFFFF 407 }; 408 409 /** Vertex input rate */ 410 enum VertexInputRate { 411 /** Vertex */ 412 CORE_VERTEX_INPUT_RATE_VERTEX = 0, 413 /** Instance */ 414 CORE_VERTEX_INPUT_RATE_INSTANCE = 1, 415 }; 416 417 /** Polygon mode */ 418 enum PolygonMode { 419 /** Fill */ 420 CORE_POLYGON_MODE_FILL = 0, 421 /** Line */ 422 CORE_POLYGON_MODE_LINE = 1, 423 /** Point */ 424 CORE_POLYGON_MODE_POINT = 2, 425 }; 426 427 /** Cull mode flag bits */ 428 enum CullModeFlagBits { 429 /** None */ 430 CORE_CULL_MODE_NONE = 0, 431 /** Front bit */ 432 CORE_CULL_MODE_FRONT_BIT = 0x00000001, 433 /** Back bit */ 434 CORE_CULL_MODE_BACK_BIT = 0x00000002, 435 /** Front and back bit */ 436 CORE_CULL_MODE_FRONT_AND_BACK = 0x00000003, 437 }; 438 /** Cull mode flags */ 439 using CullModeFlags = uint32_t; 440 441 /** Front face */ 442 enum FrontFace { 443 /** Counter clockwise */ 444 CORE_FRONT_FACE_COUNTER_CLOCKWISE = 0, 445 /** Clockwise */ 446 CORE_FRONT_FACE_CLOCKWISE = 1, 447 }; 448 449 /** Stencil face flag bits */ 450 enum StencilFaceFlagBits { 451 /** Face front bit */ 452 CORE_STENCIL_FACE_FRONT_BIT = 0x00000001, 453 /** Face back bit */ 454 CORE_STENCIL_FACE_BACK_BIT = 0x00000002, 455 /** Front and back */ 456 CORE_STENCIL_FRONT_AND_BACK = 0x00000003, 457 }; 458 /** Lume stencil face flags */ 459 using StencilFaceFlags = uint32_t; 460 461 /** Compare op */ 462 enum CompareOp { 463 /** Never */ 464 CORE_COMPARE_OP_NEVER = 0, 465 /** Less */ 466 CORE_COMPARE_OP_LESS = 1, 467 /** Equal */ 468 CORE_COMPARE_OP_EQUAL = 2, 469 /** Less or equal */ 470 CORE_COMPARE_OP_LESS_OR_EQUAL = 3, 471 /** Greater */ 472 CORE_COMPARE_OP_GREATER = 4, 473 /** Not equal */ 474 CORE_COMPARE_OP_NOT_EQUAL = 5, 475 /** Greater or equal */ 476 CORE_COMPARE_OP_GREATER_OR_EQUAL = 6, 477 /** Always */ 478 CORE_COMPARE_OP_ALWAYS = 7, 479 }; 480 481 /** Stencil op */ 482 enum StencilOp { 483 /** Keep */ 484 CORE_STENCIL_OP_KEEP = 0, 485 /** Zero */ 486 CORE_STENCIL_OP_ZERO = 1, 487 /** Replace */ 488 CORE_STENCIL_OP_REPLACE = 2, 489 /** Increment and clamp */ 490 CORE_STENCIL_OP_INCREMENT_AND_CLAMP = 3, 491 /** Decrement and clamp */ 492 CORE_STENCIL_OP_DECREMENT_AND_CLAMP = 4, 493 /** Invert */ 494 CORE_STENCIL_OP_INVERT = 5, 495 /** Increment and wrap */ 496 CORE_STENCIL_OP_INCREMENT_AND_WRAP = 6, 497 /** Decrement and wrap */ 498 CORE_STENCIL_OP_DECREMENT_AND_WRAP = 7, 499 }; 500 501 /** Primitive topology */ 502 enum PrimitiveTopology { 503 /** Point list */ 504 CORE_PRIMITIVE_TOPOLOGY_POINT_LIST = 0, 505 /** Line list */ 506 CORE_PRIMITIVE_TOPOLOGY_LINE_LIST = 1, 507 /** Line strip */ 508 CORE_PRIMITIVE_TOPOLOGY_LINE_STRIP = 2, 509 /** Triangle list */ 510 CORE_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST = 3, 511 /** Triangle strip */ 512 CORE_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP = 4, 513 /** Triangle fan */ 514 CORE_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN = 5, 515 /** Line list with adjacency */ 516 CORE_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY = 6, 517 /** Line strip with adjacency */ 518 CORE_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY = 7, 519 /** Triangle list with adjacency */ 520 CORE_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY = 8, 521 /** Triangle strip with adjacency */ 522 CORE_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY = 9, 523 /** Patch list */ 524 CORE_PRIMITIVE_TOPOLOGY_PATCH_LIST = 10, 525 /** Max enum (not defined) */ 526 CORE_PRIMITIVE_TOPOLOGY_MAX_ENUM = 0x7FFFFFFF, 527 }; 528 529 /** Blend factor */ 530 enum BlendFactor { 531 /** Zero */ 532 CORE_BLEND_FACTOR_ZERO = 0, 533 /** One */ 534 CORE_BLEND_FACTOR_ONE = 1, 535 /** Source color */ 536 CORE_BLEND_FACTOR_SRC_COLOR = 2, 537 /** One minus source color */ 538 CORE_BLEND_FACTOR_ONE_MINUS_SRC_COLOR = 3, 539 /** Destination color */ 540 CORE_BLEND_FACTOR_DST_COLOR = 4, 541 /** One minus destination color */ 542 CORE_BLEND_FACTOR_ONE_MINUS_DST_COLOR = 5, 543 /** Source alpha */ 544 CORE_BLEND_FACTOR_SRC_ALPHA = 6, 545 /** One minus source alpha */ 546 CORE_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA = 7, 547 /** Destination alpha */ 548 CORE_BLEND_FACTOR_DST_ALPHA = 8, 549 /** One minus destination alpha */ 550 CORE_BLEND_FACTOR_ONE_MINUS_DST_ALPHA = 9, 551 /** Constant color */ 552 CORE_BLEND_FACTOR_CONSTANT_COLOR = 10, 553 /** One minus constant color */ 554 CORE_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR = 11, 555 /** Constant alpha */ 556 CORE_BLEND_FACTOR_CONSTANT_ALPHA = 12, 557 /** One minus constant alpha */ 558 CORE_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA = 13, 559 /** Source alpha saturate */ 560 CORE_BLEND_FACTOR_SRC_ALPHA_SATURATE = 14, 561 /** Source one color */ 562 CORE_BLEND_FACTOR_SRC1_COLOR = 15, 563 /** One minus source one color */ 564 CORE_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR = 16, 565 /** Source one alpha */ 566 CORE_BLEND_FACTOR_SRC1_ALPHA = 17, 567 /** One minus source one alpha */ 568 CORE_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA = 18, 569 }; 570 571 /** Blend op */ 572 enum BlendOp { 573 /** Add */ 574 CORE_BLEND_OP_ADD = 0, 575 /** Subtract */ 576 CORE_BLEND_OP_SUBTRACT = 1, 577 /** Reverse subtract */ 578 CORE_BLEND_OP_REVERSE_SUBTRACT = 2, 579 /** Min */ 580 CORE_BLEND_OP_MIN = 3, 581 /** Max */ 582 CORE_BLEND_OP_MAX = 4, 583 }; 584 585 /** Color component flag bits */ 586 enum ColorComponentFlagBits { 587 /** Red bit */ 588 CORE_COLOR_COMPONENT_R_BIT = 0x00000001, 589 /** Green bit */ 590 CORE_COLOR_COMPONENT_G_BIT = 0x00000002, 591 /** Blue bit */ 592 CORE_COLOR_COMPONENT_B_BIT = 0x00000004, 593 /** Alpha bit */ 594 CORE_COLOR_COMPONENT_A_BIT = 0x00000008, 595 }; 596 /** Color component flags */ 597 using ColorComponentFlags = uint32_t; 598 599 /** Logic op */ 600 enum LogicOp { 601 /** Clear */ 602 CORE_LOGIC_OP_CLEAR = 0, 603 /** And */ 604 CORE_LOGIC_OP_AND = 1, 605 /** And reverse */ 606 CORE_LOGIC_OP_AND_REVERSE = 2, 607 /** Copy */ 608 CORE_LOGIC_OP_COPY = 3, 609 /** And inverted */ 610 CORE_LOGIC_OP_AND_INVERTED = 4, 611 /** No op */ 612 CORE_LOGIC_OP_NO_OP = 5, 613 /** Xor */ 614 CORE_LOGIC_OP_XOR = 6, 615 /** Or */ 616 CORE_LOGIC_OP_OR = 7, 617 /** Nor */ 618 CORE_LOGIC_OP_NOR = 8, 619 /** Equivalent */ 620 CORE_LOGIC_OP_EQUIVALENT = 9, 621 /** Invert */ 622 CORE_LOGIC_OP_INVERT = 10, 623 /** Or reverse */ 624 CORE_LOGIC_OP_OR_REVERSE = 11, 625 /** Copy inverted */ 626 CORE_LOGIC_OP_COPY_INVERTED = 12, 627 /** Or inverted */ 628 CORE_LOGIC_OP_OR_INVERTED = 13, 629 /** Nand */ 630 CORE_LOGIC_OP_NAND = 14, 631 /** Set */ 632 CORE_LOGIC_OP_SET = 15, 633 }; 634 635 /** Attachment load op */ 636 enum AttachmentLoadOp { 637 /** Load */ 638 CORE_ATTACHMENT_LOAD_OP_LOAD = 0, 639 /** Clear */ 640 CORE_ATTACHMENT_LOAD_OP_CLEAR = 1, 641 /** Dont care */ 642 CORE_ATTACHMENT_LOAD_OP_DONT_CARE = 2, 643 }; 644 645 /** Attachment store op */ 646 enum AttachmentStoreOp { 647 /** Store */ 648 CORE_ATTACHMENT_STORE_OP_STORE = 0, 649 /** Dont care */ 650 CORE_ATTACHMENT_STORE_OP_DONT_CARE = 1, 651 }; 652 653 /** Clear color value */ 654 union ClearColorValue { 655 ClearColorValue() = default; 656 ~ClearColorValue() = default; ClearColorValue(float r,float g,float b,float a)657 constexpr ClearColorValue(float r, float g, float b, float a) : float32 { r, g, b, a } {}; ClearColorValue(int32_t r,int32_t g,int32_t b,int32_t a)658 constexpr ClearColorValue(int32_t r, int32_t g, int32_t b, int32_t a) : int32 { r, g, b, a } {}; ClearColorValue(uint32_t r,uint32_t g,uint32_t b,uint32_t a)659 constexpr ClearColorValue(uint32_t r, uint32_t g, uint32_t b, uint32_t a) : uint32 { r, g, b, a } {}; 660 /** Float32 array of 4 */ 661 float float32[4]; 662 /** int32 array of 4 */ 663 int32_t int32[4]; 664 /** uint32 array of 4 */ 665 uint32_t uint32[4]; 666 }; 667 668 /** Clear depth stencil value */ 669 struct ClearDepthStencilValue { 670 /** Depth, default value 1.0f */ 671 float depth; 672 /** Stencil */ 673 uint32_t stencil; 674 }; 675 676 /** Clear value */ 677 union ClearValue { 678 ClearValue() = default; 679 ~ClearValue() = default; ClearValue(const ClearColorValue & color)680 constexpr explicit ClearValue(const ClearColorValue& color) : color { color } {}; ClearValue(const ClearDepthStencilValue & depthStencil)681 constexpr explicit ClearValue(const ClearDepthStencilValue& depthStencil) : depthStencil { depthStencil } {}; ClearValue(float r,float g,float b,float a)682 constexpr ClearValue(float r, float g, float b, float a) : color { r, g, b, a } {}; ClearValue(int32_t r,int32_t g,int32_t b,int32_t a)683 constexpr ClearValue(int32_t r, int32_t g, int32_t b, int32_t a) : color { r, g, b, a } {}; ClearValue(uint32_t r,uint32_t g,uint32_t b,uint32_t a)684 constexpr ClearValue(uint32_t r, uint32_t g, uint32_t b, uint32_t a) : color { r, g, b, a } {}; ClearValue(float depth,uint32_t stencil)685 constexpr ClearValue(float depth, uint32_t stencil) : depthStencil { depth, stencil } {}; 686 687 /** Color */ 688 ClearColorValue color; 689 /** Depth stencil */ 690 ClearDepthStencilValue depthStencil; 691 }; 692 693 /** Dynamic state flag bits 694 * Dynamic state flags only map to basic dynamic states. 695 * Use DynamicStateEnum s when creating the actual pso objects. 696 */ 697 enum DynamicStateFlagBits { 698 /** Undefined */ 699 CORE_DYNAMIC_STATE_UNDEFINED = 0, 700 /** Viewport */ 701 CORE_DYNAMIC_STATE_VIEWPORT = (1 << 0), 702 /** Scissor */ 703 CORE_DYNAMIC_STATE_SCISSOR = (1 << 1), 704 /** Line width */ 705 CORE_DYNAMIC_STATE_LINE_WIDTH = (1 << 2), 706 /** Depth bias */ 707 CORE_DYNAMIC_STATE_DEPTH_BIAS = (1 << 3), 708 /** Blend constants */ 709 CORE_DYNAMIC_STATE_BLEND_CONSTANTS = (1 << 4), 710 /** Depth bounds */ 711 CORE_DYNAMIC_STATE_DEPTH_BOUNDS = (1 << 5), 712 /** Stencil compare mask */ 713 CORE_DYNAMIC_STATE_STENCIL_COMPARE_MASK = (1 << 6), 714 /** Stencil write mask */ 715 CORE_DYNAMIC_STATE_STENCIL_WRITE_MASK = (1 << 7), 716 /** Stencil reference */ 717 CORE_DYNAMIC_STATE_STENCIL_REFERENCE = (1 << 8), 718 }; 719 /** Dynamic state flags */ 720 using DynamicStateFlags = uint32_t; 721 722 /** Dynamic states */ 723 enum DynamicStateEnum { 724 /** Viewport */ 725 CORE_DYNAMIC_STATE_ENUM_VIEWPORT = 0, 726 /** Scissor */ 727 CORE_DYNAMIC_STATE_ENUM_SCISSOR = 1, 728 /** Line width */ 729 CORE_DYNAMIC_STATE_ENUM_LINE_WIDTH = 2, 730 /** Depth bias */ 731 CORE_DYNAMIC_STATE_ENUM_DEPTH_BIAS = 3, 732 /** Blend constants */ 733 CORE_DYNAMIC_STATE_ENUM_BLEND_CONSTANTS = 4, 734 /** Depth bounds */ 735 CORE_DYNAMIC_STATE_ENUM_DEPTH_BOUNDS = 5, 736 /** Stencil compare mask */ 737 CORE_DYNAMIC_STATE_ENUM_STENCIL_COMPARE_MASK = 6, 738 /** Stencil write mask */ 739 CORE_DYNAMIC_STATE_ENUM_STENCIL_WRITE_MASK = 7, 740 /** Stencil reference */ 741 CORE_DYNAMIC_STATE_ENUM_STENCIL_REFERENCE = 8, 742 /** Fragment shading rate */ 743 CORE_DYNAMIC_STATE_ENUM_FRAGMENT_SHADING_RATE = 1000226000, 744 /** Max enumeration */ 745 CORE_DYNAMIC_STATE_ENUM_MAX_ENUM = 0x7FFFFFFF 746 }; 747 748 /** Resolve mode flag bits */ 749 enum ResolveModeFlagBits { 750 /** None. No resolve mode done */ 751 CORE_RESOLVE_MODE_NONE = 0, 752 /** Resolve value is same as sample zero */ 753 CORE_RESOLVE_MODE_SAMPLE_ZERO_BIT = 0x00000001, 754 /** Resolve value is same as average of all samples */ 755 CORE_RESOLVE_MODE_AVERAGE_BIT = 0x00000002, 756 /** Resolve value is same as min of all samples */ 757 CORE_RESOLVE_MODE_MIN_BIT = 0x00000004, 758 /** Resolve value is same as max of all samples */ 759 CORE_RESOLVE_MODE_MAX_BIT = 0x00000008, 760 }; 761 /** Resolve mode flags */ 762 using ResolveModeFlags = uint32_t; 763 764 /** SubpassContents Specifies how commands in the first subpass are provided 765 * CORE_SUBPASS_CONTENTS_INLINE == subpasses are recorded to the same render command list 766 * CORE_SUBPASS_CONTENTS_SECONDARY_COMMAND_LISTS == subpasses are recorded to secondary command lists 767 */ 768 enum SubpassContents { 769 /** Inline */ 770 CORE_SUBPASS_CONTENTS_INLINE = 0, 771 /* Secondary command lists */ 772 CORE_SUBPASS_CONTENTS_SECONDARY_COMMAND_LISTS = 1, 773 }; 774 775 /** Subpass flag bits 776 */ 777 enum SubpassFlagBits { 778 /* Merge subpass to previous subpasses */ 779 CORE_SUBPASS_MERGE_BIT = 1, 780 }; 781 /** Subpass flags */ 782 using SubpassFlags = uint32_t; 783 784 /** Fragment shading rate combiner op */ 785 enum FragmentShadingRateCombinerOp { 786 /** Keep */ 787 CORE_FRAGMENT_SHADING_RATE_COMBINER_OP_KEEP = 0, 788 /** Replace */ 789 CORE_FRAGMENT_SHADING_RATE_COMBINER_OP_REPLACE = 1, 790 /** Min */ 791 CORE_FRAGMENT_SHADING_RATE_COMBINER_OP_MIN = 2, 792 /** Max */ 793 CORE_FRAGMENT_SHADING_RATE_COMBINER_OP_MAX = 3, 794 /** Mul */ 795 CORE_FRAGMENT_SHADING_RATE_COMBINER_OP_MUL = 4, 796 }; 797 798 /** Fragment shading rate combiner operations for commands */ 799 struct FragmentShadingRateCombinerOps { 800 /** First combiner (combine pipeline and primitive shading rates) */ 801 FragmentShadingRateCombinerOp op1 { CORE_FRAGMENT_SHADING_RATE_COMBINER_OP_KEEP }; 802 /** Second combiner (combine the first with attachment fragment shading rate) */ 803 FragmentShadingRateCombinerOp op2 { CORE_FRAGMENT_SHADING_RATE_COMBINER_OP_KEEP }; 804 }; 805 806 /** Pipeline state constants */ 807 struct PipelineStateConstants { 808 /** GPU buffer whole size */ 809 static constexpr uint32_t GPU_BUFFER_WHOLE_SIZE { ~0u }; 810 /** GPU image all mip levels */ 811 static constexpr uint32_t GPU_IMAGE_ALL_MIP_LEVELS { ~0u }; 812 /** GPU image all layers */ 813 static constexpr uint32_t GPU_IMAGE_ALL_LAYERS { ~0u }; 814 /** Max vertex buffer count */ 815 static constexpr uint32_t MAX_VERTEX_BUFFER_COUNT { 8u }; 816 817 /** Max input attachment count */ 818 static constexpr uint32_t MAX_INPUT_ATTACHMENT_COUNT { 8u }; 819 /** Max color attachment count */ 820 static constexpr uint32_t MAX_COLOR_ATTACHMENT_COUNT { 8u }; 821 /** Max resolve attachment count */ 822 static constexpr uint32_t MAX_RESOLVE_ATTACHMENT_COUNT { 4u }; 823 /** Max render pass attachment count */ 824 static constexpr uint32_t MAX_RENDER_PASS_ATTACHMENT_COUNT { 8u }; 825 /** Max render node gpu wait signals */ 826 static constexpr uint32_t MAX_RENDER_NODE_GPU_WAIT_SIGNALS { 4u }; 827 }; 828 829 /** Viewport descriptor 830 * x and y are upper left corner (x,y) */ 831 struct ViewportDesc { 832 /** X point */ 833 float x { 0.0f }; 834 /** Y point */ 835 float y { 0.0f }; 836 /** Width */ 837 float width { 0.0f }; 838 /** Height */ 839 float height { 0.0f }; 840 841 /** Min depth (0.0f - 1.0f) */ 842 float minDepth { 0.0f }; 843 /** Max depth (0.0f - 1.0f) */ 844 float maxDepth { 1.0f }; 845 }; 846 847 /** Scissor descriptor */ 848 struct ScissorDesc { 849 /** X offset */ 850 int32_t offsetX { 0 }; 851 /** Y offset */ 852 int32_t offsetY { 0 }; 853 /** Extent width */ 854 uint32_t extentWidth { 0 }; 855 /** Extent height */ 856 uint32_t extentHeight { 0 }; 857 }; 858 859 /** Image subresource layers */ 860 struct ImageSubresourceLayers { 861 /** Image aspect flags */ 862 ImageAspectFlags imageAspectFlags { 0 }; 863 /** Mip level */ 864 uint32_t mipLevel { 0 }; 865 /** Base array layer */ 866 uint32_t baseArrayLayer { 0 }; 867 /** Layer count */ 868 uint32_t layerCount { PipelineStateConstants::GPU_IMAGE_ALL_LAYERS }; 869 }; 870 871 /** Image subresource range */ 872 struct ImageSubresourceRange { 873 /** Image aspect flags */ 874 ImageAspectFlags imageAspectFlags { 0 }; 875 /** Base mip level */ 876 uint32_t baseMipLevel { 0 }; 877 /** Level count */ 878 uint32_t levelCount { PipelineStateConstants::GPU_IMAGE_ALL_MIP_LEVELS }; 879 /** Base array layer */ 880 uint32_t baseArrayLayer { 0 }; 881 /** Layer count */ 882 uint32_t layerCount { PipelineStateConstants::GPU_IMAGE_ALL_LAYERS }; 883 }; 884 885 /** Image blit */ 886 struct ImageBlit { 887 /** Source subresource */ 888 ImageSubresourceLayers srcSubresource; 889 /** Source offsets (top left and bottom right coordinates) */ 890 Size3D srcOffsets[2u]; 891 /** Destination subresource */ 892 ImageSubresourceLayers dstSubresource; 893 /** Destination offsets (top left and bottom right coordinates) */ 894 Size3D dstOffsets[2u]; 895 }; 896 897 /** Memory barrier with pipeline stages */ 898 struct GeneralBarrier { 899 /** Access flags */ 900 AccessFlags accessFlags { 0 }; 901 /** Pipeline stage flags */ 902 PipelineStageFlags pipelineStageFlags { 0 }; 903 }; 904 905 /** Buffer resource barrier */ 906 struct BufferResourceBarrier { 907 /** Access flags */ 908 AccessFlags accessFlags { 0 }; 909 /** Pipeline stage flags */ 910 PipelineStageFlags pipelineStageFlags { 0 }; 911 }; 912 913 /** Image resource barrier */ 914 struct ImageResourceBarrier { 915 /** Access flags */ 916 AccessFlags accessFlags { 0 }; 917 /** Pipeline stage flags */ 918 PipelineStageFlags pipelineStageFlags { 0 }; 919 /** Image layout */ 920 ImageLayout imageLayout { ImageLayout::CORE_IMAGE_LAYOUT_UNDEFINED }; 921 }; 922 923 /** Buffer copy */ 924 struct BufferCopy { 925 /** Offset to source buffer */ 926 uint32_t srcOffset { 0 }; 927 /** Offset to destination buffer */ 928 uint32_t dstOffset { 0 }; 929 /** Size of copy */ 930 uint32_t size { 0 }; 931 }; 932 933 /** Buffer image copy */ 934 struct BufferImageCopy { 935 /** Buffer offset */ 936 uint32_t bufferOffset { 0 }; 937 /** Buffer row length */ 938 uint32_t bufferRowLength { 0 }; 939 /** Buffer image height */ 940 uint32_t bufferImageHeight { 0 }; 941 /** Image subresource */ 942 ImageSubresourceLayers imageSubresource; 943 /** Image offset */ 944 Size3D imageOffset; 945 /** Image extent */ 946 Size3D imageExtent; 947 }; 948 949 /** Image copy */ 950 struct ImageCopy { 951 /** Src image subresource */ 952 ImageSubresourceLayers srcSubresource; 953 /** Src offset */ 954 Offset3D srcOffset; 955 /** Dst image subresource */ 956 ImageSubresourceLayers dstSubresource; 957 /** Dst offset */ 958 Offset3D dstOffset; 959 /** Texel size of copy */ 960 Size3D extent; 961 }; 962 963 /** GPU resource state in pipeline */ 964 struct GpuResourceState { 965 /** Shader stage flags */ 966 ShaderStageFlags shaderStageFlags { 0 }; 967 968 /** Access flags */ 969 AccessFlags accessFlags { 0 }; 970 /** Pipeline stage flags */ 971 PipelineStageFlags pipelineStageFlags { 0 }; 972 973 /** GPU queue */ 974 GpuQueue gpuQueue {}; 975 }; 976 977 /** Render pass descriptor */ 978 struct RenderPassDesc { 979 /** Render area */ 980 struct RenderArea { 981 /** X offset */ 982 int32_t offsetX { 0 }; 983 /** Y offset */ 984 int32_t offsetY { 0 }; 985 /** Extent width */ 986 uint32_t extentWidth { 0u }; 987 /** Extent height */ 988 uint32_t extentHeight { 0u }; 989 }; 990 991 /** Attachment descriptor */ 992 struct AttachmentDesc { 993 /** Layer for layered image */ 994 uint32_t layer { 0u }; 995 /** Mip level to target on mipped image */ 996 uint32_t mipLevel { 0u }; 997 998 // following values are not needed in render pass compatibility 999 /** Load operation */ 1000 AttachmentLoadOp loadOp { AttachmentLoadOp::CORE_ATTACHMENT_LOAD_OP_DONT_CARE }; 1001 /** Store operation */ 1002 AttachmentStoreOp storeOp { AttachmentStoreOp::CORE_ATTACHMENT_STORE_OP_DONT_CARE }; 1003 1004 /** Stencil load operation */ 1005 AttachmentLoadOp stencilLoadOp { AttachmentLoadOp::CORE_ATTACHMENT_LOAD_OP_DONT_CARE }; 1006 /** Stencil store operation */ 1007 AttachmentStoreOp stencilStoreOp { AttachmentStoreOp::CORE_ATTACHMENT_STORE_OP_DONT_CARE }; 1008 1009 /** Clear value (union ClearColorValue or ClearDepthStencilValue) */ 1010 ClearValue clearValue {}; 1011 }; 1012 1013 /** Attachment count */ 1014 uint32_t attachmentCount { 0u }; 1015 1016 /** Attachment handles */ 1017 RenderHandle attachmentHandles[PipelineStateConstants::MAX_RENDER_PASS_ATTACHMENT_COUNT]; 1018 /** Attachments */ 1019 AttachmentDesc attachments[PipelineStateConstants::MAX_RENDER_PASS_ATTACHMENT_COUNT]; 1020 1021 /** Render area */ 1022 RenderArea renderArea; 1023 1024 /** Subpass count */ 1025 uint32_t subpassCount { 0u }; 1026 /** Subpass contents */ 1027 SubpassContents subpassContents { SubpassContents::CORE_SUBPASS_CONTENTS_INLINE }; 1028 }; 1029 1030 /** Render pass descriptor with render handle references */ 1031 struct RenderPassDescWithHandleReference { 1032 /** Attachment count */ 1033 uint32_t attachmentCount { 0u }; 1034 1035 /** Attachment handles */ 1036 RenderHandleReference attachmentHandles[PipelineStateConstants::MAX_RENDER_PASS_ATTACHMENT_COUNT]; 1037 /** Attachments */ 1038 RenderPassDesc::AttachmentDesc attachments[PipelineStateConstants::MAX_RENDER_PASS_ATTACHMENT_COUNT]; 1039 1040 /** Render area */ 1041 RenderPassDesc::RenderArea renderArea; 1042 1043 /** Subpass count */ 1044 uint32_t subpassCount { 0u }; 1045 /** Subpass contents */ 1046 SubpassContents subpassContents { SubpassContents::CORE_SUBPASS_CONTENTS_INLINE }; 1047 }; 1048 1049 /** Render pass subpass descriptor */ 1050 struct RenderPassSubpassDesc { 1051 // indices to render pass attachments 1052 /** Depth attachment index */ 1053 uint32_t depthAttachmentIndex { ~0u }; 1054 /** Depth resolve attachment index */ 1055 uint32_t depthResolveAttachmentIndex { ~0u }; 1056 /** Input attachment indices */ 1057 uint32_t inputAttachmentIndices[PipelineStateConstants::MAX_INPUT_ATTACHMENT_COUNT] {}; 1058 /** Color attachment indices */ 1059 uint32_t colorAttachmentIndices[PipelineStateConstants::MAX_COLOR_ATTACHMENT_COUNT] {}; 1060 /** Resolve attachment indices */ 1061 uint32_t resolveAttachmentIndices[PipelineStateConstants::MAX_RESOLVE_ATTACHMENT_COUNT] {}; 1062 /** Fragment shading rate attachment index */ 1063 uint32_t fragmentShadingRateAttachmentIndex { ~0u }; 1064 1065 // attachment counts in this subpass 1066 /** Depth attachment count in this subpass */ 1067 uint32_t depthAttachmentCount { 0u }; 1068 /** Depth resolve attachment count in this subpass */ 1069 uint32_t depthResolveAttachmentCount { 0u }; 1070 /** Input attachment count in this subpass */ 1071 uint32_t inputAttachmentCount { 0u }; 1072 /** Color attachment count in this subpass */ 1073 uint32_t colorAttachmentCount { 0u }; 1074 /** Resolve attachment count in this subpass */ 1075 uint32_t resolveAttachmentCount { 0u }; 1076 /** Fragmend shading rate attachment count in this subpass */ 1077 uint32_t fragmentShadingRateAttachmentCount { 0u }; 1078 1079 /** Depth resolve mode flag bit */ 1080 ResolveModeFlags depthResolveModeFlags { ResolveModeFlagBits::CORE_RESOLVE_MODE_NONE }; 1081 /** Stencil resolve mode flag bit */ 1082 ResolveModeFlags stencilResolveModeFlags { ResolveModeFlagBits::CORE_RESOLVE_MODE_NONE }; 1083 1084 /** Shading rate texel size for subpass (will be clamped to device limits automatically if not set accordingly) */ 1085 Size2D shadingRateTexelSize { 1u, 1u }; 1086 1087 /** Multi-view bitfield of view indices. Multi-view is ignored while zero. */ 1088 uint32_t viewMask { 0u }; 1089 1090 /** Subpass flags */ 1091 SubpassFlags subpassFlags { 0u }; 1092 }; 1093 1094 /** Render pass */ 1095 struct RenderPass { 1096 /** Render pass descriptor */ 1097 RenderPassDesc renderPassDesc; 1098 /** Subpass start index */ 1099 uint32_t subpassStartIndex { 0u }; 1100 /** Subpass descriptor */ 1101 RenderPassSubpassDesc subpassDesc; 1102 }; 1103 1104 /** Render pass with render handle references */ 1105 struct RenderPassWithHandleReference { 1106 /** Render pass descriptor */ 1107 RenderPassDescWithHandleReference renderPassDesc; 1108 /** Subpass start index */ 1109 uint32_t subpassStartIndex { 0u }; 1110 /** Subpass descriptor */ 1111 RenderPassSubpassDesc subpassDesc; 1112 }; 1113 1114 /** Forced graphics state flag bits */ 1115 enum GraphicsStateFlagBits { 1116 /** Input assembly bit */ 1117 CORE_GRAPHICS_STATE_INPUT_ASSEMBLY_BIT = 0x00000001, 1118 /** Rastarization state bit */ 1119 CORE_GRAPHICS_STATE_RASTERIZATION_STATE_BIT = 0x00000002, 1120 /** Depth stencil state bit */ 1121 CORE_GRAPHICS_STATE_DEPTH_STENCIL_STATE_BIT = 0x00000004, 1122 /** Color blend state bit */ 1123 CORE_GRAPHICS_STATE_COLOR_BLEND_STATE_BIT = 0x00000008, 1124 }; 1125 /** Container for graphics state flag bits */ 1126 using GraphicsStateFlags = uint32_t; 1127 1128 /** Graphics state */ 1129 struct GraphicsState { 1130 /** Stencil operation state */ 1131 struct StencilOpState { 1132 /** Fail operation */ 1133 StencilOp failOp { StencilOp::CORE_STENCIL_OP_KEEP }; 1134 /** Pass operation */ 1135 StencilOp passOp { StencilOp::CORE_STENCIL_OP_KEEP }; 1136 /** Depth fail operation */ 1137 StencilOp depthFailOp { StencilOp::CORE_STENCIL_OP_KEEP }; 1138 /** Compare operation */ 1139 CompareOp compareOp { CompareOp::CORE_COMPARE_OP_NEVER }; 1140 /** Compare mask */ 1141 uint32_t compareMask { 0 }; 1142 /** Write mask */ 1143 uint32_t writeMask { 0 }; 1144 /** Reference */ 1145 uint32_t reference { 0 }; 1146 }; 1147 1148 /** Rasterization state */ 1149 struct RasterizationState { 1150 /** Enable depth clamp */ 1151 bool enableDepthClamp { false }; 1152 /** Enable depth bias */ 1153 bool enableDepthBias { false }; 1154 /** Enable rasterizer discard */ 1155 bool enableRasterizerDiscard { false }; 1156 1157 /** Polygon mode */ 1158 PolygonMode polygonMode { PolygonMode::CORE_POLYGON_MODE_FILL }; 1159 /** Cull mode flags */ 1160 CullModeFlags cullModeFlags { CullModeFlagBits::CORE_CULL_MODE_NONE }; 1161 /** Front face */ 1162 FrontFace frontFace { FrontFace::CORE_FRONT_FACE_COUNTER_CLOCKWISE }; 1163 1164 /** Depth bias constant factor */ 1165 float depthBiasConstantFactor { 0.0f }; 1166 /** Depth bias clamp */ 1167 float depthBiasClamp { 0.0f }; 1168 /** Depth bias slope factor */ 1169 float depthBiasSlopeFactor { 0.0f }; 1170 1171 /** Line width */ 1172 float lineWidth { 1.0f }; 1173 }; 1174 1175 /** Depth stencil state */ 1176 struct DepthStencilState { 1177 /** Enable depth test */ 1178 bool enableDepthTest { false }; 1179 /** Enable depth write */ 1180 bool enableDepthWrite { false }; 1181 /** Enable depth bounds test */ 1182 bool enableDepthBoundsTest { false }; 1183 /** Enable stencil test */ 1184 bool enableStencilTest { false }; 1185 1186 /** Min depth bounds */ 1187 float minDepthBounds { 0.0f }; 1188 /** Max depth bounds */ 1189 float maxDepthBounds { 1.0f }; 1190 1191 /** Depth compare operation */ 1192 CompareOp depthCompareOp { CompareOp::CORE_COMPARE_OP_NEVER }; 1193 /** Front stencil operation state */ 1194 StencilOpState frontStencilOpState {}; 1195 /** Back stencil operation state */ 1196 StencilOpState backStencilOpState {}; 1197 }; 1198 1199 /** Color blend state */ 1200 struct ColorBlendState { 1201 /** Attachment */ 1202 struct Attachment { 1203 /** Enable blend */ 1204 bool enableBlend { false }; 1205 /** Color write mask */ 1206 ColorComponentFlags colorWriteMask { ColorComponentFlagBits::CORE_COLOR_COMPONENT_R_BIT | 1207 ColorComponentFlagBits::CORE_COLOR_COMPONENT_G_BIT | 1208 ColorComponentFlagBits::CORE_COLOR_COMPONENT_B_BIT | 1209 ColorComponentFlagBits::CORE_COLOR_COMPONENT_A_BIT }; 1210 1211 /** Source color blend factor */ 1212 BlendFactor srcColorBlendFactor { BlendFactor::CORE_BLEND_FACTOR_ONE }; 1213 /** Destination color blend factor */ 1214 BlendFactor dstColorBlendFactor { BlendFactor::CORE_BLEND_FACTOR_ONE }; 1215 /** Color blend operation */ 1216 BlendOp colorBlendOp { BlendOp::CORE_BLEND_OP_ADD }; 1217 1218 /** Source alpha blend factor */ 1219 BlendFactor srcAlphaBlendFactor { BlendFactor::CORE_BLEND_FACTOR_ONE }; 1220 /** Destination alpha blend factor */ 1221 BlendFactor dstAlphaBlendFactor { BlendFactor::CORE_BLEND_FACTOR_ONE }; 1222 /** Alpha blend operation */ 1223 BlendOp alphaBlendOp { BlendOp::CORE_BLEND_OP_ADD }; 1224 }; 1225 1226 /** Enable logic operation */ 1227 bool enableLogicOp { false }; 1228 /** Logic operation */ 1229 LogicOp logicOp { LogicOp::CORE_LOGIC_OP_NO_OP }; 1230 1231 /** Color blend constants (R, G, B, A) */ 1232 float colorBlendConstants[4u] { 0.0f, 0.0f, 0.0f, 0.0f }; 1233 /** Color attachment count */ 1234 uint32_t colorAttachmentCount { 0 }; 1235 /** Color attachments */ 1236 Attachment colorAttachments[PipelineStateConstants::MAX_COLOR_ATTACHMENT_COUNT]; 1237 }; 1238 1239 /** Input assembly */ 1240 struct InputAssembly { 1241 /** Enable primitive restart */ 1242 bool enablePrimitiveRestart { false }; 1243 /** Primitive topology */ 1244 PrimitiveTopology primitiveTopology { PrimitiveTopology::CORE_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST }; 1245 }; 1246 1247 /** Input assembly */ 1248 InputAssembly inputAssembly; 1249 /** Rasterization state */ 1250 RasterizationState rasterizationState; 1251 /** Depth stencil state */ 1252 DepthStencilState depthStencilState; 1253 /** Color blend state */ 1254 ColorBlendState colorBlendState; 1255 }; 1256 1257 /** Vertex input declaration */ 1258 struct VertexInputDeclaration { 1259 /** Vertex input binding description */ 1260 struct VertexInputBindingDescription { 1261 /** Binding */ 1262 uint32_t binding { ~0u }; 1263 /** Stride */ 1264 uint32_t stride { 0u }; 1265 /** Vertex input rate */ 1266 VertexInputRate vertexInputRate { VertexInputRate::CORE_VERTEX_INPUT_RATE_VERTEX }; 1267 }; 1268 1269 /** Vertex input attribute description */ 1270 struct VertexInputAttributeDescription { 1271 /** Location */ 1272 uint32_t location { ~0u }; 1273 /** Binding */ 1274 uint32_t binding { ~0u }; 1275 /** Format */ 1276 BASE_NS::Format format { BASE_NS::Format::BASE_FORMAT_UNDEFINED }; 1277 /** Offset */ 1278 uint32_t offset { 0u }; 1279 }; 1280 }; 1281 1282 /** Vertex input declaration data */ 1283 struct VertexInputDeclarationData { 1284 /** Binding description count */ 1285 uint32_t bindingDescriptionCount { 0 }; 1286 /** Attribute description count */ 1287 uint32_t attributeDescriptionCount { 0 }; 1288 1289 /** Array of binding descriptions */ 1290 VertexInputDeclaration::VertexInputBindingDescription 1291 bindingDescriptions[PipelineStateConstants::MAX_VERTEX_BUFFER_COUNT]; 1292 /** Array of attribute descriptions */ 1293 VertexInputDeclaration::VertexInputAttributeDescription 1294 attributeDescriptions[PipelineStateConstants::MAX_VERTEX_BUFFER_COUNT]; 1295 }; 1296 1297 /** Vertex input declaration view */ 1298 struct VertexInputDeclarationView { 1299 /** Array of binding descriptions */ 1300 BASE_NS::array_view<const VertexInputDeclaration::VertexInputBindingDescription> bindingDescriptions; 1301 /** Array of attribute descriptions */ 1302 BASE_NS::array_view<const VertexInputDeclaration::VertexInputAttributeDescription> attributeDescriptions; 1303 }; 1304 1305 /** Shader specialization */ 1306 struct ShaderSpecialization { 1307 /** Constant */ 1308 struct Constant { 1309 enum class Type : uint32_t { 1310 INVALID = 0, 1311 /** 32 bit boolean value */ 1312 BOOL = 1, 1313 /** 32 bit unsigned integer value */ 1314 UINT32 = 2, 1315 /** 32 bit signed integer value */ 1316 INT32 = 3, 1317 /** 32 bit floating-point value */ 1318 FLOAT = 4, 1319 }; 1320 /** Shader stage */ 1321 ShaderStageFlags shaderStage; 1322 /** ID */ 1323 uint32_t id; 1324 /** Type */ 1325 Type type; 1326 /** Offset */ 1327 uint32_t offset; 1328 }; 1329 }; 1330 1331 /** Shader specialization constant view */ 1332 struct ShaderSpecializationConstantView { 1333 /** Array of shader specialization constants */ 1334 BASE_NS::array_view<const ShaderSpecialization::Constant> constants; 1335 }; 1336 1337 /** Shader specialization constant data view */ 1338 struct ShaderSpecializationConstantDataView { 1339 /** Array of shader specialization constants */ 1340 BASE_NS::array_view<const ShaderSpecialization::Constant> constants; 1341 /** Data */ 1342 BASE_NS::array_view<const uint32_t> data; 1343 }; 1344 1345 /** Buffer offset */ 1346 struct BufferOffset { 1347 /** Buffer handle */ 1348 RenderHandle handle; 1349 /** Buffer offset in bytes */ 1350 uint32_t offset { 0 }; 1351 }; 1352 1353 /** Accleration structure types */ 1354 enum AccelerationStructureType : uint32_t { 1355 /** Acceleration structure type top level */ 1356 CORE_ACCELERATION_STRUCTURE_TYPE_TOP_LEVEL = 0, 1357 /** Acceleration structure type bottom level */ 1358 CORE_ACCELERATION_STRUCTURE_TYPE_BOTTOM_LEVEL = 1, 1359 /** Acceleration structure type generic */ 1360 CORE_ACCELERATION_STRUCTURE_TYPE_GENERIC = 2, 1361 }; 1362 1363 struct AccelerationStructureBuildRangeInfo { 1364 uint32_t primitiveCount { 0u }; 1365 uint32_t primitiveOffset { 0u }; 1366 uint32_t firstVertex { 0u }; 1367 uint32_t transformOffset { 0u }; 1368 }; 1369 1370 /** Additional parameters for geometry */ 1371 enum GeometryFlagBits : uint32_t { 1372 /** The geometry does not invoke the any-hit shaders even if present in a hit group */ 1373 GEOMETRY_OPAQUE_BIT = 0x00000001, 1374 /** Indicates that the implementation must only call the any-hit shader a single time for each primitive 1375 * in this geometry. 1376 */ 1377 GEOMETRY_NO_DUPLICATE_ANY_HIT_INVOCATION_BIT = 0x00000002, 1378 }; 1379 /** Geometry flags */ 1380 using GeometryFlags = uint32_t; 1381 1382 /** Acceleratoin structure geometry triangles data */ 1383 struct AccelerationStructureGeometryTrianglesInfo { 1384 /** Vertex format */ 1385 BASE_NS::Format vertexFormat { BASE_NS::Format::BASE_FORMAT_UNDEFINED }; 1386 /** Vertex stride, bytes between each vertex */ 1387 uint32_t vertexStride { 0u }; 1388 /** Highest index of a vertex for building geom */ 1389 uint32_t maxVertex { 0u }; 1390 /** Index type */ 1391 IndexType indexType { IndexType::CORE_INDEX_TYPE_UINT32 }; 1392 /** Index count */ 1393 uint32_t indexCount { 0u }; 1394 1395 /** Geometry flags */ 1396 GeometryFlags geometryFlags { 0u }; 1397 }; 1398 1399 /** Acceleratoin structure geometry triangles data */ 1400 struct AccelerationStructureGeometryTrianglesData { 1401 /** Triangles info */ 1402 AccelerationStructureGeometryTrianglesInfo info; 1403 1404 /** Vertex buffer with offset */ 1405 BufferOffset vertexData; 1406 /** Index buffer with offset */ 1407 BufferOffset indexData; 1408 /** Transform buffer (4x3 matrices), additional */ 1409 BufferOffset transformData; 1410 }; 1411 1412 /** Acceleration structure geometry AABBs info */ 1413 struct AccelerationStructureGeometryAabbsInfo { 1414 /** Stride, bytes between each AABB (must be a multiple of 8) */ 1415 uint32_t stride { 0u }; 1416 }; 1417 1418 /** Acceleration structure geometry AABBs data */ 1419 struct AccelerationStructureGeometryAabbsData { 1420 /** AABBs info */ 1421 AccelerationStructureGeometryAabbsInfo info; 1422 /** Buffer resource and offset for AabbPositions */ 1423 BufferOffset data; 1424 }; 1425 1426 /** Acceleration structure geometry instances info */ 1427 struct AccelerationStructureGeometryInstancesInfo { 1428 /** Specifies whether data is used as an array of addresses or just an array */ 1429 bool arrayOfPointers { false }; 1430 }; 1431 1432 /** Acceleration structure geometry instances data */ 1433 struct AccelerationStructureGeometryInstancesData { 1434 /** Instances info */ 1435 AccelerationStructureGeometryInstancesInfo info; 1436 /** Buffer resource and offset for structures */ 1437 BufferOffset data; 1438 }; 1439 1440 /** Build acceleration structure flag bits */ 1441 enum BuildAccelerationStructureFlagBits : uint32_t { 1442 /** Can be updated */ 1443 CORE_BUILD_ACCELERATION_STRUCTURE_ALLOW_UPDATE_BIT = 0x00000001, 1444 /** Alloc compaction bit. Can be used as a source for compaction. */ 1445 CORE_BUILD_ACCELERATION_STRUCTURE_ALLOW_COMPACTION_BIT = 0x00000002, 1446 /** Prefer fast trace. Prioritizes trace performance for build time. */ 1447 CORE_BUILD_ACCELERATION_STRUCTURE_PREFER_FAST_TRACE_BIT = 0x00000004, 1448 /** Prefer fast build. Prioritizes fast build for trace performance. */ 1449 CORE_BUILD_ACCELERATION_STRUCTURE_PREFER_FAST_BUILD_BIT = 0x00000008, 1450 /** Prefer low memory. Prioritizes the size of the scratch memory and the final acceleration structure, 1451 * potentially at the expense of build time or trace performance */ 1452 CORE_BUILD_ACCELERATION_STRUCTURE_LOW_MEMORY_BIT = 0x00000010, 1453 }; 1454 /** Build acceleration structure flags */ 1455 using BuildAccelerationStructureFlags = uint32_t; 1456 1457 /** Build acceleration structure mode */ 1458 enum BuildAccelerationStructureMode : uint32_t { 1459 /** The destination acceleration structure will be built using the specified geometries */ 1460 CORE_BUILD_ACCELERATION_STRUCTURE_MODE_BUILD = 0, 1461 /** The destination acceleration structure will be built using data in a source acceleration structure, 1462 * updated by the specified geometries. */ 1463 CORE_BUILD_ACCELERATION_STRUCTURE_MODE_UPDATE = 1, 1464 }; 1465 1466 /** Acceleration structure build geometry info */ 1467 struct AccelerationStructureBuildGeometryInfo { 1468 /** Acceleration structure type */ 1469 AccelerationStructureType type { AccelerationStructureType::CORE_ACCELERATION_STRUCTURE_TYPE_TOP_LEVEL }; 1470 /** Additional flags */ 1471 BuildAccelerationStructureFlags flags { 0 }; 1472 /** Build mode */ 1473 BuildAccelerationStructureMode mode { 1474 BuildAccelerationStructureMode::CORE_BUILD_ACCELERATION_STRUCTURE_MODE_BUILD 1475 }; 1476 }; 1477 1478 /** Acceleration structure build geometry data */ 1479 struct AccelerationStructureBuildGeometryData { 1480 /** Geometry info */ 1481 AccelerationStructureBuildGeometryInfo info; 1482 1483 /** Handle to existing acceleration structure which is used a src for dst update. */ 1484 RenderHandle srcAccelerationStructure; 1485 /** Handle to dst acceleration structure which is to be build. */ 1486 RenderHandle dstAccelerationStructure; 1487 /** Handle and offset to build scratch data. */ 1488 BufferOffset scratchBuffer; 1489 }; 1490 1491 /** Acceleration structure build sizes. 1492 * The build sizes can be queried from device with AccelerationStructureBuildGeometryInfo. 1493 */ 1494 struct AccelerationStructureBuildSizes { 1495 /** Acceleration structure size */ 1496 uint32_t accelerationStructureSize { 0u }; 1497 /** Update scratch size */ 1498 uint32_t updateScratchSize { 0u }; 1499 /** Build scratch size */ 1500 uint32_t buildScratchSize { 0u }; 1501 }; 1502 1503 /** Geometry type. 1504 */ 1505 enum GeometryType : uint32_t { 1506 /** Triangles */ 1507 CORE_GEOMETRY_TYPE_TRIANGLES = 0, 1508 /** AABBs */ 1509 CORE_GEOMETRY_TYPE_AABBS = 1, 1510 /** Instances */ 1511 CORE_GEOMETRY_TYPE_INSTANCES = 2, 1512 }; 1513 1514 /** Geometry instance flags. 1515 */ 1516 enum GeometryInstanceFlagBits : uint32_t { 1517 /** Disable face culling */ 1518 CORE_GEOMETRY_INSTANCE_TRIANGLE_FACING_CULL_DISABLE_BIT = 0x00000001, 1519 /** Invert the facing */ 1520 CORE_GEOMETRY_INSTANCE_TRIANGLE_FLIP_FACING_BIT = 0x00000002, 1521 /** Force geometry to be treated as opaque */ 1522 CORE_GEOMETRY_INSTANCE_FORCE_OPAQUE_BIT = 0x00000004, 1523 /** Removes opaque bit from geometry. Can be overriden with SPIR-v OpaqueKHR flag */ 1524 CORE_GEOMETRY_INSTANCE_FORCE_NO_OPAQUE_BIT = 0x00000008, 1525 }; 1526 using GeometryInstanceFlags = uint32_t; 1527 1528 /** Acceleration structure instance info. 1529 */ 1530 struct AccelerationStructureInstanceInfo { 1531 /** Affine transform matrix (4x3 used) */ 1532 // BASE_NS::Math::Mat4X4 transform{}; 1533 float transform[4][4]; 1534 /** User specified index accessable in ray shaders with InstanceCustomIndexKHR (24 bits) */ 1535 uint32_t instanceCustomIndex { 0u }; 1536 /** Mask, a visibility mask for geometry (8 bits). Instance may only be hit if cull mask & instance.mask != 0. */ 1537 uint8_t mask { 0u }; 1538 /** GeometryInstanceFlags for this instance */ 1539 GeometryInstanceFlags flags { 0u }; 1540 }; 1541 1542 /** Acceleration structure instance data. 1543 */ 1544 struct AccelerationStructureInstanceData { 1545 /** Instance info */ 1546 AccelerationStructureInstanceInfo info; 1547 1548 /** Acceleration structure handle */ 1549 RenderHandle accelerationStructureReference; 1550 }; 1551 /** @} */ 1552 RENDER_END_NAMESPACE() 1553 1554 #endif // API_RENDER_DEVICE_PIPELINE_STATE_DESC_H 1555