1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Author: Huacai Chen <chenhuacai@loongson.cn>
4 * Copyright (C) 2020 Loongson Technology Corporation Limited
5 */
6 #include <linux/bitfield.h>
7 #include <linux/bitops.h>
8 #include <linux/bug.h>
9 #include <linux/compiler.h>
10 #include <linux/context_tracking.h>
11 #include <linux/entry-common.h>
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/kexec.h>
15 #include <linux/module.h>
16 #include <linux/extable.h>
17 #include <linux/mm.h>
18 #include <linux/sched/mm.h>
19 #include <linux/sched/debug.h>
20 #include <linux/smp.h>
21 #include <linux/spinlock.h>
22 #include <linux/kallsyms.h>
23 #include <linux/memblock.h>
24 #include <linux/interrupt.h>
25 #include <linux/ptrace.h>
26 #include <linux/kgdb.h>
27 #include <linux/kdebug.h>
28 #include <linux/notifier.h>
29 #include <linux/kdb.h>
30 #include <linux/irq.h>
31 #include <linux/perf_event.h>
32
33 #include <asm/addrspace.h>
34 #include <asm/bootinfo.h>
35 #include <asm/branch.h>
36 #include <asm/break.h>
37 #include <asm/cpu.h>
38 #include <asm/exception.h>
39 #include <asm/fpu.h>
40 #include <asm/inst.h>
41 #include <asm/loongarchregs.h>
42 #include <asm/pgtable.h>
43 #include <asm/ptrace.h>
44 #include <asm/sections.h>
45 #include <asm/siginfo.h>
46 #include <asm/tlb.h>
47 #include <asm/watch.h>
48 #include <asm/mmu_context.h>
49 #include <asm/types.h>
50 #include <asm/stacktrace.h>
51 #include <asm/unwind.h>
52 #include <asm/lbt.h>
53
54 #include "access-helper.h"
55
56 void *exception_table[EXCCODE_INT_START] = {
57 [0 ... EXCCODE_INT_START - 1] = handle_reserved,
58
59 [EXCCODE_TLBI] = handle_tlb_load,
60 [EXCCODE_TLBL] = handle_tlb_load,
61 [EXCCODE_TLBS] = handle_tlb_store,
62 [EXCCODE_TLBM] = handle_tlb_modify,
63 [EXCCODE_TLBNR] = handle_tlb_protect,
64 [EXCCODE_TLBNX] = handle_tlb_protect,
65 [EXCCODE_TLBPE] = handle_tlb_protect,
66 [EXCCODE_ADE] = handle_ade,
67 [EXCCODE_ALE] = handle_ale,
68 [EXCCODE_BCE] = handle_bce,
69 [EXCCODE_SYS] = handle_sys,
70 [EXCCODE_BP] = handle_bp,
71 [EXCCODE_INE] = handle_ri,
72 [EXCCODE_IPE] = handle_ri,
73 [EXCCODE_FPDIS] = handle_fpu,
74 [EXCCODE_LSXDIS] = handle_lsx,
75 [EXCCODE_LASXDIS] = handle_lasx,
76 [EXCCODE_FPE] = handle_fpe,
77 [EXCCODE_BTDIS] = handle_lbt,
78 [EXCCODE_WATCH] = handle_watch,
79 };
80 EXPORT_SYMBOL_GPL(exception_table);
81
show_backtrace(struct task_struct * task,const struct pt_regs * regs,const char * loglvl,bool user)82 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs,
83 const char *loglvl, bool user)
84 {
85 unsigned long pc;
86 struct unwind_state state;
87 struct pt_regs *pregs = (struct pt_regs *)regs;
88
89 if (!task)
90 task = current;
91
92 unwind_start(&state, task, pregs);
93
94 #ifdef CONFIG_UNWINDER_PROLOGUE
95 if (user_mode(regs))
96 state.enable = false;
97 #endif
98
99 printk("%sCall Trace:\n", loglvl);
100 for (; !unwind_done(&state); unwind_next_frame(&state)) {
101 pc = unwind_get_return_address(&state);
102 print_ip_sym(loglvl, pc);
103 }
104 printk("%s\n", loglvl);
105 }
106
show_stacktrace(struct task_struct * task,const struct pt_regs * regs,const char * loglvl,bool user)107 static void show_stacktrace(struct task_struct *task,
108 const struct pt_regs *regs, const char *loglvl, bool user)
109 {
110 int i;
111 const int field = 2 * sizeof(unsigned long);
112 unsigned long stackdata;
113 unsigned long *sp = (unsigned long *)regs->regs[3];
114
115 printk("%sStack :", loglvl);
116 i = 0;
117 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
118 if (i && ((i % (64 / field)) == 0)) {
119 pr_cont("\n");
120 printk("%s ", loglvl);
121 }
122 if (i > 39) {
123 pr_cont(" ...");
124 break;
125 }
126
127 if (__get_addr(&stackdata, sp++, user)) {
128 pr_cont(" (Bad stack address)");
129 break;
130 }
131
132 pr_cont(" %0*lx", field, stackdata);
133 i++;
134 }
135 pr_cont("\n");
136 show_backtrace(task, regs, loglvl, user);
137 }
138
show_stack(struct task_struct * task,unsigned long * sp,const char * loglvl)139 void show_stack(struct task_struct *task, unsigned long *sp, const char *loglvl)
140 {
141 struct pt_regs regs;
142
143 regs.csr_crmd = 0;
144 if (sp) {
145 regs.csr_era = 0;
146 regs.regs[1] = 0;
147 regs.regs[3] = (unsigned long)sp;
148 } else {
149 if (!task || task == current)
150 prepare_frametrace(®s);
151 else {
152 regs.csr_era = task->thread.reg01;
153 regs.regs[1] = 0;
154 regs.regs[3] = task->thread.reg03;
155 regs.regs[22] = task->thread.reg22;
156 }
157 }
158
159 show_stacktrace(task, ®s, loglvl, false);
160 }
161
show_code(unsigned int * pc,bool user)162 static void show_code(unsigned int *pc, bool user)
163 {
164 long i;
165 unsigned int insn;
166
167 printk("Code:");
168
169 for(i = -3 ; i < 6 ; i++) {
170 if (__get_inst(&insn, pc + i, user)) {
171 pr_cont(" (Bad address in era)\n");
172 break;
173 }
174 pr_cont("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
175 }
176 pr_cont("\n");
177 }
178
print_bool_fragment(const char * key,unsigned long val,bool first)179 static void print_bool_fragment(const char *key, unsigned long val, bool first)
180 {
181 /* e.g. "+PG", "-DA" */
182 pr_cont("%s%c%s", first ? "" : " ", val ? '+' : '-', key);
183 }
184
print_plv_fragment(const char * key,int val)185 static void print_plv_fragment(const char *key, int val)
186 {
187 /* e.g. "PLV0", "PPLV3" */
188 pr_cont("%s%d", key, val);
189 }
190
print_memory_type_fragment(const char * key,unsigned long val)191 static void print_memory_type_fragment(const char *key, unsigned long val)
192 {
193 const char *humanized_type;
194
195 switch (val) {
196 case 0:
197 humanized_type = "SUC";
198 break;
199 case 1:
200 humanized_type = "CC";
201 break;
202 case 2:
203 humanized_type = "WUC";
204 break;
205 default:
206 pr_cont(" %s=Reserved(%lu)", key, val);
207 return;
208 }
209
210 /* e.g. " DATM=WUC" */
211 pr_cont(" %s=%s", key, humanized_type);
212 }
213
print_intr_fragment(const char * key,unsigned long val)214 static void print_intr_fragment(const char *key, unsigned long val)
215 {
216 /* e.g. "LIE=0-1,3,5-7" */
217 pr_cont("%s=%*pbl", key, EXCCODE_INT_NUM, &val);
218 }
219
print_crmd(unsigned long x)220 static void print_crmd(unsigned long x)
221 {
222 printk(" CRMD: %08lx (", x);
223 print_plv_fragment("PLV", (int) FIELD_GET(CSR_CRMD_PLV, x));
224 print_bool_fragment("IE", FIELD_GET(CSR_CRMD_IE, x), false);
225 print_bool_fragment("DA", FIELD_GET(CSR_CRMD_DA, x), false);
226 print_bool_fragment("PG", FIELD_GET(CSR_CRMD_PG, x), false);
227 print_memory_type_fragment("DACF", FIELD_GET(CSR_CRMD_DACF, x));
228 print_memory_type_fragment("DACM", FIELD_GET(CSR_CRMD_DACM, x));
229 print_bool_fragment("WE", FIELD_GET(CSR_CRMD_WE, x), false);
230 pr_cont(")\n");
231 }
232
print_prmd(unsigned long x)233 static void print_prmd(unsigned long x)
234 {
235 printk(" PRMD: %08lx (", x);
236 print_plv_fragment("PPLV", (int) FIELD_GET(CSR_PRMD_PPLV, x));
237 print_bool_fragment("PIE", FIELD_GET(CSR_PRMD_PIE, x), false);
238 print_bool_fragment("PWE", FIELD_GET(CSR_PRMD_PWE, x), false);
239 pr_cont(")\n");
240 }
241
print_euen(unsigned long x)242 static void print_euen(unsigned long x)
243 {
244 printk(" EUEN: %08lx (", x);
245 print_bool_fragment("FPE", FIELD_GET(CSR_EUEN_FPEN, x), true);
246 print_bool_fragment("SXE", FIELD_GET(CSR_EUEN_LSXEN, x), false);
247 print_bool_fragment("ASXE", FIELD_GET(CSR_EUEN_LASXEN, x), false);
248 print_bool_fragment("BTE", FIELD_GET(CSR_EUEN_LBTEN, x), false);
249 pr_cont(")\n");
250 }
251
print_ecfg(unsigned long x)252 static void print_ecfg(unsigned long x)
253 {
254 printk(" ECFG: %08lx (", x);
255 print_intr_fragment("LIE", FIELD_GET(CSR_ECFG_IM, x));
256 pr_cont(" VS=%d)\n", (int) FIELD_GET(CSR_ECFG_VS, x));
257 }
258
humanize_exc_name(unsigned int ecode,unsigned int esubcode)259 static const char *humanize_exc_name(unsigned int ecode, unsigned int esubcode)
260 {
261 /*
262 * LoongArch users and developers are probably more familiar with
263 * those names found in the ISA manual, so we are going to print out
264 * the latter. This will require some mapping.
265 */
266 switch (ecode) {
267 case EXCCODE_RSV: return "INT";
268 case EXCCODE_TLBL: return "PIL";
269 case EXCCODE_TLBS: return "PIS";
270 case EXCCODE_TLBI: return "PIF";
271 case EXCCODE_TLBM: return "PME";
272 case EXCCODE_TLBNR: return "PNR";
273 case EXCCODE_TLBNX: return "PNX";
274 case EXCCODE_TLBPE: return "PPI";
275 case EXCCODE_ADE:
276 switch (esubcode) {
277 case EXSUBCODE_ADEF: return "ADEF";
278 case EXSUBCODE_ADEM: return "ADEM";
279 }
280 break;
281 case EXCCODE_ALE: return "ALE";
282 case EXCCODE_BCE: return "BCE";
283 case EXCCODE_SYS: return "SYS";
284 case EXCCODE_BP: return "BRK";
285 case EXCCODE_INE: return "INE";
286 case EXCCODE_IPE: return "IPE";
287 case EXCCODE_FPDIS: return "FPD";
288 case EXCCODE_LSXDIS: return "SXD";
289 case EXCCODE_LASXDIS: return "ASXD";
290 case EXCCODE_FPE:
291 switch (esubcode) {
292 case EXCSUBCODE_FPE: return "FPE";
293 case EXCSUBCODE_VFPE: return "VFPE";
294 }
295 break;
296 case EXCCODE_WATCH:
297 switch (esubcode) {
298 case EXCSUBCODE_WPEF: return "WPEF";
299 case EXCSUBCODE_WPEM: return "WPEM";
300 }
301 break;
302 case EXCCODE_BTDIS: return "BTD";
303 case EXCCODE_BTE: return "BTE";
304 case EXCCODE_GSPR: return "GSPR";
305 case EXCCODE_HVC: return "HVC";
306 case EXCCODE_GCM:
307 switch (esubcode) {
308 case EXCSUBCODE_GCSC: return "GCSC";
309 case EXCSUBCODE_GCHC: return "GCHC";
310 }
311 break;
312 /*
313 * The manual did not mention the EXCCODE_SE case, but print out it
314 * nevertheless.
315 */
316 case EXCCODE_SE: return "SE";
317 }
318
319 return "???";
320 }
321
print_estat(unsigned long x)322 static void print_estat(unsigned long x)
323 {
324 unsigned int ecode = FIELD_GET(CSR_ESTAT_EXC, x);
325 unsigned int esubcode = FIELD_GET(CSR_ESTAT_ESUBCODE, x);
326
327 printk("ESTAT: %08lx [%s] (", x, humanize_exc_name(ecode, esubcode));
328 print_intr_fragment("IS", FIELD_GET(CSR_ESTAT_IS, x));
329 pr_cont(" ECode=%d EsubCode=%d)\n", (int) ecode, (int) esubcode);
330 }
331
__show_regs(const struct pt_regs * regs)332 static void __show_regs(const struct pt_regs *regs)
333 {
334 const int field = 2 * sizeof(unsigned long);
335 unsigned int exccode = FIELD_GET(CSR_ESTAT_EXC, regs->csr_estat);
336
337 show_regs_print_info(KERN_DEFAULT);
338
339 /* Print saved GPRs except $zero (substituting with PC/ERA) */
340 #define GPR_FIELD(x) field, regs->regs[x]
341 printk("pc %0*lx ra %0*lx tp %0*lx sp %0*lx\n",
342 field, regs->csr_era, GPR_FIELD(1), GPR_FIELD(2), GPR_FIELD(3));
343 printk("a0 %0*lx a1 %0*lx a2 %0*lx a3 %0*lx\n",
344 GPR_FIELD(4), GPR_FIELD(5), GPR_FIELD(6), GPR_FIELD(7));
345 printk("a4 %0*lx a5 %0*lx a6 %0*lx a7 %0*lx\n",
346 GPR_FIELD(8), GPR_FIELD(9), GPR_FIELD(10), GPR_FIELD(11));
347 printk("t0 %0*lx t1 %0*lx t2 %0*lx t3 %0*lx\n",
348 GPR_FIELD(12), GPR_FIELD(13), GPR_FIELD(14), GPR_FIELD(15));
349 printk("t4 %0*lx t5 %0*lx t6 %0*lx t7 %0*lx\n",
350 GPR_FIELD(16), GPR_FIELD(17), GPR_FIELD(18), GPR_FIELD(19));
351 printk("t8 %0*lx u0 %0*lx s9 %0*lx s0 %0*lx\n",
352 GPR_FIELD(20), GPR_FIELD(21), GPR_FIELD(22), GPR_FIELD(23));
353 printk("s1 %0*lx s2 %0*lx s3 %0*lx s4 %0*lx\n",
354 GPR_FIELD(24), GPR_FIELD(25), GPR_FIELD(26), GPR_FIELD(27));
355 printk("s5 %0*lx s6 %0*lx s7 %0*lx s8 %0*lx\n",
356 GPR_FIELD(28), GPR_FIELD(29), GPR_FIELD(30), GPR_FIELD(31));
357
358 /* The slot for $zero is reused as the syscall restart flag */
359 if (regs->regs[0])
360 printk("syscall restart flag: %0*lx\n", GPR_FIELD(0));
361
362 if (user_mode(regs)) {
363 printk(" ra: %0*lx\n", GPR_FIELD(1));
364 printk(" ERA: %0*lx\n", field, regs->csr_era);
365 } else {
366 printk(" ra: %0*lx %pS\n", GPR_FIELD(1), (void *) regs->regs[1]);
367 printk(" ERA: %0*lx %pS\n", field, regs->csr_era, (void *) regs->csr_era);
368 }
369 #undef GPR_FIELD
370
371 /* Print saved important CSRs */
372 print_crmd(regs->csr_crmd);
373 print_prmd(regs->csr_prmd);
374 print_euen(regs->csr_euen);
375 print_ecfg(regs->csr_ecfg);
376 print_estat(regs->csr_estat);
377
378 if (exccode >= EXCCODE_TLBL && exccode <= EXCCODE_ALE)
379 printk(" BADV: %0*lx\n", field, regs->csr_badvaddr);
380
381 printk(" PRID: %08x (%s, %s)\n", read_cpucfg(LOONGARCH_CPUCFG0),
382 cpu_family_string(), cpu_full_name_string());
383 }
384
show_regs(struct pt_regs * regs)385 void show_regs(struct pt_regs *regs)
386 {
387 __show_regs((struct pt_regs *)regs);
388 dump_stack();
389 }
390
show_registers(struct pt_regs * regs)391 void show_registers(struct pt_regs *regs)
392 {
393 __show_regs(regs);
394 print_modules();
395 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
396 current->comm, current->pid, current_thread_info(), current);
397
398 show_stacktrace(current, regs, KERN_DEFAULT, user_mode(regs));
399 show_code((void *)regs->csr_era, user_mode(regs));
400 printk("\n");
401 }
402
403 static DEFINE_RAW_SPINLOCK(die_lock);
404
die(const char * str,struct pt_regs * regs)405 void __noreturn die(const char *str, struct pt_regs *regs)
406 {
407 static int die_counter;
408 int sig = SIGSEGV;
409
410 oops_enter();
411
412 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr,
413 SIGSEGV) == NOTIFY_STOP)
414 sig = 0;
415
416 console_verbose();
417 raw_spin_lock_irq(&die_lock);
418 bust_spinlocks(1);
419
420 printk("%s[#%d]:\n", str, ++die_counter);
421 show_registers(regs);
422 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
423 raw_spin_unlock_irq(&die_lock);
424
425 oops_exit();
426
427 if (regs && kexec_should_crash(current))
428 crash_kexec(regs);
429
430 if (in_interrupt())
431 panic("Fatal exception in interrupt");
432
433 if (panic_on_oops)
434 panic("Fatal exception");
435
436 do_exit(sig);
437 }
438
setup_vint_size(unsigned int size)439 static inline void setup_vint_size(unsigned int size)
440 {
441 unsigned int vs;
442
443 vs = ilog2(size/4);
444
445 if(vs == 0 || vs > 7)
446 panic("vint_size %d Not support yet", vs);
447
448 csr_xchg32(vs<<CSR_ECFG_VS_SHIFT, CSR_ECFG_VS, LOONGARCH_CSR_ECFG);
449 }
450
451 /*
452 * Send SIGFPE according to FCSR Cause bits, which must have already
453 * been masked against Enable bits. This is impotant as Inexact can
454 * happen together with Overflow or Underflow, and `ptrace' can set
455 * any bits.
456 */
force_fcsr_sig(unsigned long fcsr,void __user * fault_addr,struct task_struct * tsk)457 static void force_fcsr_sig(unsigned long fcsr,
458 void __user *fault_addr, struct task_struct *tsk)
459 {
460 int si_code = FPE_FLTUNK;
461
462 if (fcsr & FPU_CSR_INV_X)
463 si_code = FPE_FLTINV;
464 else if (fcsr & FPU_CSR_DIV_X)
465 si_code = FPE_FLTDIV;
466 else if (fcsr & FPU_CSR_OVF_X)
467 si_code = FPE_FLTOVF;
468 else if (fcsr & FPU_CSR_UDF_X)
469 si_code = FPE_FLTUND;
470 else if (fcsr & FPU_CSR_INE_X)
471 si_code = FPE_FLTRES;
472
473 force_sig_fault(SIGFPE, si_code, fault_addr);
474 }
475
process_fpemu_return(int sig,void __user * fault_addr,unsigned long fcsr)476 static int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcsr)
477 {
478 int si_code;
479 struct vm_area_struct *vma;
480
481 switch (sig) {
482 case 0:
483 return 0;
484
485 case SIGFPE:
486 force_fcsr_sig(fcsr, fault_addr, current);
487 return 1;
488
489 case SIGBUS:
490 force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr);
491 return 1;
492
493 case SIGSEGV:
494 mmap_read_lock(current->mm);
495 vma = find_vma(current->mm, (unsigned long)fault_addr);
496 if (vma && (vma->vm_start <= (unsigned long)fault_addr))
497 si_code = SEGV_ACCERR;
498 else
499 si_code = SEGV_MAPERR;
500 mmap_read_unlock(current->mm);
501 force_sig_fault(SIGSEGV, si_code, fault_addr);
502 return 1;
503
504 default:
505 force_sig(sig);
506 return 1;
507 }
508 }
509
510 /*
511 * Delayed fp exceptions when doing a lazy ctx switch
512 */
do_fpe(struct pt_regs * regs,unsigned long fcsr)513 asmlinkage void noinstr do_fpe(struct pt_regs *regs, unsigned long fcsr)
514 {
515 int sig;
516 void __user *fault_addr;
517 irqentry_state_t state = irqentry_enter(regs);
518
519 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr,
520 SIGFPE) == NOTIFY_STOP)
521 goto out;
522
523 /* Clear FCSR.Cause before enabling interrupts */
524 write_fcsr(LOONGARCH_FCSR0, fcsr & ~mask_fcsr_x(fcsr));
525 local_irq_enable();
526
527 die_if_kernel("FP exception in kernel code", regs);
528
529 sig = SIGFPE;
530 fault_addr = (void __user *) regs->csr_era;
531
532 /* Send a signal if required. */
533 process_fpemu_return(sig, fault_addr, fcsr);
534
535 out:
536 local_irq_disable();
537 irqentry_exit(regs, state);
538 }
539
do_ade(struct pt_regs * regs)540 asmlinkage void noinstr do_ade(struct pt_regs *regs)
541 {
542 irqentry_state_t state = irqentry_enter(regs);
543
544 die_if_kernel("Kernel ade access", regs);
545 force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)regs->csr_badvaddr);
546
547 irqentry_exit(regs, state);
548 }
549
550 /* sysctl hooks */
551 int unaligned_enabled __read_mostly = 1; /* Enabled by default */
552 int no_unaligned_warning __read_mostly = 1; /* Only 1 warning by default */
553
do_ale(struct pt_regs * regs)554 asmlinkage void noinstr do_ale(struct pt_regs *regs)
555 {
556 irqentry_state_t state = irqentry_enter(regs);
557
558 #ifndef CONFIG_ARCH_STRICT_ALIGN
559 die_if_kernel("Kernel ale access", regs);
560 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)regs->csr_badvaddr);
561 #else
562 unsigned int *pc;
563
564 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, regs->csr_badvaddr);
565
566 /*
567 * Did we catch a fault trying to load an instruction?
568 */
569 if (regs->csr_badvaddr == regs->csr_era)
570 goto sigbus;
571 if (user_mode(regs) && !test_thread_flag(TIF_FIXADE))
572 goto sigbus;
573 if (!unaligned_enabled)
574 goto sigbus;
575 if (!no_unaligned_warning)
576 show_registers(regs);
577
578 pc = (unsigned int *)exception_era(regs);
579
580 emulate_load_store_insn(regs, (void __user *)regs->csr_badvaddr, pc);
581
582 goto out;
583
584 sigbus:
585 die_if_kernel("Kernel ale access", regs);
586 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)regs->csr_badvaddr);
587 out:
588 #endif
589 irqentry_exit(regs, state);
590 }
591
592 #ifdef CONFIG_GENERIC_BUG
is_valid_bugaddr(unsigned long addr)593 int is_valid_bugaddr(unsigned long addr)
594 {
595 return 1;
596 }
597 #endif /* CONFIG_GENERIC_BUG */
598
bug_handler(struct pt_regs * regs)599 static void bug_handler(struct pt_regs *regs)
600 {
601 switch (report_bug(regs->csr_era, regs)) {
602 case BUG_TRAP_TYPE_BUG:
603 case BUG_TRAP_TYPE_NONE:
604 die_if_kernel("Oops - BUG", regs);
605 force_sig(SIGTRAP);
606 break;
607
608 case BUG_TRAP_TYPE_WARN:
609 /* Skip the BUG instruction and continue */
610 regs->csr_era += LOONGARCH_INSN_SIZE;
611 break;
612 }
613 }
614
do_bce(struct pt_regs * regs)615 asmlinkage void noinstr do_bce(struct pt_regs *regs)
616 {
617 bool user = user_mode(regs);
618 unsigned long era = exception_era(regs);
619 u64 badv = 0, lower = 0, upper = ULONG_MAX;
620 union loongarch_instruction insn;
621 irqentry_state_t state = irqentry_enter(regs);
622
623 if (regs->csr_prmd & CSR_PRMD_PIE)
624 local_irq_enable();
625
626 current->thread.trap_nr = read_csr_excode();
627
628 die_if_kernel("Bounds check error in kernel code", regs);
629
630 /*
631 * Pull out the address that failed bounds checking, and the lower /
632 * upper bound, by minimally looking at the faulting instruction word
633 * and reading from the correct register.
634 */
635 if (__get_inst(&insn.word, (u32 *)era, user))
636 goto bad_era;
637
638 switch (insn.reg3_format.opcode) {
639 case asrtled_op:
640 if (insn.reg3_format.rd != 0)
641 break; /* not asrtle */
642 badv = regs->regs[insn.reg3_format.rj];
643 upper = regs->regs[insn.reg3_format.rk];
644 break;
645
646 case asrtgtd_op:
647 if (insn.reg3_format.rd != 0)
648 break; /* not asrtgt */
649 badv = regs->regs[insn.reg3_format.rj];
650 lower = regs->regs[insn.reg3_format.rk];
651 break;
652
653 case ldleb_op:
654 case ldleh_op:
655 case ldlew_op:
656 case ldled_op:
657 case stleb_op:
658 case stleh_op:
659 case stlew_op:
660 case stled_op:
661 case fldles_op:
662 case fldled_op:
663 case fstles_op:
664 case fstled_op:
665 badv = regs->regs[insn.reg3_format.rj];
666 upper = regs->regs[insn.reg3_format.rk];
667 break;
668
669 case ldgtb_op:
670 case ldgth_op:
671 case ldgtw_op:
672 case ldgtd_op:
673 case stgtb_op:
674 case stgth_op:
675 case stgtw_op:
676 case stgtd_op:
677 case fldgts_op:
678 case fldgtd_op:
679 case fstgts_op:
680 case fstgtd_op:
681 badv = regs->regs[insn.reg3_format.rj];
682 lower = regs->regs[insn.reg3_format.rk];
683 break;
684 }
685
686 force_sig_bnderr((void __user *)badv, (void __user *)lower, (void __user *)upper);
687
688 out:
689 if (regs->csr_prmd & CSR_PRMD_PIE)
690 local_irq_disable();
691
692 irqentry_exit(regs, state);
693 return;
694
695 bad_era:
696 /*
697 * Cannot pull out the instruction word, hence cannot provide more
698 * info than a regular SIGSEGV in this case.
699 */
700 force_sig(SIGSEGV);
701 goto out;
702 }
703
do_bp(struct pt_regs * regs)704 asmlinkage void noinstr do_bp(struct pt_regs *regs)
705 {
706 bool user = user_mode(regs);
707 unsigned int opcode, bcode;
708 unsigned long era = exception_era(regs);
709 irqentry_state_t state = irqentry_enter(regs);
710
711 local_irq_enable();
712 current->thread.trap_nr = read_csr_excode();
713 if (__get_inst(&opcode, (u32 *)era, user))
714 goto out_sigsegv;
715
716 bcode = (opcode & 0x7fff);
717
718 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
719 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr,
720 SIGTRAP) == NOTIFY_STOP)
721 return;
722 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
723
724 /*
725 * notify the kprobe handlers, if instruction is likely to
726 * pertain to them.
727 */
728 switch (bcode) {
729 case BRK_KPROBE_BP:
730 if (notify_die(DIE_BREAK, "Kprobe", regs, bcode,
731 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
732 goto out;
733 else
734 break;
735 case BRK_KPROBE_SSTEPBP:
736 if (notify_die(DIE_SSTEPBP, "Kprobe_SingleStep", regs, bcode,
737 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
738 goto out;
739 else
740 break;
741 case BRK_UPROBE_BP:
742 if (notify_die(DIE_UPROBE, "Uprobe", regs, bcode,
743 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
744 goto out;
745 else
746 break;
747 case BRK_UPROBE_XOLBP:
748 if (notify_die(DIE_UPROBE_XOL, "Uprobe_XOL", regs, bcode,
749 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
750 goto out;
751 else
752 break;
753 default:
754 if (notify_die(DIE_TRAP, "Break", regs, bcode,
755 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
756 goto out;
757 else
758 break;
759 }
760
761 switch (bcode) {
762 case BRK_BUG:
763 bug_handler(regs);
764 break;
765 case BRK_DIVZERO:
766 die_if_kernel("Break instruction in kernel code", regs);
767 force_sig_fault(SIGFPE, FPE_INTDIV, (void __user *)regs->csr_era);
768 break;
769 case BRK_OVERFLOW:
770 die_if_kernel("Break instruction in kernel code", regs);
771 force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->csr_era);
772 break;
773 default:
774 die_if_kernel("Break instruction in kernel code", regs);
775 force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)regs->csr_era);
776 break;
777 }
778
779 out:
780 local_irq_disable();
781 irqentry_exit(regs, state);
782 return;
783
784 out_sigsegv:
785 force_sig(SIGSEGV);
786 goto out;
787 }
788
do_watch(struct pt_regs * regs)789 asmlinkage void noinstr do_watch(struct pt_regs *regs)
790 {
791 int i;
792 siginfo_t info;
793 irqentry_state_t state = irqentry_enter(regs);
794 struct loongarch_watch_reg_state *watches = ¤t->thread.watch;
795
796 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
797 loongarch_read_watch_registers(regs);
798 for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
799 if ((watch_csrrd(LOONGARCH_CSR_MWPS) & (0x1 << i))) {
800 info.si_addr = (void __user *)watches->addr[i];
801 watch_csrwr(0x1 << i, LOONGARCH_CSR_MWPS);
802 }
803 }
804 force_sig_fault(SIGTRAP, TRAP_HWBKPT, info.si_addr);
805 } else if (test_tsk_thread_flag(current, TIF_SINGLESTEP)) {
806 int llbit = (csr_read32(LOONGARCH_CSR_LLBCTL) & 0x1);
807 unsigned long pc = regs->csr_era;
808
809 if (llbit) {
810 csr_write32(0x10000, LOONGARCH_CSR_FWPS);
811 csr_write32(0x4, LOONGARCH_CSR_LLBCTL);
812 } else if (pc == current->thread.single_step) {
813 csr_write32(0x10000, LOONGARCH_CSR_FWPS);
814 } else {
815 loongarch_read_watch_registers(regs);
816 force_sig(SIGTRAP);
817 }
818 } else {
819 if (notify_die(DIE_TRAP, "Break", regs, 0,
820 current->thread.trap_nr, SIGTRAP) != NOTIFY_STOP)
821 loongarch_clear_watch_registers();
822 }
823
824 irqentry_exit(regs, state);
825 }
826
do_ri(struct pt_regs * regs)827 asmlinkage void noinstr do_ri(struct pt_regs *regs)
828 {
829 int status = SIGILL;
830 unsigned int __maybe_unused opcode;
831 unsigned int __user *era = (unsigned int __user *)exception_era(regs);
832 irqentry_state_t state = irqentry_enter(regs);
833
834 local_irq_enable();
835 current->thread.trap_nr = read_csr_excode();
836
837 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
838 SIGILL) == NOTIFY_STOP)
839 goto out;
840
841 die_if_kernel("Reserved instruction in kernel code", regs);
842
843 if (unlikely(get_user(opcode, era) < 0)) {
844 status = SIGSEGV;
845 current->thread.error_code = 1;
846 }
847
848 force_sig(status);
849
850 out:
851 local_irq_disable();
852 irqentry_exit(regs, state);
853 }
854
init_restore_fp(void)855 static void init_restore_fp(void)
856 {
857 if (!used_math()) {
858 /* First time FP context user. */
859 init_fpu();
860 } else {
861 /* This task has formerly used the FP context */
862 if (!is_fpu_owner())
863 own_fpu_inatomic(1);
864 }
865
866 BUG_ON(!is_fp_enabled());
867 }
868
init_restore_lsx(void)869 static void init_restore_lsx(void)
870 {
871 enable_lsx();
872
873 if (!thread_lsx_context_live()) {
874 /* First time LSX context user */
875 init_restore_fp();
876 init_lsx_upper();
877 set_thread_flag(TIF_LSX_CTX_LIVE);
878 } else {
879 if (!is_simd_owner()) {
880 if (is_fpu_owner()) {
881 restore_lsx_upper(current);
882 } else {
883 __own_fpu();
884 restore_lsx(current);
885 }
886 }
887 }
888
889 set_thread_flag(TIF_USEDSIMD);
890
891 BUG_ON(!is_fp_enabled());
892 BUG_ON(!is_lsx_enabled());
893 }
894
init_restore_lasx(void)895 static void init_restore_lasx(void)
896 {
897 enable_lasx();
898
899 if (!thread_lasx_context_live()) {
900 /* First time LASX context user */
901 init_restore_lsx();
902 init_lasx_upper();
903 set_thread_flag(TIF_LASX_CTX_LIVE);
904 } else {
905 if (is_fpu_owner() || is_simd_owner()) {
906 init_restore_lsx();
907 restore_lasx_upper(current);
908 } else {
909 __own_fpu();
910 enable_lsx();
911 restore_lasx(current);
912 }
913 }
914
915 set_thread_flag(TIF_USEDSIMD);
916
917 BUG_ON(!is_fp_enabled());
918 BUG_ON(!is_lsx_enabled());
919 BUG_ON(!is_lasx_enabled());
920 }
921
do_fpu(struct pt_regs * regs)922 asmlinkage void noinstr do_fpu(struct pt_regs *regs)
923 {
924 irqentry_state_t state = irqentry_enter(regs);
925
926 local_irq_enable();
927 die_if_kernel("do_fpu invoked from kernel context!", regs);
928 BUG_ON(is_lsx_enabled());
929 BUG_ON(is_lasx_enabled());
930
931 preempt_disable();
932 init_restore_fp();
933 preempt_enable();
934
935 local_irq_disable();
936 irqentry_exit(regs, state);
937 }
938
do_lsx(struct pt_regs * regs)939 asmlinkage void noinstr do_lsx(struct pt_regs *regs)
940 {
941 irqentry_state_t state = irqentry_enter(regs);
942
943 local_irq_enable();
944 if (!cpu_has_lsx) {
945 force_sig(SIGILL);
946 goto out;
947 }
948
949 die_if_kernel("do_lsx invoked from kernel context!", regs);
950 BUG_ON(is_lasx_enabled());
951
952 preempt_disable();
953 init_restore_lsx();
954 preempt_enable();
955
956 out:
957 local_irq_disable();
958 irqentry_exit(regs, state);
959 }
960
do_lasx(struct pt_regs * regs)961 asmlinkage void noinstr do_lasx(struct pt_regs *regs)
962 {
963 irqentry_state_t state = irqentry_enter(regs);
964
965 local_irq_enable();
966 if (!cpu_has_lasx) {
967 force_sig(SIGILL);
968 goto out;
969 }
970
971 die_if_kernel("do_lasx invoked from kernel context!", regs);
972
973 preempt_disable();
974 init_restore_lasx();
975 preempt_enable();
976
977 out:
978 local_irq_disable();
979 irqentry_exit(regs, state);
980 }
981
init_restore_lbt(void)982 static void init_restore_lbt(void)
983 {
984 if (!thread_lbt_context_live()) {
985 /* First lbt context user */
986 init_lbt();
987 set_thread_flag(TIF_LBT_CTX_LIVE);
988 } else {
989 /* Enable and restore */
990 own_lbt_inatomic(1);
991 }
992 }
993
do_lbt(struct pt_regs * regs)994 asmlinkage void noinstr do_lbt(struct pt_regs *regs)
995 {
996 irqentry_state_t state = irqentry_enter(regs);
997
998 if (regs->csr_prmd & CSR_PRMD_PIE)
999 local_irq_enable();
1000
1001 if (!cpu_has_lbt) {
1002 force_sig(SIGILL);
1003 goto out;
1004 }
1005
1006 preempt_disable();
1007 init_restore_lbt();
1008 preempt_enable();
1009
1010 out:
1011 if (regs->csr_prmd & CSR_PRMD_PIE)
1012 local_irq_disable();
1013
1014 irqentry_exit(regs, state);
1015 }
1016
do_reserved(struct pt_regs * regs)1017 asmlinkage void noinstr do_reserved(struct pt_regs *regs)
1018 {
1019 irqentry_state_t state = irqentry_enter(regs);
1020
1021 local_irq_enable();
1022 /*
1023 * Game over - no way to handle this if it ever occurs. Most probably
1024 * caused by a fatal error after another hardware/software error.
1025 */
1026 pr_err("Caught reserved exception %u on pid:%d [%s] - should not happen\n",
1027 read_csr_excode(), current->pid, current->comm);
1028 die_if_kernel("do_reserved exception", regs);
1029 force_sig(SIGUNUSED);
1030
1031 local_irq_disable();
1032 irqentry_exit(regs, state);
1033 }
1034
cache_parity_error(void)1035 asmlinkage void cache_parity_error(void)
1036 {
1037 /* For the moment, report the problem and hang. */
1038 printk("Cache error exception:\n");
1039 printk("csr_merrctl == %08x\n", csr_read32(LOONGARCH_CSR_MERRCTL));
1040 printk("csr_merrera == %016lx\n", csr_read64(LOONGARCH_CSR_MERRERA));
1041 panic("Can't handle the cache error!");
1042 }
1043
do_vint(struct pt_regs * regs,unsigned long sp)1044 asmlinkage void noinstr do_vint(struct pt_regs *regs, unsigned long sp)
1045 {
1046 register int cpu;
1047 register unsigned long stack;
1048 irqentry_state_t state = irqentry_enter(regs);
1049
1050 cpu = smp_processor_id();
1051
1052 if (on_irq_stack(cpu, sp))
1053 handle_arch_irq(regs);
1054 else {
1055 stack = per_cpu(irq_stack, cpu) + IRQ_STACK_START;
1056
1057 /* Save task's sp on IRQ stack for unwinding */
1058 *(unsigned long *)stack = sp;
1059
1060 __asm__ __volatile__(
1061 "move $s0, $sp \n" /* Preserve sp */
1062 "move $sp, %[stk] \n" /* Switch stack */
1063 "move $a0, %[regs] \n"
1064 "la $t0, handle_arch_irq \n"
1065 "ld.d $t1, $t0, 0 \n"
1066 "jirl $ra, $t1, 0 \n"
1067 "move $sp, $s0 \n" /* Restore sp */
1068 : /* No outputs */
1069 : [stk] "r" (stack), [regs] "r" (regs)
1070 : "$a0", "$a1", "$a2", "$a3", "$a4", "$a5", "$a6", "$a7", "$s0",
1071 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", "$t8",
1072 "memory");
1073 }
1074
1075 irqentry_exit(regs, state);
1076 }
1077
1078 unsigned long eentry;
1079 EXPORT_SYMBOL_GPL(eentry);
1080 unsigned long tlbrentry;
1081 EXPORT_SYMBOL_GPL(tlbrentry);
1082
1083 long exception_handlers[VECSIZE * 128 / sizeof(long)] __aligned(SZ_64K);
1084
configure_exception_vector(void)1085 static void configure_exception_vector(void)
1086 {
1087 eentry = (unsigned long)exception_handlers;
1088 tlbrentry = (unsigned long)exception_handlers + 80*VECSIZE;
1089
1090 csr_write64(eentry, LOONGARCH_CSR_EENTRY);
1091 csr_write64(eentry, LOONGARCH_CSR_MERRENTRY);
1092 csr_write64(tlbrentry, LOONGARCH_CSR_TLBRENTRY);
1093 }
1094
per_cpu_trap_init(int cpu)1095 void per_cpu_trap_init(int cpu)
1096 {
1097 unsigned int i;
1098
1099 setup_vint_size(VECSIZE);
1100
1101 configure_exception_vector();
1102
1103 if (!cpu_data[cpu].asid_cache)
1104 cpu_data[cpu].asid_cache = asid_first_version(cpu);
1105
1106 mmgrab(&init_mm);
1107 current->active_mm = &init_mm;
1108 BUG_ON(current->mm);
1109 enter_lazy_tlb(&init_mm, current);
1110
1111 /* Initialise exception handlers */
1112 if (cpu == 0)
1113 for (i = 0; i < 64; i++)
1114 set_handler(i * VECSIZE, handle_reserved, VECSIZE);
1115
1116 tlb_init(cpu);
1117 cpu_cache_init();
1118 }
1119
1120 /* Install CPU exception handler */
set_handler(unsigned long offset,void * addr,unsigned long size)1121 void set_handler(unsigned long offset, void *addr, unsigned long size)
1122 {
1123 memcpy((void *)(eentry + offset), addr, size);
1124 local_flush_icache_range(eentry + offset, eentry + offset + size);
1125 }
1126
1127 static const char panic_null_cerr[] =
1128 "Trying to set NULL cache error exception handler\n";
1129
1130 /*
1131 * Install uncached CPU exception handler.
1132 * This is suitable only for the cache error exception which is the only
1133 * exception handler that is being run uncached.
1134 */
set_merr_handler(unsigned long offset,void * addr,unsigned long size)1135 void set_merr_handler(unsigned long offset, void *addr, unsigned long size)
1136 {
1137 unsigned long uncached_eentry = TO_UNCACHE(__pa(eentry));
1138
1139 if (!addr)
1140 panic(panic_null_cerr);
1141
1142 memcpy((void *)(uncached_eentry + offset), addr, size);
1143 }
1144
trap_init(void)1145 void __init trap_init(void)
1146 {
1147 long i;
1148
1149 /* Set interrupt vector handler */
1150 for (i = EXCCODE_INT_START; i <= EXCCODE_INT_END; i++)
1151 set_handler(i * VECSIZE, handle_vint, VECSIZE);
1152
1153 for (i = EXCCODE_ADE; i <= EXCCODE_BTDIS; i++)
1154 set_handler(i * VECSIZE, exception_table[i], VECSIZE);
1155
1156 cache_error_setup();
1157
1158 local_flush_icache_range(eentry, eentry + 0x400);
1159 }
1160