1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Silicon Labs Si5340, Si5341, Si5342, Si5344 and Si5345
4 * Copyright (C) 2019 Topic Embedded Products
5 * Author: Mike Looijmans <mike.looijmans@topic.nl>
6 *
7 * The Si5341 has 10 outputs and 5 synthesizers.
8 * The Si5340 is a smaller version of the Si5341 with only 4 outputs.
9 * The Si5345 is similar to the Si5341, with the addition of fractional input
10 * dividers and automatic input selection.
11 * The Si5342 and Si5344 are smaller versions of the Si5345.
12 */
13
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
16 #include <linux/delay.h>
17 #include <linux/gcd.h>
18 #include <linux/math64.h>
19 #include <linux/i2c.h>
20 #include <linux/module.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <asm/unaligned.h>
25
26 #define SI5341_NUM_INPUTS 4
27
28 #define SI5340_MAX_NUM_OUTPUTS 4
29 #define SI5341_MAX_NUM_OUTPUTS 10
30 #define SI5342_MAX_NUM_OUTPUTS 2
31 #define SI5344_MAX_NUM_OUTPUTS 4
32 #define SI5345_MAX_NUM_OUTPUTS 10
33
34 #define SI5340_NUM_SYNTH 4
35 #define SI5341_NUM_SYNTH 5
36 #define SI5342_NUM_SYNTH 2
37 #define SI5344_NUM_SYNTH 4
38 #define SI5345_NUM_SYNTH 5
39
40 /* Range of the synthesizer fractional divider */
41 #define SI5341_SYNTH_N_MIN 10
42 #define SI5341_SYNTH_N_MAX 4095
43
44 /* The chip can get its input clock from 3 input pins or an XTAL */
45
46 /* There is one PLL running at 13500–14256 MHz */
47 #define SI5341_PLL_VCO_MIN 13500000000ull
48 #define SI5341_PLL_VCO_MAX 14256000000ull
49
50 /* The 5 frequency synthesizers obtain their input from the PLL */
51 struct clk_si5341_synth {
52 struct clk_hw hw;
53 struct clk_si5341 *data;
54 u8 index;
55 };
56 #define to_clk_si5341_synth(_hw) \
57 container_of(_hw, struct clk_si5341_synth, hw)
58
59 /* The output stages can be connected to any synth (full mux) */
60 struct clk_si5341_output {
61 struct clk_hw hw;
62 struct clk_si5341 *data;
63 struct regulator *vddo_reg;
64 u8 index;
65 };
66 #define to_clk_si5341_output(_hw) \
67 container_of(_hw, struct clk_si5341_output, hw)
68
69 struct clk_si5341 {
70 struct clk_hw hw;
71 struct regmap *regmap;
72 struct i2c_client *i2c_client;
73 struct clk_si5341_synth synth[SI5341_NUM_SYNTH];
74 struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS];
75 struct clk *input_clk[SI5341_NUM_INPUTS];
76 const char *input_clk_name[SI5341_NUM_INPUTS];
77 const u16 *reg_output_offset;
78 const u16 *reg_rdiv_offset;
79 u64 freq_vco; /* 13500–14256 MHz */
80 u8 num_outputs;
81 u8 num_synth;
82 u16 chip_id;
83 };
84 #define to_clk_si5341(_hw) container_of(_hw, struct clk_si5341, hw)
85
86 struct clk_si5341_output_config {
87 u8 out_format_drv_bits;
88 u8 out_cm_ampl_bits;
89 u8 vdd_sel_bits;
90 bool synth_master;
91 bool always_on;
92 };
93
94 #define SI5341_PAGE 0x0001
95 #define SI5341_PN_BASE 0x0002
96 #define SI5341_DEVICE_REV 0x0005
97 #define SI5341_STATUS 0x000C
98 #define SI5341_LOS 0x000D
99 #define SI5341_STATUS_STICKY 0x0011
100 #define SI5341_LOS_STICKY 0x0012
101 #define SI5341_SOFT_RST 0x001C
102 #define SI5341_IN_SEL 0x0021
103 #define SI5341_DEVICE_READY 0x00FE
104 #define SI5341_XAXB_CFG 0x090E
105 #define SI5341_IN_EN 0x0949
106 #define SI5341_INX_TO_PFD_EN 0x094A
107
108 /* Status bits */
109 #define SI5341_STATUS_SYSINCAL BIT(0)
110 #define SI5341_STATUS_LOSXAXB BIT(1)
111 #define SI5341_STATUS_LOSREF BIT(2)
112 #define SI5341_STATUS_LOL BIT(3)
113
114 /* Input selection */
115 #define SI5341_IN_SEL_MASK 0x06
116 #define SI5341_IN_SEL_SHIFT 1
117 #define SI5341_IN_SEL_REGCTRL 0x01
118 #define SI5341_INX_TO_PFD_SHIFT 4
119
120 /* XTAL config bits */
121 #define SI5341_XAXB_CFG_EXTCLK_EN BIT(0)
122 #define SI5341_XAXB_CFG_PDNB BIT(1)
123
124 /* Input dividers (48-bit) */
125 #define SI5341_IN_PDIV(x) (0x0208 + ((x) * 10))
126 #define SI5341_IN_PSET(x) (0x020E + ((x) * 10))
127 #define SI5341_PX_UPD 0x0230
128
129 /* PLL configuration */
130 #define SI5341_PLL_M_NUM 0x0235
131 #define SI5341_PLL_M_DEN 0x023B
132
133 /* Output configuration */
134 #define SI5341_OUT_CONFIG(output) \
135 ((output)->data->reg_output_offset[(output)->index])
136 #define SI5341_OUT_FORMAT(output) (SI5341_OUT_CONFIG(output) + 1)
137 #define SI5341_OUT_CM(output) (SI5341_OUT_CONFIG(output) + 2)
138 #define SI5341_OUT_MUX_SEL(output) (SI5341_OUT_CONFIG(output) + 3)
139 #define SI5341_OUT_R_REG(output) \
140 ((output)->data->reg_rdiv_offset[(output)->index])
141
142 #define SI5341_OUT_MUX_VDD_SEL_MASK 0x38
143
144 /* Synthesize N divider */
145 #define SI5341_SYNTH_N_NUM(x) (0x0302 + ((x) * 11))
146 #define SI5341_SYNTH_N_DEN(x) (0x0308 + ((x) * 11))
147 #define SI5341_SYNTH_N_UPD(x) (0x030C + ((x) * 11))
148
149 /* Synthesizer output enable, phase bypass, power mode */
150 #define SI5341_SYNTH_N_CLK_TO_OUTX_EN 0x0A03
151 #define SI5341_SYNTH_N_PIBYP 0x0A04
152 #define SI5341_SYNTH_N_PDNB 0x0A05
153 #define SI5341_SYNTH_N_CLK_DIS 0x0B4A
154
155 #define SI5341_REGISTER_MAX 0xBFF
156
157 /* SI5341_OUT_CONFIG bits */
158 #define SI5341_OUT_CFG_PDN BIT(0)
159 #define SI5341_OUT_CFG_OE BIT(1)
160 #define SI5341_OUT_CFG_RDIV_FORCE2 BIT(2)
161
162 /* Static configuration (to be moved to firmware) */
163 struct si5341_reg_default {
164 u16 address;
165 u8 value;
166 };
167
168 static const char * const si5341_input_clock_names[] = {
169 "in0", "in1", "in2", "xtal"
170 };
171
172 /* Output configuration registers 0..9 are not quite logically organized */
173 /* Also for si5345 */
174 static const u16 si5341_reg_output_offset[] = {
175 0x0108,
176 0x010D,
177 0x0112,
178 0x0117,
179 0x011C,
180 0x0121,
181 0x0126,
182 0x012B,
183 0x0130,
184 0x013A,
185 };
186
187 /* for si5340, si5342 and si5344 */
188 static const u16 si5340_reg_output_offset[] = {
189 0x0112,
190 0x0117,
191 0x0126,
192 0x012B,
193 };
194
195 /* The location of the R divider registers */
196 static const u16 si5341_reg_rdiv_offset[] = {
197 0x024A,
198 0x024D,
199 0x0250,
200 0x0253,
201 0x0256,
202 0x0259,
203 0x025C,
204 0x025F,
205 0x0262,
206 0x0268,
207 };
208 static const u16 si5340_reg_rdiv_offset[] = {
209 0x0250,
210 0x0253,
211 0x025C,
212 0x025F,
213 };
214
215 /*
216 * Programming sequence from ClockBuilder, settings to initialize the system
217 * using only the XTAL input, without pre-divider.
218 * This also contains settings that aren't mentioned anywhere in the datasheet.
219 * The "known" settings like synth and output configuration are done later.
220 */
221 static const struct si5341_reg_default si5341_reg_defaults[] = {
222 { 0x0017, 0x3A }, /* INT mask (disable interrupts) */
223 { 0x0018, 0xFF }, /* INT mask */
224 { 0x0021, 0x0F }, /* Select XTAL as input */
225 { 0x0022, 0x00 }, /* Not in datasheet */
226 { 0x002B, 0x02 }, /* SPI config */
227 { 0x002C, 0x20 }, /* LOS enable for XTAL */
228 { 0x002D, 0x00 }, /* LOS timing */
229 { 0x002E, 0x00 },
230 { 0x002F, 0x00 },
231 { 0x0030, 0x00 },
232 { 0x0031, 0x00 },
233 { 0x0032, 0x00 },
234 { 0x0033, 0x00 },
235 { 0x0034, 0x00 },
236 { 0x0035, 0x00 },
237 { 0x0036, 0x00 },
238 { 0x0037, 0x00 },
239 { 0x0038, 0x00 }, /* LOS setting (thresholds) */
240 { 0x0039, 0x00 },
241 { 0x003A, 0x00 },
242 { 0x003B, 0x00 },
243 { 0x003C, 0x00 },
244 { 0x003D, 0x00 }, /* LOS setting (thresholds) end */
245 { 0x0041, 0x00 }, /* LOS0_DIV_SEL */
246 { 0x0042, 0x00 }, /* LOS1_DIV_SEL */
247 { 0x0043, 0x00 }, /* LOS2_DIV_SEL */
248 { 0x0044, 0x00 }, /* LOS3_DIV_SEL */
249 { 0x009E, 0x00 }, /* Not in datasheet */
250 { 0x0102, 0x01 }, /* Enable outputs */
251 { 0x013F, 0x00 }, /* Not in datasheet */
252 { 0x0140, 0x00 }, /* Not in datasheet */
253 { 0x0141, 0x40 }, /* OUT LOS */
254 { 0x0202, 0x00 }, /* XAXB_FREQ_OFFSET (=0)*/
255 { 0x0203, 0x00 },
256 { 0x0204, 0x00 },
257 { 0x0205, 0x00 },
258 { 0x0206, 0x00 }, /* PXAXB (2^x) */
259 { 0x0208, 0x00 }, /* Px divider setting (usually 0) */
260 { 0x0209, 0x00 },
261 { 0x020A, 0x00 },
262 { 0x020B, 0x00 },
263 { 0x020C, 0x00 },
264 { 0x020D, 0x00 },
265 { 0x020E, 0x00 },
266 { 0x020F, 0x00 },
267 { 0x0210, 0x00 },
268 { 0x0211, 0x00 },
269 { 0x0212, 0x00 },
270 { 0x0213, 0x00 },
271 { 0x0214, 0x00 },
272 { 0x0215, 0x00 },
273 { 0x0216, 0x00 },
274 { 0x0217, 0x00 },
275 { 0x0218, 0x00 },
276 { 0x0219, 0x00 },
277 { 0x021A, 0x00 },
278 { 0x021B, 0x00 },
279 { 0x021C, 0x00 },
280 { 0x021D, 0x00 },
281 { 0x021E, 0x00 },
282 { 0x021F, 0x00 },
283 { 0x0220, 0x00 },
284 { 0x0221, 0x00 },
285 { 0x0222, 0x00 },
286 { 0x0223, 0x00 },
287 { 0x0224, 0x00 },
288 { 0x0225, 0x00 },
289 { 0x0226, 0x00 },
290 { 0x0227, 0x00 },
291 { 0x0228, 0x00 },
292 { 0x0229, 0x00 },
293 { 0x022A, 0x00 },
294 { 0x022B, 0x00 },
295 { 0x022C, 0x00 },
296 { 0x022D, 0x00 },
297 { 0x022E, 0x00 },
298 { 0x022F, 0x00 }, /* Px divider setting (usually 0) end */
299 { 0x026B, 0x00 }, /* DESIGN_ID (ASCII string) */
300 { 0x026C, 0x00 },
301 { 0x026D, 0x00 },
302 { 0x026E, 0x00 },
303 { 0x026F, 0x00 },
304 { 0x0270, 0x00 },
305 { 0x0271, 0x00 },
306 { 0x0272, 0x00 }, /* DESIGN_ID (ASCII string) end */
307 { 0x0339, 0x1F }, /* N_FSTEP_MSK */
308 { 0x033B, 0x00 }, /* Nx_FSTEPW (Frequency step) */
309 { 0x033C, 0x00 },
310 { 0x033D, 0x00 },
311 { 0x033E, 0x00 },
312 { 0x033F, 0x00 },
313 { 0x0340, 0x00 },
314 { 0x0341, 0x00 },
315 { 0x0342, 0x00 },
316 { 0x0343, 0x00 },
317 { 0x0344, 0x00 },
318 { 0x0345, 0x00 },
319 { 0x0346, 0x00 },
320 { 0x0347, 0x00 },
321 { 0x0348, 0x00 },
322 { 0x0349, 0x00 },
323 { 0x034A, 0x00 },
324 { 0x034B, 0x00 },
325 { 0x034C, 0x00 },
326 { 0x034D, 0x00 },
327 { 0x034E, 0x00 },
328 { 0x034F, 0x00 },
329 { 0x0350, 0x00 },
330 { 0x0351, 0x00 },
331 { 0x0352, 0x00 },
332 { 0x0353, 0x00 },
333 { 0x0354, 0x00 },
334 { 0x0355, 0x00 },
335 { 0x0356, 0x00 },
336 { 0x0357, 0x00 },
337 { 0x0358, 0x00 }, /* Nx_FSTEPW (Frequency step) end */
338 { 0x0359, 0x00 }, /* Nx_DELAY */
339 { 0x035A, 0x00 },
340 { 0x035B, 0x00 },
341 { 0x035C, 0x00 },
342 { 0x035D, 0x00 },
343 { 0x035E, 0x00 },
344 { 0x035F, 0x00 },
345 { 0x0360, 0x00 },
346 { 0x0361, 0x00 },
347 { 0x0362, 0x00 }, /* Nx_DELAY end */
348 { 0x0802, 0x00 }, /* Not in datasheet */
349 { 0x0803, 0x00 }, /* Not in datasheet */
350 { 0x0804, 0x00 }, /* Not in datasheet */
351 { 0x090E, 0x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */
352 { 0x091C, 0x04 }, /* ZDM_EN=4 (Normal mode) */
353 { 0x0943, 0x00 }, /* IO_VDD_SEL=0 (0=1v8, use 1=3v3) */
354 { 0x0949, 0x00 }, /* IN_EN (disable input clocks) */
355 { 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */
356 { 0x0A02, 0x00 }, /* Not in datasheet */
357 { 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */
358 { 0x0B57, 0x10 }, /* VCO_RESET_CALCODE (not described in datasheet) */
359 { 0x0B58, 0x05 }, /* VCO_RESET_CALCODE (not described in datasheet) */
360 };
361
362 /* Read and interpret a 44-bit followed by a 32-bit value in the regmap */
si5341_decode_44_32(struct regmap * regmap,unsigned int reg,u64 * val1,u32 * val2)363 static int si5341_decode_44_32(struct regmap *regmap, unsigned int reg,
364 u64 *val1, u32 *val2)
365 {
366 int err;
367 u8 r[10];
368
369 err = regmap_bulk_read(regmap, reg, r, 10);
370 if (err < 0)
371 return err;
372
373 *val1 = ((u64)((r[5] & 0x0f) << 8 | r[4]) << 32) |
374 (get_unaligned_le32(r));
375 *val2 = get_unaligned_le32(&r[6]);
376
377 return 0;
378 }
379
si5341_encode_44_32(struct regmap * regmap,unsigned int reg,u64 n_num,u32 n_den)380 static int si5341_encode_44_32(struct regmap *regmap, unsigned int reg,
381 u64 n_num, u32 n_den)
382 {
383 u8 r[10];
384
385 /* Shift left as far as possible without overflowing */
386 while (!(n_num & BIT_ULL(43)) && !(n_den & BIT(31))) {
387 n_num <<= 1;
388 n_den <<= 1;
389 }
390
391 /* 44 bits (6 bytes) numerator */
392 put_unaligned_le32(n_num, r);
393 r[4] = (n_num >> 32) & 0xff;
394 r[5] = (n_num >> 40) & 0x0f;
395 /* 32 bits denominator */
396 put_unaligned_le32(n_den, &r[6]);
397
398 /* Program the fraction */
399 return regmap_bulk_write(regmap, reg, r, sizeof(r));
400 }
401
402 /* VCO, we assume it runs at a constant frequency */
si5341_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)403 static unsigned long si5341_clk_recalc_rate(struct clk_hw *hw,
404 unsigned long parent_rate)
405 {
406 struct clk_si5341 *data = to_clk_si5341(hw);
407 int err;
408 u64 res;
409 u64 m_num;
410 u32 m_den;
411 unsigned int shift;
412
413 /* Assume that PDIV is not being used, just read the PLL setting */
414 err = si5341_decode_44_32(data->regmap, SI5341_PLL_M_NUM,
415 &m_num, &m_den);
416 if (err < 0)
417 return 0;
418
419 if (!m_num || !m_den)
420 return 0;
421
422 /*
423 * Though m_num is 64-bit, only the upper bits are actually used. While
424 * calculating m_num and m_den, they are shifted as far as possible to
425 * the left. To avoid 96-bit division here, we just shift them back so
426 * we can do with just 64 bits.
427 */
428 shift = 0;
429 res = m_num;
430 while (res & 0xffff00000000ULL) {
431 ++shift;
432 res >>= 1;
433 }
434 res *= parent_rate;
435 do_div(res, (m_den >> shift));
436
437 /* We cannot return the actual frequency in 32 bit, store it locally */
438 data->freq_vco = res;
439
440 /* Report kHz since the value is out of range */
441 do_div(res, 1000);
442
443 return (unsigned long)res;
444 }
445
si5341_clk_get_selected_input(struct clk_si5341 * data)446 static int si5341_clk_get_selected_input(struct clk_si5341 *data)
447 {
448 int err;
449 u32 val;
450
451 err = regmap_read(data->regmap, SI5341_IN_SEL, &val);
452 if (err < 0)
453 return err;
454
455 return (val & SI5341_IN_SEL_MASK) >> SI5341_IN_SEL_SHIFT;
456 }
457
si5341_clk_get_parent(struct clk_hw * hw)458 static u8 si5341_clk_get_parent(struct clk_hw *hw)
459 {
460 struct clk_si5341 *data = to_clk_si5341(hw);
461 int res = si5341_clk_get_selected_input(data);
462
463 if (res < 0)
464 return 0; /* Apparently we cannot report errors */
465
466 return res;
467 }
468
si5341_clk_reparent(struct clk_si5341 * data,u8 index)469 static int si5341_clk_reparent(struct clk_si5341 *data, u8 index)
470 {
471 int err;
472 u8 val;
473
474 val = (index << SI5341_IN_SEL_SHIFT) & SI5341_IN_SEL_MASK;
475 /* Enable register-based input selection */
476 val |= SI5341_IN_SEL_REGCTRL;
477
478 err = regmap_update_bits(data->regmap,
479 SI5341_IN_SEL, SI5341_IN_SEL_REGCTRL | SI5341_IN_SEL_MASK, val);
480 if (err < 0)
481 return err;
482
483 if (index < 3) {
484 /* Enable input buffer for selected input */
485 err = regmap_update_bits(data->regmap,
486 SI5341_IN_EN, 0x07, BIT(index));
487 if (err < 0)
488 return err;
489
490 /* Enables the input to phase detector */
491 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
492 0x7 << SI5341_INX_TO_PFD_SHIFT,
493 BIT(index + SI5341_INX_TO_PFD_SHIFT));
494 if (err < 0)
495 return err;
496
497 /* Power down XTAL oscillator and buffer */
498 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
499 SI5341_XAXB_CFG_PDNB, 0);
500 if (err < 0)
501 return err;
502
503 /*
504 * Set the P divider to "1". There's no explanation in the
505 * datasheet of these registers, but the clockbuilder software
506 * programs a "1" when the input is being used.
507 */
508 err = regmap_write(data->regmap, SI5341_IN_PDIV(index), 1);
509 if (err < 0)
510 return err;
511
512 err = regmap_write(data->regmap, SI5341_IN_PSET(index), 1);
513 if (err < 0)
514 return err;
515
516 /* Set update PDIV bit */
517 err = regmap_write(data->regmap, SI5341_PX_UPD, BIT(index));
518 if (err < 0)
519 return err;
520 } else {
521 /* Disable all input buffers */
522 err = regmap_update_bits(data->regmap, SI5341_IN_EN, 0x07, 0);
523 if (err < 0)
524 return err;
525
526 /* Disable input to phase detector */
527 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
528 0x7 << SI5341_INX_TO_PFD_SHIFT, 0);
529 if (err < 0)
530 return err;
531
532 /* Power up XTAL oscillator and buffer */
533 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
534 SI5341_XAXB_CFG_PDNB, SI5341_XAXB_CFG_PDNB);
535 if (err < 0)
536 return err;
537 }
538
539 return 0;
540 }
541
si5341_clk_set_parent(struct clk_hw * hw,u8 index)542 static int si5341_clk_set_parent(struct clk_hw *hw, u8 index)
543 {
544 struct clk_si5341 *data = to_clk_si5341(hw);
545
546 return si5341_clk_reparent(data, index);
547 }
548
549 static const struct clk_ops si5341_clk_ops = {
550 .set_parent = si5341_clk_set_parent,
551 .get_parent = si5341_clk_get_parent,
552 .recalc_rate = si5341_clk_recalc_rate,
553 };
554
555 /* Synthesizers, there are 5 synthesizers that connect to any of the outputs */
556
557 /* The synthesizer is on if all power and enable bits are set */
si5341_synth_clk_is_on(struct clk_hw * hw)558 static int si5341_synth_clk_is_on(struct clk_hw *hw)
559 {
560 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
561 int err;
562 u32 val;
563 u8 index = synth->index;
564
565 err = regmap_read(synth->data->regmap,
566 SI5341_SYNTH_N_CLK_TO_OUTX_EN, &val);
567 if (err < 0)
568 return 0;
569
570 if (!(val & BIT(index)))
571 return 0;
572
573 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val);
574 if (err < 0)
575 return 0;
576
577 if (!(val & BIT(index)))
578 return 0;
579
580 /* This bit must be 0 for the synthesizer to receive clock input */
581 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val);
582 if (err < 0)
583 return 0;
584
585 return !(val & BIT(index));
586 }
587
si5341_synth_clk_unprepare(struct clk_hw * hw)588 static void si5341_synth_clk_unprepare(struct clk_hw *hw)
589 {
590 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
591 u8 index = synth->index; /* In range 0..5 */
592 u8 mask = BIT(index);
593
594 /* Disable output */
595 regmap_update_bits(synth->data->regmap,
596 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, 0);
597 /* Power down */
598 regmap_update_bits(synth->data->regmap,
599 SI5341_SYNTH_N_PDNB, mask, 0);
600 /* Disable clock input to synth (set to 1 to disable) */
601 regmap_update_bits(synth->data->regmap,
602 SI5341_SYNTH_N_CLK_DIS, mask, mask);
603 }
604
si5341_synth_clk_prepare(struct clk_hw * hw)605 static int si5341_synth_clk_prepare(struct clk_hw *hw)
606 {
607 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
608 int err;
609 u8 index = synth->index;
610 u8 mask = BIT(index);
611
612 /* Power up */
613 err = regmap_update_bits(synth->data->regmap,
614 SI5341_SYNTH_N_PDNB, mask, mask);
615 if (err < 0)
616 return err;
617
618 /* Enable clock input to synth (set bit to 0 to enable) */
619 err = regmap_update_bits(synth->data->regmap,
620 SI5341_SYNTH_N_CLK_DIS, mask, 0);
621 if (err < 0)
622 return err;
623
624 /* Enable output */
625 return regmap_update_bits(synth->data->regmap,
626 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, mask);
627 }
628
629 /* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */
si5341_synth_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)630 static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw,
631 unsigned long parent_rate)
632 {
633 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
634 u64 f;
635 u64 n_num;
636 u32 n_den;
637 int err;
638
639 err = si5341_decode_44_32(synth->data->regmap,
640 SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den);
641 if (err < 0)
642 return err;
643 /* Check for bogus/uninitialized settings */
644 if (!n_num || !n_den)
645 return 0;
646
647 /*
648 * n_num and n_den are shifted left as much as possible, so to prevent
649 * overflow in 64-bit math, we shift n_den 4 bits to the right
650 */
651 f = synth->data->freq_vco;
652 f *= n_den >> 4;
653
654 /* Now we need to to 64-bit division: f/n_num */
655 /* And compensate for the 4 bits we dropped */
656 f = div64_u64(f, (n_num >> 4));
657
658 return f;
659 }
660
si5341_synth_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)661 static long si5341_synth_clk_round_rate(struct clk_hw *hw, unsigned long rate,
662 unsigned long *parent_rate)
663 {
664 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
665 u64 f;
666
667 /* The synthesizer accuracy is such that anything in range will work */
668 f = synth->data->freq_vco;
669 do_div(f, SI5341_SYNTH_N_MAX);
670 if (rate < f)
671 return f;
672
673 f = synth->data->freq_vco;
674 do_div(f, SI5341_SYNTH_N_MIN);
675 if (rate > f)
676 return f;
677
678 return rate;
679 }
680
si5341_synth_program(struct clk_si5341_synth * synth,u64 n_num,u32 n_den,bool is_integer)681 static int si5341_synth_program(struct clk_si5341_synth *synth,
682 u64 n_num, u32 n_den, bool is_integer)
683 {
684 int err;
685 u8 index = synth->index;
686
687 err = si5341_encode_44_32(synth->data->regmap,
688 SI5341_SYNTH_N_NUM(index), n_num, n_den);
689
690 err = regmap_update_bits(synth->data->regmap,
691 SI5341_SYNTH_N_PIBYP, BIT(index), is_integer ? BIT(index) : 0);
692 if (err < 0)
693 return err;
694
695 return regmap_write(synth->data->regmap,
696 SI5341_SYNTH_N_UPD(index), 0x01);
697 }
698
699
si5341_synth_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)700 static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate,
701 unsigned long parent_rate)
702 {
703 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
704 u64 n_num;
705 u32 n_den;
706 u32 r;
707 u32 g;
708 bool is_integer;
709
710 n_num = synth->data->freq_vco;
711
712 /* see if there's an integer solution */
713 r = do_div(n_num, rate);
714 is_integer = (r == 0);
715 if (is_integer) {
716 /* Integer divider equal to n_num */
717 n_den = 1;
718 } else {
719 /* Calculate a fractional solution */
720 g = gcd(r, rate);
721 n_den = rate / g;
722 n_num *= n_den;
723 n_num += r / g;
724 }
725
726 dev_dbg(&synth->data->i2c_client->dev,
727 "%s(%u): n=0x%llx d=0x%x %s\n", __func__,
728 synth->index, n_num, n_den,
729 is_integer ? "int" : "frac");
730
731 return si5341_synth_program(synth, n_num, n_den, is_integer);
732 }
733
734 static const struct clk_ops si5341_synth_clk_ops = {
735 .is_prepared = si5341_synth_clk_is_on,
736 .prepare = si5341_synth_clk_prepare,
737 .unprepare = si5341_synth_clk_unprepare,
738 .recalc_rate = si5341_synth_clk_recalc_rate,
739 .round_rate = si5341_synth_clk_round_rate,
740 .set_rate = si5341_synth_clk_set_rate,
741 };
742
si5341_output_clk_is_on(struct clk_hw * hw)743 static int si5341_output_clk_is_on(struct clk_hw *hw)
744 {
745 struct clk_si5341_output *output = to_clk_si5341_output(hw);
746 int err;
747 u32 val;
748
749 err = regmap_read(output->data->regmap,
750 SI5341_OUT_CONFIG(output), &val);
751 if (err < 0)
752 return err;
753
754 /* Bit 0=PDN, 1=OE so only a value of 0x2 enables the output */
755 return (val & 0x03) == SI5341_OUT_CFG_OE;
756 }
757
758 /* Disables and then powers down the output */
si5341_output_clk_unprepare(struct clk_hw * hw)759 static void si5341_output_clk_unprepare(struct clk_hw *hw)
760 {
761 struct clk_si5341_output *output = to_clk_si5341_output(hw);
762
763 regmap_update_bits(output->data->regmap,
764 SI5341_OUT_CONFIG(output),
765 SI5341_OUT_CFG_OE, 0);
766 regmap_update_bits(output->data->regmap,
767 SI5341_OUT_CONFIG(output),
768 SI5341_OUT_CFG_PDN, SI5341_OUT_CFG_PDN);
769 }
770
771 /* Powers up and then enables the output */
si5341_output_clk_prepare(struct clk_hw * hw)772 static int si5341_output_clk_prepare(struct clk_hw *hw)
773 {
774 struct clk_si5341_output *output = to_clk_si5341_output(hw);
775 int err;
776
777 err = regmap_update_bits(output->data->regmap,
778 SI5341_OUT_CONFIG(output),
779 SI5341_OUT_CFG_PDN, 0);
780 if (err < 0)
781 return err;
782
783 return regmap_update_bits(output->data->regmap,
784 SI5341_OUT_CONFIG(output),
785 SI5341_OUT_CFG_OE, SI5341_OUT_CFG_OE);
786 }
787
si5341_output_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)788 static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,
789 unsigned long parent_rate)
790 {
791 struct clk_si5341_output *output = to_clk_si5341_output(hw);
792 int err;
793 u32 val;
794 u32 r_divider;
795 u8 r[3];
796
797 err = regmap_read(output->data->regmap,
798 SI5341_OUT_CONFIG(output), &val);
799 if (err < 0)
800 return err;
801
802 /* If SI5341_OUT_CFG_RDIV_FORCE2 is set, r_divider is 2 */
803 if (val & SI5341_OUT_CFG_RDIV_FORCE2)
804 return parent_rate / 2;
805
806 err = regmap_bulk_read(output->data->regmap,
807 SI5341_OUT_R_REG(output), r, 3);
808 if (err < 0)
809 return err;
810
811 /* Calculate value as 24-bit integer*/
812 r_divider = r[2] << 16 | r[1] << 8 | r[0];
813
814 /* If Rx_REG is zero, the divider is disabled, so return a "0" rate */
815 if (!r_divider)
816 return 0;
817
818 /* Divider is 2*(Rx_REG+1) */
819 r_divider += 1;
820 r_divider <<= 1;
821
822
823 return parent_rate / r_divider;
824 }
825
si5341_output_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)826 static long si5341_output_clk_round_rate(struct clk_hw *hw, unsigned long rate,
827 unsigned long *parent_rate)
828 {
829 unsigned long r;
830
831 if (!rate)
832 return 0;
833
834 r = *parent_rate >> 1;
835
836 /* If rate is an even divisor, no changes to parent required */
837 if (r && !(r % rate))
838 return (long)rate;
839
840 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
841 if (rate > 200000000) {
842 /* minimum r-divider is 2 */
843 r = 2;
844 } else {
845 /* Take a parent frequency near 400 MHz */
846 r = (400000000u / rate) & ~1;
847 }
848 *parent_rate = r * rate;
849 } else {
850 /* We cannot change our parent's rate, report what we can do */
851 r /= rate;
852 rate = *parent_rate / (r << 1);
853 }
854
855 return rate;
856 }
857
si5341_output_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)858 static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate,
859 unsigned long parent_rate)
860 {
861 struct clk_si5341_output *output = to_clk_si5341_output(hw);
862 u32 r_div;
863 int err;
864 u8 r[3];
865
866 if (!rate)
867 return -EINVAL;
868
869 /* Frequency divider is (r_div + 1) * 2 */
870 r_div = (parent_rate / rate) >> 1;
871
872 if (r_div <= 1)
873 r_div = 0;
874 else if (r_div >= BIT(24))
875 r_div = BIT(24) - 1;
876 else
877 --r_div;
878
879 /* For a value of "2", we set the "OUT0_RDIV_FORCE2" bit */
880 err = regmap_update_bits(output->data->regmap,
881 SI5341_OUT_CONFIG(output),
882 SI5341_OUT_CFG_RDIV_FORCE2,
883 (r_div == 0) ? SI5341_OUT_CFG_RDIV_FORCE2 : 0);
884 if (err < 0)
885 return err;
886
887 /* Always write Rx_REG, because a zero value disables the divider */
888 r[0] = r_div ? (r_div & 0xff) : 1;
889 r[1] = (r_div >> 8) & 0xff;
890 r[2] = (r_div >> 16) & 0xff;
891 return regmap_bulk_write(output->data->regmap,
892 SI5341_OUT_R_REG(output), r, 3);
893 }
894
si5341_output_reparent(struct clk_si5341_output * output,u8 index)895 static int si5341_output_reparent(struct clk_si5341_output *output, u8 index)
896 {
897 return regmap_update_bits(output->data->regmap,
898 SI5341_OUT_MUX_SEL(output), 0x07, index);
899 }
900
si5341_output_set_parent(struct clk_hw * hw,u8 index)901 static int si5341_output_set_parent(struct clk_hw *hw, u8 index)
902 {
903 struct clk_si5341_output *output = to_clk_si5341_output(hw);
904
905 if (index >= output->data->num_synth)
906 return -EINVAL;
907
908 return si5341_output_reparent(output, index);
909 }
910
si5341_output_get_parent(struct clk_hw * hw)911 static u8 si5341_output_get_parent(struct clk_hw *hw)
912 {
913 struct clk_si5341_output *output = to_clk_si5341_output(hw);
914 u32 val;
915
916 regmap_read(output->data->regmap, SI5341_OUT_MUX_SEL(output), &val);
917
918 return val & 0x7;
919 }
920
921 static const struct clk_ops si5341_output_clk_ops = {
922 .is_prepared = si5341_output_clk_is_on,
923 .prepare = si5341_output_clk_prepare,
924 .unprepare = si5341_output_clk_unprepare,
925 .recalc_rate = si5341_output_clk_recalc_rate,
926 .round_rate = si5341_output_clk_round_rate,
927 .set_rate = si5341_output_clk_set_rate,
928 .set_parent = si5341_output_set_parent,
929 .get_parent = si5341_output_get_parent,
930 };
931
932 /*
933 * The chip can be bought in a pre-programmed version, or one can program the
934 * NVM in the chip to boot up in a preset mode. This routine tries to determine
935 * if that's the case, or if we need to reset and program everything from
936 * scratch. Returns negative error, or true/false.
937 */
si5341_is_programmed_already(struct clk_si5341 * data)938 static int si5341_is_programmed_already(struct clk_si5341 *data)
939 {
940 int err;
941 u8 r[4];
942
943 /* Read the PLL divider value, it must have a non-zero value */
944 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_DEN,
945 r, ARRAY_SIZE(r));
946 if (err < 0)
947 return err;
948
949 return !!get_unaligned_le32(r);
950 }
951
952 static struct clk_hw *
of_clk_si5341_get(struct of_phandle_args * clkspec,void * _data)953 of_clk_si5341_get(struct of_phandle_args *clkspec, void *_data)
954 {
955 struct clk_si5341 *data = _data;
956 unsigned int idx = clkspec->args[1];
957 unsigned int group = clkspec->args[0];
958
959 switch (group) {
960 case 0:
961 if (idx >= data->num_outputs) {
962 dev_err(&data->i2c_client->dev,
963 "invalid output index %u\n", idx);
964 return ERR_PTR(-EINVAL);
965 }
966 return &data->clk[idx].hw;
967 case 1:
968 if (idx >= data->num_synth) {
969 dev_err(&data->i2c_client->dev,
970 "invalid synthesizer index %u\n", idx);
971 return ERR_PTR(-EINVAL);
972 }
973 return &data->synth[idx].hw;
974 case 2:
975 if (idx > 0) {
976 dev_err(&data->i2c_client->dev,
977 "invalid PLL index %u\n", idx);
978 return ERR_PTR(-EINVAL);
979 }
980 return &data->hw;
981 default:
982 dev_err(&data->i2c_client->dev, "invalid group %u\n", group);
983 return ERR_PTR(-EINVAL);
984 }
985 }
986
si5341_probe_chip_id(struct clk_si5341 * data)987 static int si5341_probe_chip_id(struct clk_si5341 *data)
988 {
989 int err;
990 u8 reg[4];
991 u16 model;
992
993 err = regmap_bulk_read(data->regmap, SI5341_PN_BASE, reg,
994 ARRAY_SIZE(reg));
995 if (err < 0) {
996 dev_err(&data->i2c_client->dev, "Failed to read chip ID\n");
997 return err;
998 }
999
1000 model = get_unaligned_le16(reg);
1001
1002 dev_info(&data->i2c_client->dev, "Chip: %x Grade: %u Rev: %u\n",
1003 model, reg[2], reg[3]);
1004
1005 switch (model) {
1006 case 0x5340:
1007 data->num_outputs = SI5340_MAX_NUM_OUTPUTS;
1008 data->num_synth = SI5340_NUM_SYNTH;
1009 data->reg_output_offset = si5340_reg_output_offset;
1010 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1011 break;
1012 case 0x5341:
1013 data->num_outputs = SI5341_MAX_NUM_OUTPUTS;
1014 data->num_synth = SI5341_NUM_SYNTH;
1015 data->reg_output_offset = si5341_reg_output_offset;
1016 data->reg_rdiv_offset = si5341_reg_rdiv_offset;
1017 break;
1018 case 0x5342:
1019 data->num_outputs = SI5342_MAX_NUM_OUTPUTS;
1020 data->num_synth = SI5342_NUM_SYNTH;
1021 data->reg_output_offset = si5340_reg_output_offset;
1022 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1023 break;
1024 case 0x5344:
1025 data->num_outputs = SI5344_MAX_NUM_OUTPUTS;
1026 data->num_synth = SI5344_NUM_SYNTH;
1027 data->reg_output_offset = si5340_reg_output_offset;
1028 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1029 break;
1030 case 0x5345:
1031 data->num_outputs = SI5345_MAX_NUM_OUTPUTS;
1032 data->num_synth = SI5345_NUM_SYNTH;
1033 data->reg_output_offset = si5341_reg_output_offset;
1034 data->reg_rdiv_offset = si5341_reg_rdiv_offset;
1035 break;
1036 default:
1037 dev_err(&data->i2c_client->dev, "Model '%x' not supported\n",
1038 model);
1039 return -EINVAL;
1040 }
1041
1042 data->chip_id = model;
1043
1044 return 0;
1045 }
1046
1047 /* Read active settings into the regmap cache for later reference */
si5341_read_settings(struct clk_si5341 * data)1048 static int si5341_read_settings(struct clk_si5341 *data)
1049 {
1050 int err;
1051 u8 i;
1052 u8 r[10];
1053
1054 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_NUM, r, 10);
1055 if (err < 0)
1056 return err;
1057
1058 err = regmap_bulk_read(data->regmap,
1059 SI5341_SYNTH_N_CLK_TO_OUTX_EN, r, 3);
1060 if (err < 0)
1061 return err;
1062
1063 err = regmap_bulk_read(data->regmap,
1064 SI5341_SYNTH_N_CLK_DIS, r, 1);
1065 if (err < 0)
1066 return err;
1067
1068 for (i = 0; i < data->num_synth; ++i) {
1069 err = regmap_bulk_read(data->regmap,
1070 SI5341_SYNTH_N_NUM(i), r, 10);
1071 if (err < 0)
1072 return err;
1073 }
1074
1075 for (i = 0; i < data->num_outputs; ++i) {
1076 err = regmap_bulk_read(data->regmap,
1077 data->reg_output_offset[i], r, 4);
1078 if (err < 0)
1079 return err;
1080
1081 err = regmap_bulk_read(data->regmap,
1082 data->reg_rdiv_offset[i], r, 3);
1083 if (err < 0)
1084 return err;
1085 }
1086
1087 return 0;
1088 }
1089
si5341_write_multiple(struct clk_si5341 * data,const struct si5341_reg_default * values,unsigned int num_values)1090 static int si5341_write_multiple(struct clk_si5341 *data,
1091 const struct si5341_reg_default *values, unsigned int num_values)
1092 {
1093 unsigned int i;
1094 int res;
1095
1096 for (i = 0; i < num_values; ++i) {
1097 res = regmap_write(data->regmap,
1098 values[i].address, values[i].value);
1099 if (res < 0) {
1100 dev_err(&data->i2c_client->dev,
1101 "Failed to write %#x:%#x\n",
1102 values[i].address, values[i].value);
1103 return res;
1104 }
1105 }
1106
1107 return 0;
1108 }
1109
1110 static const struct si5341_reg_default si5341_preamble[] = {
1111 { 0x0B25, 0x00 },
1112 { 0x0502, 0x01 },
1113 { 0x0505, 0x03 },
1114 { 0x0957, 0x17 },
1115 { 0x0B4E, 0x1A },
1116 };
1117
1118 static const struct si5341_reg_default si5345_preamble[] = {
1119 { 0x0B25, 0x00 },
1120 { 0x0540, 0x01 },
1121 };
1122
si5341_send_preamble(struct clk_si5341 * data)1123 static int si5341_send_preamble(struct clk_si5341 *data)
1124 {
1125 int res;
1126 u32 revision;
1127
1128 /* For revision 2 and up, the values are slightly different */
1129 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
1130 if (res < 0)
1131 return res;
1132
1133 /* Write "preamble" as specified by datasheet */
1134 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xD8 : 0xC0);
1135 if (res < 0)
1136 return res;
1137
1138 /* The si5342..si5345 require a different preamble */
1139 if (data->chip_id > 0x5341)
1140 res = si5341_write_multiple(data,
1141 si5345_preamble, ARRAY_SIZE(si5345_preamble));
1142 else
1143 res = si5341_write_multiple(data,
1144 si5341_preamble, ARRAY_SIZE(si5341_preamble));
1145 if (res < 0)
1146 return res;
1147
1148 /* Datasheet specifies a 300ms wait after sending the preamble */
1149 msleep(300);
1150
1151 return 0;
1152 }
1153
1154 /* Perform a soft reset and write post-amble */
si5341_finalize_defaults(struct clk_si5341 * data)1155 static int si5341_finalize_defaults(struct clk_si5341 *data)
1156 {
1157 int res;
1158 u32 revision;
1159
1160 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
1161 if (res < 0)
1162 return res;
1163
1164 dev_dbg(&data->i2c_client->dev, "%s rev=%u\n", __func__, revision);
1165
1166 res = regmap_write(data->regmap, SI5341_SOFT_RST, 0x01);
1167 if (res < 0)
1168 return res;
1169
1170 /* The si5342..si5345 have an additional post-amble */
1171 if (data->chip_id > 0x5341) {
1172 res = regmap_write(data->regmap, 0x540, 0x0);
1173 if (res < 0)
1174 return res;
1175 }
1176
1177 /* Datasheet does not explain these nameless registers */
1178 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xDB : 0xC3);
1179 if (res < 0)
1180 return res;
1181 res = regmap_write(data->regmap, 0x0B25, 0x02);
1182 if (res < 0)
1183 return res;
1184
1185 return 0;
1186 }
1187
1188
1189 static const struct regmap_range si5341_regmap_volatile_range[] = {
1190 regmap_reg_range(0x000C, 0x0012), /* Status */
1191 regmap_reg_range(0x001C, 0x001E), /* reset, finc/fdec */
1192 regmap_reg_range(0x00E2, 0x00FE), /* NVM, interrupts, device ready */
1193 /* Update bits for P divider and synth config */
1194 regmap_reg_range(SI5341_PX_UPD, SI5341_PX_UPD),
1195 regmap_reg_range(SI5341_SYNTH_N_UPD(0), SI5341_SYNTH_N_UPD(0)),
1196 regmap_reg_range(SI5341_SYNTH_N_UPD(1), SI5341_SYNTH_N_UPD(1)),
1197 regmap_reg_range(SI5341_SYNTH_N_UPD(2), SI5341_SYNTH_N_UPD(2)),
1198 regmap_reg_range(SI5341_SYNTH_N_UPD(3), SI5341_SYNTH_N_UPD(3)),
1199 regmap_reg_range(SI5341_SYNTH_N_UPD(4), SI5341_SYNTH_N_UPD(4)),
1200 };
1201
1202 static const struct regmap_access_table si5341_regmap_volatile = {
1203 .yes_ranges = si5341_regmap_volatile_range,
1204 .n_yes_ranges = ARRAY_SIZE(si5341_regmap_volatile_range),
1205 };
1206
1207 /* Pages 0, 1, 2, 3, 9, A, B are valid, so there are 12 pages */
1208 static const struct regmap_range_cfg si5341_regmap_ranges[] = {
1209 {
1210 .range_min = 0,
1211 .range_max = SI5341_REGISTER_MAX,
1212 .selector_reg = SI5341_PAGE,
1213 .selector_mask = 0xff,
1214 .selector_shift = 0,
1215 .window_start = 0,
1216 .window_len = 256,
1217 },
1218 };
1219
si5341_wait_device_ready(struct i2c_client * client)1220 static int si5341_wait_device_ready(struct i2c_client *client)
1221 {
1222 int count;
1223
1224 /* Datasheet warns: Any attempt to read or write any register other
1225 * than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the
1226 * NVM programming and may corrupt the register contents, as they are
1227 * read from NVM. Note that this includes accesses to the PAGE register.
1228 * Also: DEVICE_READY is available on every register page, so no page
1229 * change is needed to read it.
1230 * Do this outside regmap to avoid automatic PAGE register access.
1231 * May take up to 300ms to complete.
1232 */
1233 for (count = 0; count < 15; ++count) {
1234 s32 result = i2c_smbus_read_byte_data(client,
1235 SI5341_DEVICE_READY);
1236 if (result < 0)
1237 return result;
1238 if (result == 0x0F)
1239 return 0;
1240 msleep(20);
1241 }
1242 dev_err(&client->dev, "timeout waiting for DEVICE_READY\n");
1243 return -EIO;
1244 }
1245
1246 static const struct regmap_config si5341_regmap_config = {
1247 .reg_bits = 8,
1248 .val_bits = 8,
1249 .cache_type = REGCACHE_RBTREE,
1250 .ranges = si5341_regmap_ranges,
1251 .num_ranges = ARRAY_SIZE(si5341_regmap_ranges),
1252 .max_register = SI5341_REGISTER_MAX,
1253 .volatile_table = &si5341_regmap_volatile,
1254 };
1255
si5341_dt_parse_dt(struct clk_si5341 * data,struct clk_si5341_output_config * config)1256 static int si5341_dt_parse_dt(struct clk_si5341 *data,
1257 struct clk_si5341_output_config *config)
1258 {
1259 struct device_node *child;
1260 struct device_node *np = data->i2c_client->dev.of_node;
1261 u32 num;
1262 u32 val;
1263
1264 memset(config, 0, sizeof(struct clk_si5341_output_config) *
1265 SI5341_MAX_NUM_OUTPUTS);
1266
1267 for_each_child_of_node(np, child) {
1268 if (of_property_read_u32(child, "reg", &num)) {
1269 dev_err(&data->i2c_client->dev, "missing reg property of %s\n",
1270 child->name);
1271 goto put_child;
1272 }
1273
1274 if (num >= SI5341_MAX_NUM_OUTPUTS) {
1275 dev_err(&data->i2c_client->dev, "invalid clkout %d\n", num);
1276 goto put_child;
1277 }
1278
1279 if (!of_property_read_u32(child, "silabs,format", &val)) {
1280 /* Set cm and ampl conservatively to 3v3 settings */
1281 switch (val) {
1282 case 1: /* normal differential */
1283 config[num].out_cm_ampl_bits = 0x33;
1284 break;
1285 case 2: /* low-power differential */
1286 config[num].out_cm_ampl_bits = 0x13;
1287 break;
1288 case 4: /* LVCMOS */
1289 config[num].out_cm_ampl_bits = 0x33;
1290 /* Set SI recommended impedance for LVCMOS */
1291 config[num].out_format_drv_bits |= 0xc0;
1292 break;
1293 default:
1294 dev_err(&data->i2c_client->dev,
1295 "invalid silabs,format %u for %u\n",
1296 val, num);
1297 goto put_child;
1298 }
1299 config[num].out_format_drv_bits &= ~0x07;
1300 config[num].out_format_drv_bits |= val & 0x07;
1301 /* Always enable the SYNC feature */
1302 config[num].out_format_drv_bits |= 0x08;
1303 }
1304
1305 if (!of_property_read_u32(child, "silabs,common-mode", &val)) {
1306 if (val > 0xf) {
1307 dev_err(&data->i2c_client->dev,
1308 "invalid silabs,common-mode %u\n",
1309 val);
1310 goto put_child;
1311 }
1312 config[num].out_cm_ampl_bits &= 0xf0;
1313 config[num].out_cm_ampl_bits |= val & 0x0f;
1314 }
1315
1316 if (!of_property_read_u32(child, "silabs,amplitude", &val)) {
1317 if (val > 0xf) {
1318 dev_err(&data->i2c_client->dev,
1319 "invalid silabs,amplitude %u\n",
1320 val);
1321 goto put_child;
1322 }
1323 config[num].out_cm_ampl_bits &= 0x0f;
1324 config[num].out_cm_ampl_bits |= (val << 4) & 0xf0;
1325 }
1326
1327 if (of_property_read_bool(child, "silabs,disable-high"))
1328 config[num].out_format_drv_bits |= 0x10;
1329
1330 config[num].synth_master =
1331 of_property_read_bool(child, "silabs,synth-master");
1332
1333 config[num].always_on =
1334 of_property_read_bool(child, "always-on");
1335
1336 config[num].vdd_sel_bits = 0x08;
1337 if (data->clk[num].vddo_reg) {
1338 int vdd = regulator_get_voltage(data->clk[num].vddo_reg);
1339
1340 switch (vdd) {
1341 case 3300000:
1342 config[num].vdd_sel_bits |= 0 << 4;
1343 break;
1344 case 1800000:
1345 config[num].vdd_sel_bits |= 1 << 4;
1346 break;
1347 case 2500000:
1348 config[num].vdd_sel_bits |= 2 << 4;
1349 break;
1350 default:
1351 dev_err(&data->i2c_client->dev,
1352 "unsupported vddo voltage %d for %s\n",
1353 vdd, child->name);
1354 goto put_child;
1355 }
1356 } else {
1357 /* chip seems to default to 2.5V when not set */
1358 dev_warn(&data->i2c_client->dev,
1359 "no regulator set, defaulting vdd_sel to 2.5V for %s\n",
1360 child->name);
1361 config[num].vdd_sel_bits |= 2 << 4;
1362 }
1363 }
1364
1365 return 0;
1366
1367 put_child:
1368 of_node_put(child);
1369 return -EINVAL;
1370 }
1371
1372 /*
1373 * If not pre-configured, calculate and set the PLL configuration manually.
1374 * For low-jitter performance, the PLL should be set such that the synthesizers
1375 * only need integer division.
1376 * Without any user guidance, we'll set the PLL to 14GHz, which still allows
1377 * the chip to generate any frequency on its outputs, but jitter performance
1378 * may be sub-optimal.
1379 */
si5341_initialize_pll(struct clk_si5341 * data)1380 static int si5341_initialize_pll(struct clk_si5341 *data)
1381 {
1382 struct device_node *np = data->i2c_client->dev.of_node;
1383 u32 m_num = 0;
1384 u32 m_den = 0;
1385 int sel;
1386
1387 if (of_property_read_u32(np, "silabs,pll-m-num", &m_num)) {
1388 dev_err(&data->i2c_client->dev,
1389 "PLL configuration requires silabs,pll-m-num\n");
1390 }
1391 if (of_property_read_u32(np, "silabs,pll-m-den", &m_den)) {
1392 dev_err(&data->i2c_client->dev,
1393 "PLL configuration requires silabs,pll-m-den\n");
1394 }
1395
1396 if (!m_num || !m_den) {
1397 dev_err(&data->i2c_client->dev,
1398 "PLL configuration invalid, assume 14GHz\n");
1399 sel = si5341_clk_get_selected_input(data);
1400 if (sel < 0)
1401 return sel;
1402
1403 m_den = clk_get_rate(data->input_clk[sel]) / 10;
1404 m_num = 1400000000;
1405 }
1406
1407 return si5341_encode_44_32(data->regmap,
1408 SI5341_PLL_M_NUM, m_num, m_den);
1409 }
1410
si5341_clk_select_active_input(struct clk_si5341 * data)1411 static int si5341_clk_select_active_input(struct clk_si5341 *data)
1412 {
1413 int res;
1414 int err;
1415 int i;
1416
1417 res = si5341_clk_get_selected_input(data);
1418 if (res < 0)
1419 return res;
1420
1421 /* If the current register setting is invalid, pick the first input */
1422 if (!data->input_clk[res]) {
1423 dev_dbg(&data->i2c_client->dev,
1424 "Input %d not connected, rerouting\n", res);
1425 res = -ENODEV;
1426 for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
1427 if (data->input_clk[i]) {
1428 res = i;
1429 break;
1430 }
1431 }
1432 if (res < 0) {
1433 dev_err(&data->i2c_client->dev,
1434 "No clock input available\n");
1435 return res;
1436 }
1437 }
1438
1439 /* Make sure the selected clock is also enabled and routed */
1440 err = si5341_clk_reparent(data, res);
1441 if (err < 0)
1442 return err;
1443
1444 err = clk_prepare_enable(data->input_clk[res]);
1445 if (err < 0)
1446 return err;
1447
1448 return res;
1449 }
1450
input_present_show(struct device * dev,struct device_attribute * attr,char * buf)1451 static ssize_t input_present_show(struct device *dev,
1452 struct device_attribute *attr,
1453 char *buf)
1454 {
1455 struct clk_si5341 *data = dev_get_drvdata(dev);
1456 u32 status;
1457 int res = regmap_read(data->regmap, SI5341_STATUS, &status);
1458
1459 if (res < 0)
1460 return res;
1461 res = !(status & SI5341_STATUS_LOSREF);
1462 return snprintf(buf, PAGE_SIZE, "%d\n", res);
1463 }
1464 static DEVICE_ATTR_RO(input_present);
1465
input_present_sticky_show(struct device * dev,struct device_attribute * attr,char * buf)1466 static ssize_t input_present_sticky_show(struct device *dev,
1467 struct device_attribute *attr,
1468 char *buf)
1469 {
1470 struct clk_si5341 *data = dev_get_drvdata(dev);
1471 u32 status;
1472 int res = regmap_read(data->regmap, SI5341_STATUS_STICKY, &status);
1473
1474 if (res < 0)
1475 return res;
1476 res = !(status & SI5341_STATUS_LOSREF);
1477 return snprintf(buf, PAGE_SIZE, "%d\n", res);
1478 }
1479 static DEVICE_ATTR_RO(input_present_sticky);
1480
pll_locked_show(struct device * dev,struct device_attribute * attr,char * buf)1481 static ssize_t pll_locked_show(struct device *dev,
1482 struct device_attribute *attr,
1483 char *buf)
1484 {
1485 struct clk_si5341 *data = dev_get_drvdata(dev);
1486 u32 status;
1487 int res = regmap_read(data->regmap, SI5341_STATUS, &status);
1488
1489 if (res < 0)
1490 return res;
1491 res = !(status & SI5341_STATUS_LOL);
1492 return snprintf(buf, PAGE_SIZE, "%d\n", res);
1493 }
1494 static DEVICE_ATTR_RO(pll_locked);
1495
pll_locked_sticky_show(struct device * dev,struct device_attribute * attr,char * buf)1496 static ssize_t pll_locked_sticky_show(struct device *dev,
1497 struct device_attribute *attr,
1498 char *buf)
1499 {
1500 struct clk_si5341 *data = dev_get_drvdata(dev);
1501 u32 status;
1502 int res = regmap_read(data->regmap, SI5341_STATUS_STICKY, &status);
1503
1504 if (res < 0)
1505 return res;
1506 res = !(status & SI5341_STATUS_LOL);
1507 return snprintf(buf, PAGE_SIZE, "%d\n", res);
1508 }
1509 static DEVICE_ATTR_RO(pll_locked_sticky);
1510
clear_sticky_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1511 static ssize_t clear_sticky_store(struct device *dev,
1512 struct device_attribute *attr,
1513 const char *buf, size_t count)
1514 {
1515 struct clk_si5341 *data = dev_get_drvdata(dev);
1516 long val;
1517
1518 if (kstrtol(buf, 10, &val))
1519 return -EINVAL;
1520 if (val) {
1521 int res = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0);
1522
1523 if (res < 0)
1524 return res;
1525 }
1526 return count;
1527 }
1528 static DEVICE_ATTR_WO(clear_sticky);
1529
1530 static const struct attribute *si5341_attributes[] = {
1531 &dev_attr_input_present.attr,
1532 &dev_attr_input_present_sticky.attr,
1533 &dev_attr_pll_locked.attr,
1534 &dev_attr_pll_locked_sticky.attr,
1535 &dev_attr_clear_sticky.attr,
1536 NULL
1537 };
1538
si5341_probe(struct i2c_client * client,const struct i2c_device_id * id)1539 static int si5341_probe(struct i2c_client *client,
1540 const struct i2c_device_id *id)
1541 {
1542 struct clk_si5341 *data;
1543 struct clk_init_data init;
1544 struct clk *input;
1545 const char *root_clock_name;
1546 const char *synth_clock_names[SI5341_NUM_SYNTH] = { NULL };
1547 int err;
1548 unsigned int i;
1549 struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS];
1550 bool initialization_required;
1551 u32 status;
1552
1553 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
1554 if (!data)
1555 return -ENOMEM;
1556
1557 data->i2c_client = client;
1558
1559 /* Must be done before otherwise touching hardware */
1560 err = si5341_wait_device_ready(client);
1561 if (err)
1562 return err;
1563
1564 for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
1565 input = devm_clk_get(&client->dev, si5341_input_clock_names[i]);
1566 if (IS_ERR(input)) {
1567 if (PTR_ERR(input) == -EPROBE_DEFER)
1568 return -EPROBE_DEFER;
1569 data->input_clk_name[i] = si5341_input_clock_names[i];
1570 } else {
1571 data->input_clk[i] = input;
1572 data->input_clk_name[i] = __clk_get_name(input);
1573 }
1574 }
1575
1576 for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) {
1577 char reg_name[10];
1578
1579 snprintf(reg_name, sizeof(reg_name), "vddo%d", i);
1580 data->clk[i].vddo_reg = devm_regulator_get_optional(
1581 &client->dev, reg_name);
1582 if (IS_ERR(data->clk[i].vddo_reg)) {
1583 err = PTR_ERR(data->clk[i].vddo_reg);
1584 data->clk[i].vddo_reg = NULL;
1585 if (err == -ENODEV)
1586 continue;
1587 goto cleanup;
1588 } else {
1589 err = regulator_enable(data->clk[i].vddo_reg);
1590 if (err) {
1591 dev_err(&client->dev,
1592 "failed to enable %s regulator: %d\n",
1593 reg_name, err);
1594 data->clk[i].vddo_reg = NULL;
1595 goto cleanup;
1596 }
1597 }
1598 }
1599
1600 err = si5341_dt_parse_dt(data, config);
1601 if (err)
1602 goto cleanup;
1603
1604 if (of_property_read_string(client->dev.of_node, "clock-output-names",
1605 &init.name))
1606 init.name = client->dev.of_node->name;
1607 root_clock_name = init.name;
1608
1609 data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config);
1610 if (IS_ERR(data->regmap)) {
1611 err = PTR_ERR(data->regmap);
1612 goto cleanup;
1613 }
1614
1615 i2c_set_clientdata(client, data);
1616
1617 err = si5341_probe_chip_id(data);
1618 if (err < 0)
1619 goto cleanup;
1620
1621 if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) {
1622 initialization_required = true;
1623 } else {
1624 err = si5341_is_programmed_already(data);
1625 if (err < 0)
1626 goto cleanup;
1627
1628 initialization_required = !err;
1629 }
1630
1631 if (initialization_required) {
1632 /* Populate the regmap cache in preparation for "cache only" */
1633 err = si5341_read_settings(data);
1634 if (err < 0)
1635 goto cleanup;
1636
1637 err = si5341_send_preamble(data);
1638 if (err < 0)
1639 goto cleanup;
1640
1641 /*
1642 * We intend to send all 'final' register values in a single
1643 * transaction. So cache all register writes until we're done
1644 * configuring.
1645 */
1646 regcache_cache_only(data->regmap, true);
1647
1648 /* Write the configuration pairs from the firmware blob */
1649 err = si5341_write_multiple(data, si5341_reg_defaults,
1650 ARRAY_SIZE(si5341_reg_defaults));
1651 if (err < 0)
1652 goto cleanup;
1653 }
1654
1655 /* Input must be up and running at this point */
1656 err = si5341_clk_select_active_input(data);
1657 if (err < 0)
1658 goto cleanup;
1659
1660 if (initialization_required) {
1661 /* PLL configuration is required */
1662 err = si5341_initialize_pll(data);
1663 if (err < 0)
1664 goto cleanup;
1665 }
1666
1667 /* Register the PLL */
1668 init.parent_names = data->input_clk_name;
1669 init.num_parents = SI5341_NUM_INPUTS;
1670 init.ops = &si5341_clk_ops;
1671 init.flags = 0;
1672 data->hw.init = &init;
1673
1674 err = devm_clk_hw_register(&client->dev, &data->hw);
1675 if (err) {
1676 dev_err(&client->dev, "clock registration failed\n");
1677 goto cleanup;
1678 }
1679
1680 init.num_parents = 1;
1681 init.parent_names = &root_clock_name;
1682 init.ops = &si5341_synth_clk_ops;
1683 for (i = 0; i < data->num_synth; ++i) {
1684 synth_clock_names[i] = devm_kasprintf(&client->dev, GFP_KERNEL,
1685 "%s.N%u", client->dev.of_node->name, i);
1686 if (!synth_clock_names[i]) {
1687 err = -ENOMEM;
1688 goto free_clk_names;
1689 }
1690 init.name = synth_clock_names[i];
1691 data->synth[i].index = i;
1692 data->synth[i].data = data;
1693 data->synth[i].hw.init = &init;
1694 err = devm_clk_hw_register(&client->dev, &data->synth[i].hw);
1695 if (err) {
1696 dev_err(&client->dev,
1697 "synth N%u registration failed\n", i);
1698 goto free_clk_names;
1699 }
1700 }
1701
1702 init.num_parents = data->num_synth;
1703 init.parent_names = synth_clock_names;
1704 init.ops = &si5341_output_clk_ops;
1705 for (i = 0; i < data->num_outputs; ++i) {
1706 init.name = kasprintf(GFP_KERNEL, "%s.%d",
1707 client->dev.of_node->name, i);
1708 if (!init.name) {
1709 err = -ENOMEM;
1710 goto free_clk_names;
1711 }
1712 init.flags = config[i].synth_master ? CLK_SET_RATE_PARENT : 0;
1713 data->clk[i].index = i;
1714 data->clk[i].data = data;
1715 data->clk[i].hw.init = &init;
1716 if (config[i].out_format_drv_bits & 0x07) {
1717 regmap_write(data->regmap,
1718 SI5341_OUT_FORMAT(&data->clk[i]),
1719 config[i].out_format_drv_bits);
1720 regmap_write(data->regmap,
1721 SI5341_OUT_CM(&data->clk[i]),
1722 config[i].out_cm_ampl_bits);
1723 regmap_update_bits(data->regmap,
1724 SI5341_OUT_MUX_SEL(&data->clk[i]),
1725 SI5341_OUT_MUX_VDD_SEL_MASK,
1726 config[i].vdd_sel_bits);
1727 }
1728 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw);
1729 kfree(init.name); /* clock framework made a copy of the name */
1730 if (err) {
1731 dev_err(&client->dev,
1732 "output %u registration failed\n", i);
1733 goto free_clk_names;
1734 }
1735 if (config[i].always_on)
1736 clk_prepare(data->clk[i].hw.clk);
1737 }
1738
1739 err = devm_of_clk_add_hw_provider(&client->dev, of_clk_si5341_get,
1740 data);
1741 if (err) {
1742 dev_err(&client->dev, "unable to add clk provider\n");
1743 goto free_clk_names;
1744 }
1745
1746 if (initialization_required) {
1747 /* Synchronize */
1748 regcache_cache_only(data->regmap, false);
1749 err = regcache_sync(data->regmap);
1750 if (err < 0)
1751 goto free_clk_names;
1752
1753 err = si5341_finalize_defaults(data);
1754 if (err < 0)
1755 goto free_clk_names;
1756 }
1757
1758 /* wait for device to report input clock present and PLL lock */
1759 err = regmap_read_poll_timeout(data->regmap, SI5341_STATUS, status,
1760 !(status & (SI5341_STATUS_LOSREF | SI5341_STATUS_LOL)),
1761 10000, 250000);
1762 if (err) {
1763 dev_err(&client->dev, "Error waiting for input clock or PLL lock\n");
1764 goto free_clk_names;
1765 }
1766
1767 /* clear sticky alarm bits from initialization */
1768 err = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0);
1769 if (err) {
1770 dev_err(&client->dev, "unable to clear sticky status\n");
1771 goto free_clk_names;
1772 }
1773
1774 err = sysfs_create_files(&client->dev.kobj, si5341_attributes);
1775 if (err)
1776 dev_err(&client->dev, "unable to create sysfs files\n");
1777
1778 free_clk_names:
1779 /* Free the names, clk framework makes copies */
1780 for (i = 0; i < data->num_synth; ++i)
1781 devm_kfree(&client->dev, (void *)synth_clock_names[i]);
1782
1783 cleanup:
1784 if (err) {
1785 for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) {
1786 if (data->clk[i].vddo_reg)
1787 regulator_disable(data->clk[i].vddo_reg);
1788 }
1789 }
1790 return err;
1791 }
1792
si5341_remove(struct i2c_client * client)1793 static int si5341_remove(struct i2c_client *client)
1794 {
1795 struct clk_si5341 *data = i2c_get_clientdata(client);
1796 int i;
1797
1798 sysfs_remove_files(&client->dev.kobj, si5341_attributes);
1799
1800 for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) {
1801 if (data->clk[i].vddo_reg)
1802 regulator_disable(data->clk[i].vddo_reg);
1803 }
1804
1805 return 0;
1806 }
1807
1808 static const struct i2c_device_id si5341_id[] = {
1809 { "si5340", 0 },
1810 { "si5341", 1 },
1811 { "si5342", 2 },
1812 { "si5344", 4 },
1813 { "si5345", 5 },
1814 { }
1815 };
1816 MODULE_DEVICE_TABLE(i2c, si5341_id);
1817
1818 static const struct of_device_id clk_si5341_of_match[] = {
1819 { .compatible = "silabs,si5340" },
1820 { .compatible = "silabs,si5341" },
1821 { .compatible = "silabs,si5342" },
1822 { .compatible = "silabs,si5344" },
1823 { .compatible = "silabs,si5345" },
1824 { }
1825 };
1826 MODULE_DEVICE_TABLE(of, clk_si5341_of_match);
1827
1828 static struct i2c_driver si5341_driver = {
1829 .driver = {
1830 .name = "si5341",
1831 .of_match_table = clk_si5341_of_match,
1832 },
1833 .probe = si5341_probe,
1834 .remove = si5341_remove,
1835 .id_table = si5341_id,
1836 };
1837 module_i2c_driver(si5341_driver);
1838
1839 MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
1840 MODULE_DESCRIPTION("Si5341 driver");
1841 MODULE_LICENSE("GPL");
1842