1 /*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/iopoll.h>
27 #include <linux/module.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/regulator/consumer.h>
31
32 #include <video/display_timing.h>
33 #include <video/of_display_timing.h>
34 #include <video/videomode.h>
35
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_device.h>
38 #include <drm/drm_mipi_dsi.h>
39 #include <drm/drm_panel.h>
40
41 /**
42 * @modes: Pointer to array of fixed modes appropriate for this panel. If
43 * only one mode then this can just be the address of this the mode.
44 * NOTE: cannot be used with "timings" and also if this is specified
45 * then you cannot override the mode in the device tree.
46 * @num_modes: Number of elements in modes array.
47 * @timings: Pointer to array of display timings. NOTE: cannot be used with
48 * "modes" and also these will be used to validate a device tree
49 * override if one is present.
50 * @num_timings: Number of elements in timings array.
51 * @bpc: Bits per color.
52 * @size: Structure containing the physical size of this panel.
53 * @delay: Structure containing various delay values for this panel.
54 * @bus_format: See MEDIA_BUS_FMT_... defines.
55 * @bus_flags: See DRM_BUS_FLAG_... defines.
56 */
57 struct panel_desc {
58 const struct drm_display_mode *modes;
59 unsigned int num_modes;
60 const struct display_timing *timings;
61 unsigned int num_timings;
62
63 unsigned int bpc;
64
65 /**
66 * @width: width (in millimeters) of the panel's active display area
67 * @height: height (in millimeters) of the panel's active display area
68 */
69 struct {
70 unsigned int width;
71 unsigned int height;
72 } size;
73
74 /**
75 * @prepare: the time (in milliseconds) that it takes for the panel to
76 * become ready and start receiving video data
77 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
78 * Plug Detect isn't used.
79 * @enable: the time (in milliseconds) that it takes for the panel to
80 * display the first valid frame after starting to receive
81 * video data
82 * @disable: the time (in milliseconds) that it takes for the panel to
83 * turn the display off (no content is visible)
84 * @unprepare: the time (in milliseconds) that it takes for the panel
85 * to power itself down completely
86 */
87 struct {
88 unsigned int prepare;
89 unsigned int hpd_absent_delay;
90 unsigned int enable;
91 unsigned int disable;
92 unsigned int unprepare;
93 } delay;
94
95 u32 bus_format;
96 u32 bus_flags;
97 int connector_type;
98 };
99
100 struct panel_simple {
101 struct drm_panel base;
102 bool prepared;
103 bool enabled;
104 bool no_hpd;
105
106 const struct panel_desc *desc;
107
108 struct regulator *supply;
109 struct i2c_adapter *ddc;
110
111 struct gpio_desc *enable_gpio;
112 struct gpio_desc *hpd_gpio;
113
114 struct drm_display_mode override_mode;
115
116 enum drm_panel_orientation orientation;
117 };
118
to_panel_simple(struct drm_panel * panel)119 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
120 {
121 return container_of(panel, struct panel_simple, base);
122 }
123
panel_simple_get_timings_modes(struct panel_simple * panel,struct drm_connector * connector)124 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
125 struct drm_connector *connector)
126 {
127 struct drm_display_mode *mode;
128 unsigned int i, num = 0;
129
130 for (i = 0; i < panel->desc->num_timings; i++) {
131 const struct display_timing *dt = &panel->desc->timings[i];
132 struct videomode vm;
133
134 videomode_from_timing(dt, &vm);
135 mode = drm_mode_create(connector->dev);
136 if (!mode) {
137 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
138 dt->hactive.typ, dt->vactive.typ);
139 continue;
140 }
141
142 drm_display_mode_from_videomode(&vm, mode);
143
144 mode->type |= DRM_MODE_TYPE_DRIVER;
145
146 if (panel->desc->num_timings == 1)
147 mode->type |= DRM_MODE_TYPE_PREFERRED;
148
149 drm_mode_probed_add(connector, mode);
150 num++;
151 }
152
153 return num;
154 }
155
panel_simple_get_display_modes(struct panel_simple * panel,struct drm_connector * connector)156 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
157 struct drm_connector *connector)
158 {
159 struct drm_display_mode *mode;
160 unsigned int i, num = 0;
161
162 for (i = 0; i < panel->desc->num_modes; i++) {
163 const struct drm_display_mode *m = &panel->desc->modes[i];
164
165 mode = drm_mode_duplicate(connector->dev, m);
166 if (!mode) {
167 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
168 m->hdisplay, m->vdisplay,
169 drm_mode_vrefresh(m));
170 continue;
171 }
172
173 mode->type |= DRM_MODE_TYPE_DRIVER;
174
175 if (panel->desc->num_modes == 1)
176 mode->type |= DRM_MODE_TYPE_PREFERRED;
177
178 drm_mode_set_name(mode);
179
180 drm_mode_probed_add(connector, mode);
181 num++;
182 }
183
184 return num;
185 }
186
panel_simple_get_non_edid_modes(struct panel_simple * panel,struct drm_connector * connector)187 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
188 struct drm_connector *connector)
189 {
190 struct drm_display_mode *mode;
191 bool has_override = panel->override_mode.type;
192 unsigned int num = 0;
193
194 if (!panel->desc)
195 return 0;
196
197 if (has_override) {
198 mode = drm_mode_duplicate(connector->dev,
199 &panel->override_mode);
200 if (mode) {
201 drm_mode_probed_add(connector, mode);
202 num = 1;
203 } else {
204 dev_err(panel->base.dev, "failed to add override mode\n");
205 }
206 }
207
208 /* Only add timings if override was not there or failed to validate */
209 if (num == 0 && panel->desc->num_timings)
210 num = panel_simple_get_timings_modes(panel, connector);
211
212 /*
213 * Only add fixed modes if timings/override added no mode.
214 *
215 * We should only ever have either the display timings specified
216 * or a fixed mode. Anything else is rather bogus.
217 */
218 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
219 if (num == 0)
220 num = panel_simple_get_display_modes(panel, connector);
221
222 connector->display_info.bpc = panel->desc->bpc;
223 connector->display_info.width_mm = panel->desc->size.width;
224 connector->display_info.height_mm = panel->desc->size.height;
225 if (panel->desc->bus_format)
226 drm_display_info_set_bus_formats(&connector->display_info,
227 &panel->desc->bus_format, 1);
228 connector->display_info.bus_flags = panel->desc->bus_flags;
229
230 return num;
231 }
232
panel_simple_disable(struct drm_panel * panel)233 static int panel_simple_disable(struct drm_panel *panel)
234 {
235 struct panel_simple *p = to_panel_simple(panel);
236
237 if (!p->enabled)
238 return 0;
239
240 if (p->desc->delay.disable)
241 msleep(p->desc->delay.disable);
242
243 p->enabled = false;
244
245 return 0;
246 }
247
panel_simple_unprepare(struct drm_panel * panel)248 static int panel_simple_unprepare(struct drm_panel *panel)
249 {
250 struct panel_simple *p = to_panel_simple(panel);
251
252 if (!p->prepared)
253 return 0;
254
255 gpiod_set_value_cansleep(p->enable_gpio, 0);
256
257 regulator_disable(p->supply);
258
259 if (p->desc->delay.unprepare)
260 msleep(p->desc->delay.unprepare);
261
262 p->prepared = false;
263
264 return 0;
265 }
266
panel_simple_get_hpd_gpio(struct device * dev,struct panel_simple * p,bool from_probe)267 static int panel_simple_get_hpd_gpio(struct device *dev,
268 struct panel_simple *p, bool from_probe)
269 {
270 int err;
271
272 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
273 if (IS_ERR(p->hpd_gpio)) {
274 err = PTR_ERR(p->hpd_gpio);
275
276 /*
277 * If we're called from probe we won't consider '-EPROBE_DEFER'
278 * to be an error--we'll leave the error code in "hpd_gpio".
279 * When we try to use it we'll try again. This allows for
280 * circular dependencies where the component providing the
281 * hpd gpio needs the panel to init before probing.
282 */
283 if (err != -EPROBE_DEFER || !from_probe) {
284 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err);
285 return err;
286 }
287 }
288
289 return 0;
290 }
291
panel_simple_prepare(struct drm_panel * panel)292 static int panel_simple_prepare(struct drm_panel *panel)
293 {
294 struct panel_simple *p = to_panel_simple(panel);
295 unsigned int delay;
296 int err;
297 int hpd_asserted;
298
299 if (p->prepared)
300 return 0;
301
302 err = regulator_enable(p->supply);
303 if (err < 0) {
304 dev_err(panel->dev, "failed to enable supply: %d\n", err);
305 return err;
306 }
307
308 gpiod_set_value_cansleep(p->enable_gpio, 1);
309
310 delay = p->desc->delay.prepare;
311 if (p->no_hpd)
312 delay += p->desc->delay.hpd_absent_delay;
313 if (delay)
314 msleep(delay);
315
316 if (p->hpd_gpio) {
317 if (IS_ERR(p->hpd_gpio)) {
318 err = panel_simple_get_hpd_gpio(panel->dev, p, false);
319 if (err)
320 return err;
321 }
322
323 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio,
324 hpd_asserted, hpd_asserted,
325 1000, 2000000);
326 if (hpd_asserted < 0)
327 err = hpd_asserted;
328
329 if (err) {
330 dev_err(panel->dev,
331 "error waiting for hpd GPIO: %d\n", err);
332 return err;
333 }
334 }
335
336 p->prepared = true;
337
338 return 0;
339 }
340
panel_simple_enable(struct drm_panel * panel)341 static int panel_simple_enable(struct drm_panel *panel)
342 {
343 struct panel_simple *p = to_panel_simple(panel);
344
345 if (p->enabled)
346 return 0;
347
348 if (p->desc->delay.enable)
349 msleep(p->desc->delay.enable);
350
351 p->enabled = true;
352
353 return 0;
354 }
355
panel_simple_get_modes(struct drm_panel * panel,struct drm_connector * connector)356 static int panel_simple_get_modes(struct drm_panel *panel,
357 struct drm_connector *connector)
358 {
359 struct panel_simple *p = to_panel_simple(panel);
360 int num = 0;
361
362 /* probe EDID if a DDC bus is available */
363 if (p->ddc) {
364 struct edid *edid = drm_get_edid(connector, p->ddc);
365
366 drm_connector_update_edid_property(connector, edid);
367 if (edid) {
368 num += drm_add_edid_modes(connector, edid);
369 kfree(edid);
370 }
371 }
372
373 /* add hard-coded panel modes */
374 num += panel_simple_get_non_edid_modes(p, connector);
375
376 /* set up connector's "panel orientation" property */
377 drm_connector_set_panel_orientation(connector, p->orientation);
378
379 return num;
380 }
381
panel_simple_get_timings(struct drm_panel * panel,unsigned int num_timings,struct display_timing * timings)382 static int panel_simple_get_timings(struct drm_panel *panel,
383 unsigned int num_timings,
384 struct display_timing *timings)
385 {
386 struct panel_simple *p = to_panel_simple(panel);
387 unsigned int i;
388
389 if (p->desc->num_timings < num_timings)
390 num_timings = p->desc->num_timings;
391
392 if (timings)
393 for (i = 0; i < num_timings; i++)
394 timings[i] = p->desc->timings[i];
395
396 return p->desc->num_timings;
397 }
398
399 static const struct drm_panel_funcs panel_simple_funcs = {
400 .disable = panel_simple_disable,
401 .unprepare = panel_simple_unprepare,
402 .prepare = panel_simple_prepare,
403 .enable = panel_simple_enable,
404 .get_modes = panel_simple_get_modes,
405 .get_timings = panel_simple_get_timings,
406 };
407
408 static struct panel_desc panel_dpi;
409
panel_dpi_probe(struct device * dev,struct panel_simple * panel)410 static int panel_dpi_probe(struct device *dev,
411 struct panel_simple *panel)
412 {
413 struct display_timing *timing;
414 const struct device_node *np;
415 struct panel_desc *desc;
416 unsigned int bus_flags;
417 struct videomode vm;
418 int ret;
419
420 np = dev->of_node;
421 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
422 if (!desc)
423 return -ENOMEM;
424
425 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
426 if (!timing)
427 return -ENOMEM;
428
429 ret = of_get_display_timing(np, "panel-timing", timing);
430 if (ret < 0) {
431 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
432 np);
433 return ret;
434 }
435
436 desc->timings = timing;
437 desc->num_timings = 1;
438
439 of_property_read_u32(np, "width-mm", &desc->size.width);
440 of_property_read_u32(np, "height-mm", &desc->size.height);
441
442 /* Extract bus_flags from display_timing */
443 bus_flags = 0;
444 vm.flags = timing->flags;
445 drm_bus_flags_from_videomode(&vm, &bus_flags);
446 desc->bus_flags = bus_flags;
447
448 /* We do not know the connector for the DT node, so guess it */
449 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
450
451 panel->desc = desc;
452
453 return 0;
454 }
455
456 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
457 (to_check->field.typ >= bounds->field.min && \
458 to_check->field.typ <= bounds->field.max)
panel_simple_parse_panel_timing_node(struct device * dev,struct panel_simple * panel,const struct display_timing * ot)459 static void panel_simple_parse_panel_timing_node(struct device *dev,
460 struct panel_simple *panel,
461 const struct display_timing *ot)
462 {
463 const struct panel_desc *desc = panel->desc;
464 struct videomode vm;
465 unsigned int i;
466
467 if (WARN_ON(desc->num_modes)) {
468 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
469 return;
470 }
471 if (WARN_ON(!desc->num_timings)) {
472 dev_err(dev, "Reject override mode: no timings specified\n");
473 return;
474 }
475
476 for (i = 0; i < panel->desc->num_timings; i++) {
477 const struct display_timing *dt = &panel->desc->timings[i];
478
479 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
480 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
481 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
482 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
483 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
484 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
485 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
486 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
487 continue;
488
489 if (ot->flags != dt->flags)
490 continue;
491
492 videomode_from_timing(ot, &vm);
493 drm_display_mode_from_videomode(&vm, &panel->override_mode);
494 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
495 DRM_MODE_TYPE_PREFERRED;
496 break;
497 }
498
499 if (WARN_ON(!panel->override_mode.type))
500 dev_err(dev, "Reject override mode: No display_timing found\n");
501 }
502
panel_simple_probe(struct device * dev,const struct panel_desc * desc)503 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
504 {
505 struct panel_simple *panel;
506 struct display_timing dt;
507 struct device_node *ddc;
508 int connector_type;
509 u32 bus_flags;
510 int err;
511
512 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
513 if (!panel)
514 return -ENOMEM;
515
516 panel->enabled = false;
517 panel->prepared = false;
518 panel->desc = desc;
519
520 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
521 if (!panel->no_hpd) {
522 err = panel_simple_get_hpd_gpio(dev, panel, true);
523 if (err)
524 return err;
525 }
526
527 panel->supply = devm_regulator_get(dev, "power");
528 if (IS_ERR(panel->supply))
529 return PTR_ERR(panel->supply);
530
531 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
532 GPIOD_OUT_LOW);
533 if (IS_ERR(panel->enable_gpio)) {
534 err = PTR_ERR(panel->enable_gpio);
535 if (err != -EPROBE_DEFER)
536 dev_err(dev, "failed to request GPIO: %d\n", err);
537 return err;
538 }
539
540 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
541 if (err) {
542 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
543 return err;
544 }
545
546 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
547 if (ddc) {
548 panel->ddc = of_find_i2c_adapter_by_node(ddc);
549 of_node_put(ddc);
550
551 if (!panel->ddc)
552 return -EPROBE_DEFER;
553 }
554
555 if (desc == &panel_dpi) {
556 /* Handle the generic panel-dpi binding */
557 err = panel_dpi_probe(dev, panel);
558 if (err)
559 goto free_ddc;
560 desc = panel->desc;
561 } else {
562 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
563 panel_simple_parse_panel_timing_node(dev, panel, &dt);
564 }
565
566 connector_type = desc->connector_type;
567 /* Catch common mistakes for panels. */
568 switch (connector_type) {
569 case 0:
570 dev_warn(dev, "Specify missing connector_type\n");
571 connector_type = DRM_MODE_CONNECTOR_DPI;
572 break;
573 case DRM_MODE_CONNECTOR_LVDS:
574 WARN_ON(desc->bus_flags &
575 ~(DRM_BUS_FLAG_DE_LOW |
576 DRM_BUS_FLAG_DE_HIGH |
577 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
578 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
579 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
580 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
581 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
582 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
583 desc->bpc != 6);
584 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
585 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
586 desc->bpc != 8);
587 break;
588 case DRM_MODE_CONNECTOR_eDP:
589 if (desc->bus_format == 0)
590 dev_warn(dev, "Specify missing bus_format\n");
591 if (desc->bpc != 6 && desc->bpc != 8)
592 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
593 break;
594 case DRM_MODE_CONNECTOR_DSI:
595 if (desc->bpc != 6 && desc->bpc != 8)
596 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
597 break;
598 case DRM_MODE_CONNECTOR_DPI:
599 bus_flags = DRM_BUS_FLAG_DE_LOW |
600 DRM_BUS_FLAG_DE_HIGH |
601 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
602 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
603 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
604 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
605 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
606 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
607 if (desc->bus_flags & ~bus_flags)
608 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
609 if (!(desc->bus_flags & bus_flags))
610 dev_warn(dev, "Specify missing bus_flags\n");
611 if (desc->bus_format == 0)
612 dev_warn(dev, "Specify missing bus_format\n");
613 if (desc->bpc != 6 && desc->bpc != 8)
614 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
615 break;
616 default:
617 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
618 connector_type = DRM_MODE_CONNECTOR_DPI;
619 break;
620 }
621
622 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
623
624 err = drm_panel_of_backlight(&panel->base);
625 if (err)
626 goto free_ddc;
627
628 drm_panel_add(&panel->base);
629
630 dev_set_drvdata(dev, panel);
631
632 return 0;
633
634 free_ddc:
635 if (panel->ddc)
636 put_device(&panel->ddc->dev);
637
638 return err;
639 }
640
panel_simple_remove(struct device * dev)641 static int panel_simple_remove(struct device *dev)
642 {
643 struct panel_simple *panel = dev_get_drvdata(dev);
644
645 drm_panel_remove(&panel->base);
646 drm_panel_disable(&panel->base);
647 drm_panel_unprepare(&panel->base);
648
649 if (panel->ddc)
650 put_device(&panel->ddc->dev);
651
652 return 0;
653 }
654
panel_simple_shutdown(struct device * dev)655 static void panel_simple_shutdown(struct device *dev)
656 {
657 struct panel_simple *panel = dev_get_drvdata(dev);
658
659 drm_panel_disable(&panel->base);
660 drm_panel_unprepare(&panel->base);
661 }
662
663 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
664 .clock = 71100,
665 .hdisplay = 1280,
666 .hsync_start = 1280 + 40,
667 .hsync_end = 1280 + 40 + 80,
668 .htotal = 1280 + 40 + 80 + 40,
669 .vdisplay = 800,
670 .vsync_start = 800 + 3,
671 .vsync_end = 800 + 3 + 10,
672 .vtotal = 800 + 3 + 10 + 10,
673 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
674 };
675
676 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
677 .modes = &ire_am_1280800n3tzqw_t00h_mode,
678 .num_modes = 1,
679 .bpc = 8,
680 .size = {
681 .width = 217,
682 .height = 136,
683 },
684 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
685 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
686 .connector_type = DRM_MODE_CONNECTOR_LVDS,
687 };
688
689 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
690 .clock = 9000,
691 .hdisplay = 480,
692 .hsync_start = 480 + 2,
693 .hsync_end = 480 + 2 + 41,
694 .htotal = 480 + 2 + 41 + 2,
695 .vdisplay = 272,
696 .vsync_start = 272 + 2,
697 .vsync_end = 272 + 2 + 10,
698 .vtotal = 272 + 2 + 10 + 2,
699 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
700 };
701
702 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
703 .modes = &ire_am_480272h3tmqw_t01h_mode,
704 .num_modes = 1,
705 .bpc = 8,
706 .size = {
707 .width = 99,
708 .height = 58,
709 },
710 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
711 };
712
713 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
714 .clock = 33333,
715 .hdisplay = 800,
716 .hsync_start = 800 + 0,
717 .hsync_end = 800 + 0 + 255,
718 .htotal = 800 + 0 + 255 + 0,
719 .vdisplay = 480,
720 .vsync_start = 480 + 2,
721 .vsync_end = 480 + 2 + 45,
722 .vtotal = 480 + 2 + 45 + 0,
723 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
724 };
725
726 static const struct panel_desc ampire_am800480r3tmqwa1h = {
727 .modes = &ire_am800480r3tmqwa1h_mode,
728 .num_modes = 1,
729 .bpc = 6,
730 .size = {
731 .width = 152,
732 .height = 91,
733 },
734 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
735 };
736
737 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
738 .pixelclock = { 26400000, 33300000, 46800000 },
739 .hactive = { 800, 800, 800 },
740 .hfront_porch = { 16, 210, 354 },
741 .hback_porch = { 45, 36, 6 },
742 .hsync_len = { 1, 10, 40 },
743 .vactive = { 480, 480, 480 },
744 .vfront_porch = { 7, 22, 147 },
745 .vback_porch = { 22, 13, 3 },
746 .vsync_len = { 1, 10, 20 },
747 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
748 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
749 };
750
751 static const struct panel_desc armadeus_st0700_adapt = {
752 .timings = &santek_st0700i5y_rbslw_f_timing,
753 .num_timings = 1,
754 .bpc = 6,
755 .size = {
756 .width = 154,
757 .height = 86,
758 },
759 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
760 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
761 };
762
763 static const struct drm_display_mode auo_b101aw03_mode = {
764 .clock = 51450,
765 .hdisplay = 1024,
766 .hsync_start = 1024 + 156,
767 .hsync_end = 1024 + 156 + 8,
768 .htotal = 1024 + 156 + 8 + 156,
769 .vdisplay = 600,
770 .vsync_start = 600 + 16,
771 .vsync_end = 600 + 16 + 6,
772 .vtotal = 600 + 16 + 6 + 16,
773 };
774
775 static const struct panel_desc auo_b101aw03 = {
776 .modes = &auo_b101aw03_mode,
777 .num_modes = 1,
778 .bpc = 6,
779 .size = {
780 .width = 223,
781 .height = 125,
782 },
783 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
784 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
785 .connector_type = DRM_MODE_CONNECTOR_LVDS,
786 };
787
788 static const struct display_timing auo_b101ean01_timing = {
789 .pixelclock = { 65300000, 72500000, 75000000 },
790 .hactive = { 1280, 1280, 1280 },
791 .hfront_porch = { 18, 119, 119 },
792 .hback_porch = { 21, 21, 21 },
793 .hsync_len = { 32, 32, 32 },
794 .vactive = { 800, 800, 800 },
795 .vfront_porch = { 4, 4, 4 },
796 .vback_porch = { 8, 8, 8 },
797 .vsync_len = { 18, 20, 20 },
798 };
799
800 static const struct panel_desc auo_b101ean01 = {
801 .timings = &auo_b101ean01_timing,
802 .num_timings = 1,
803 .bpc = 6,
804 .size = {
805 .width = 217,
806 .height = 136,
807 },
808 };
809
810 static const struct drm_display_mode auo_b101xtn01_mode = {
811 .clock = 72000,
812 .hdisplay = 1366,
813 .hsync_start = 1366 + 20,
814 .hsync_end = 1366 + 20 + 70,
815 .htotal = 1366 + 20 + 70,
816 .vdisplay = 768,
817 .vsync_start = 768 + 14,
818 .vsync_end = 768 + 14 + 42,
819 .vtotal = 768 + 14 + 42,
820 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
821 };
822
823 static const struct panel_desc auo_b101xtn01 = {
824 .modes = &auo_b101xtn01_mode,
825 .num_modes = 1,
826 .bpc = 6,
827 .size = {
828 .width = 223,
829 .height = 125,
830 },
831 };
832
833 static const struct drm_display_mode auo_b116xak01_mode = {
834 .clock = 69300,
835 .hdisplay = 1366,
836 .hsync_start = 1366 + 48,
837 .hsync_end = 1366 + 48 + 32,
838 .htotal = 1366 + 48 + 32 + 10,
839 .vdisplay = 768,
840 .vsync_start = 768 + 4,
841 .vsync_end = 768 + 4 + 6,
842 .vtotal = 768 + 4 + 6 + 15,
843 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
844 };
845
846 static const struct panel_desc auo_b116xak01 = {
847 .modes = &auo_b116xak01_mode,
848 .num_modes = 1,
849 .bpc = 6,
850 .size = {
851 .width = 256,
852 .height = 144,
853 },
854 .delay = {
855 .hpd_absent_delay = 200,
856 },
857 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
858 .connector_type = DRM_MODE_CONNECTOR_eDP,
859 };
860
861 static const struct drm_display_mode auo_b116xw03_mode = {
862 .clock = 70589,
863 .hdisplay = 1366,
864 .hsync_start = 1366 + 40,
865 .hsync_end = 1366 + 40 + 40,
866 .htotal = 1366 + 40 + 40 + 32,
867 .vdisplay = 768,
868 .vsync_start = 768 + 10,
869 .vsync_end = 768 + 10 + 12,
870 .vtotal = 768 + 10 + 12 + 6,
871 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
872 };
873
874 static const struct panel_desc auo_b116xw03 = {
875 .modes = &auo_b116xw03_mode,
876 .num_modes = 1,
877 .bpc = 6,
878 .size = {
879 .width = 256,
880 .height = 144,
881 },
882 .delay = {
883 .enable = 400,
884 },
885 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
886 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
887 .connector_type = DRM_MODE_CONNECTOR_eDP,
888 };
889
890 static const struct drm_display_mode auo_b133xtn01_mode = {
891 .clock = 69500,
892 .hdisplay = 1366,
893 .hsync_start = 1366 + 48,
894 .hsync_end = 1366 + 48 + 32,
895 .htotal = 1366 + 48 + 32 + 20,
896 .vdisplay = 768,
897 .vsync_start = 768 + 3,
898 .vsync_end = 768 + 3 + 6,
899 .vtotal = 768 + 3 + 6 + 13,
900 };
901
902 static const struct panel_desc auo_b133xtn01 = {
903 .modes = &auo_b133xtn01_mode,
904 .num_modes = 1,
905 .bpc = 6,
906 .size = {
907 .width = 293,
908 .height = 165,
909 },
910 };
911
912 static const struct drm_display_mode auo_b133htn01_mode = {
913 .clock = 150660,
914 .hdisplay = 1920,
915 .hsync_start = 1920 + 172,
916 .hsync_end = 1920 + 172 + 80,
917 .htotal = 1920 + 172 + 80 + 60,
918 .vdisplay = 1080,
919 .vsync_start = 1080 + 25,
920 .vsync_end = 1080 + 25 + 10,
921 .vtotal = 1080 + 25 + 10 + 10,
922 };
923
924 static const struct panel_desc auo_b133htn01 = {
925 .modes = &auo_b133htn01_mode,
926 .num_modes = 1,
927 .bpc = 6,
928 .size = {
929 .width = 293,
930 .height = 165,
931 },
932 .delay = {
933 .prepare = 105,
934 .enable = 20,
935 .unprepare = 50,
936 },
937 };
938
939 static const struct display_timing auo_g070vvn01_timings = {
940 .pixelclock = { 33300000, 34209000, 45000000 },
941 .hactive = { 800, 800, 800 },
942 .hfront_porch = { 20, 40, 200 },
943 .hback_porch = { 87, 40, 1 },
944 .hsync_len = { 1, 48, 87 },
945 .vactive = { 480, 480, 480 },
946 .vfront_porch = { 5, 13, 200 },
947 .vback_porch = { 31, 31, 29 },
948 .vsync_len = { 1, 1, 3 },
949 };
950
951 static const struct panel_desc auo_g070vvn01 = {
952 .timings = &auo_g070vvn01_timings,
953 .num_timings = 1,
954 .bpc = 8,
955 .size = {
956 .width = 152,
957 .height = 91,
958 },
959 .delay = {
960 .prepare = 200,
961 .enable = 50,
962 .disable = 50,
963 .unprepare = 1000,
964 },
965 };
966
967 static const struct drm_display_mode auo_g101evn010_mode = {
968 .clock = 68930,
969 .hdisplay = 1280,
970 .hsync_start = 1280 + 82,
971 .hsync_end = 1280 + 82 + 2,
972 .htotal = 1280 + 82 + 2 + 84,
973 .vdisplay = 800,
974 .vsync_start = 800 + 8,
975 .vsync_end = 800 + 8 + 2,
976 .vtotal = 800 + 8 + 2 + 6,
977 };
978
979 static const struct panel_desc auo_g101evn010 = {
980 .modes = &auo_g101evn010_mode,
981 .num_modes = 1,
982 .bpc = 6,
983 .size = {
984 .width = 216,
985 .height = 135,
986 },
987 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
988 .connector_type = DRM_MODE_CONNECTOR_LVDS,
989 };
990
991 static const struct drm_display_mode auo_g104sn02_mode = {
992 .clock = 40000,
993 .hdisplay = 800,
994 .hsync_start = 800 + 40,
995 .hsync_end = 800 + 40 + 216,
996 .htotal = 800 + 40 + 216 + 128,
997 .vdisplay = 600,
998 .vsync_start = 600 + 10,
999 .vsync_end = 600 + 10 + 35,
1000 .vtotal = 600 + 10 + 35 + 2,
1001 };
1002
1003 static const struct panel_desc auo_g104sn02 = {
1004 .modes = &auo_g104sn02_mode,
1005 .num_modes = 1,
1006 .bpc = 8,
1007 .size = {
1008 .width = 211,
1009 .height = 158,
1010 },
1011 };
1012
1013 static const struct display_timing auo_g121ean01_timing = {
1014 .pixelclock = { 60000000, 74400000, 90000000 },
1015 .hactive = { 1280, 1280, 1280 },
1016 .hfront_porch = { 20, 50, 100 },
1017 .hback_porch = { 20, 50, 100 },
1018 .hsync_len = { 30, 100, 200 },
1019 .vactive = { 800, 800, 800 },
1020 .vfront_porch = { 2, 10, 25 },
1021 .vback_porch = { 2, 10, 25 },
1022 .vsync_len = { 4, 18, 50 },
1023 };
1024
1025 static const struct panel_desc auo_g121ean01 = {
1026 .timings = &auo_g121ean01_timing,
1027 .num_timings = 1,
1028 .bpc = 8,
1029 .size = {
1030 .width = 261,
1031 .height = 163,
1032 },
1033 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1034 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1035 };
1036
1037 static const struct display_timing auo_g133han01_timings = {
1038 .pixelclock = { 134000000, 141200000, 149000000 },
1039 .hactive = { 1920, 1920, 1920 },
1040 .hfront_porch = { 39, 58, 77 },
1041 .hback_porch = { 59, 88, 117 },
1042 .hsync_len = { 28, 42, 56 },
1043 .vactive = { 1080, 1080, 1080 },
1044 .vfront_porch = { 3, 8, 11 },
1045 .vback_porch = { 5, 14, 19 },
1046 .vsync_len = { 4, 14, 19 },
1047 };
1048
1049 static const struct panel_desc auo_g133han01 = {
1050 .timings = &auo_g133han01_timings,
1051 .num_timings = 1,
1052 .bpc = 8,
1053 .size = {
1054 .width = 293,
1055 .height = 165,
1056 },
1057 .delay = {
1058 .prepare = 200,
1059 .enable = 50,
1060 .disable = 50,
1061 .unprepare = 1000,
1062 },
1063 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1064 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1065 };
1066
1067 static const struct drm_display_mode auo_g156xtn01_mode = {
1068 .clock = 76000,
1069 .hdisplay = 1366,
1070 .hsync_start = 1366 + 33,
1071 .hsync_end = 1366 + 33 + 67,
1072 .htotal = 1560,
1073 .vdisplay = 768,
1074 .vsync_start = 768 + 4,
1075 .vsync_end = 768 + 4 + 4,
1076 .vtotal = 806,
1077 };
1078
1079 static const struct panel_desc auo_g156xtn01 = {
1080 .modes = &auo_g156xtn01_mode,
1081 .num_modes = 1,
1082 .bpc = 8,
1083 .size = {
1084 .width = 344,
1085 .height = 194,
1086 },
1087 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1088 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1089 };
1090
1091 static const struct display_timing auo_g185han01_timings = {
1092 .pixelclock = { 120000000, 144000000, 175000000 },
1093 .hactive = { 1920, 1920, 1920 },
1094 .hfront_porch = { 36, 120, 148 },
1095 .hback_porch = { 24, 88, 108 },
1096 .hsync_len = { 20, 48, 64 },
1097 .vactive = { 1080, 1080, 1080 },
1098 .vfront_porch = { 6, 10, 40 },
1099 .vback_porch = { 2, 5, 20 },
1100 .vsync_len = { 2, 5, 20 },
1101 };
1102
1103 static const struct panel_desc auo_g185han01 = {
1104 .timings = &auo_g185han01_timings,
1105 .num_timings = 1,
1106 .bpc = 8,
1107 .size = {
1108 .width = 409,
1109 .height = 230,
1110 },
1111 .delay = {
1112 .prepare = 50,
1113 .enable = 200,
1114 .disable = 110,
1115 .unprepare = 1000,
1116 },
1117 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1118 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1119 };
1120
1121 static const struct display_timing auo_g190ean01_timings = {
1122 .pixelclock = { 90000000, 108000000, 135000000 },
1123 .hactive = { 1280, 1280, 1280 },
1124 .hfront_porch = { 126, 184, 1266 },
1125 .hback_porch = { 84, 122, 844 },
1126 .hsync_len = { 70, 102, 704 },
1127 .vactive = { 1024, 1024, 1024 },
1128 .vfront_porch = { 4, 26, 76 },
1129 .vback_porch = { 2, 8, 25 },
1130 .vsync_len = { 2, 8, 25 },
1131 };
1132
1133 static const struct panel_desc auo_g190ean01 = {
1134 .timings = &auo_g190ean01_timings,
1135 .num_timings = 1,
1136 .bpc = 8,
1137 .size = {
1138 .width = 376,
1139 .height = 301,
1140 },
1141 .delay = {
1142 .prepare = 50,
1143 .enable = 200,
1144 .disable = 110,
1145 .unprepare = 1000,
1146 },
1147 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1148 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1149 };
1150
1151 static const struct display_timing auo_p320hvn03_timings = {
1152 .pixelclock = { 106000000, 148500000, 164000000 },
1153 .hactive = { 1920, 1920, 1920 },
1154 .hfront_porch = { 25, 50, 130 },
1155 .hback_porch = { 25, 50, 130 },
1156 .hsync_len = { 20, 40, 105 },
1157 .vactive = { 1080, 1080, 1080 },
1158 .vfront_porch = { 8, 17, 150 },
1159 .vback_porch = { 8, 17, 150 },
1160 .vsync_len = { 4, 11, 100 },
1161 };
1162
1163 static const struct panel_desc auo_p320hvn03 = {
1164 .timings = &auo_p320hvn03_timings,
1165 .num_timings = 1,
1166 .bpc = 8,
1167 .size = {
1168 .width = 698,
1169 .height = 393,
1170 },
1171 .delay = {
1172 .prepare = 1,
1173 .enable = 450,
1174 .unprepare = 500,
1175 },
1176 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1177 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1178 };
1179
1180 static const struct drm_display_mode auo_t215hvn01_mode = {
1181 .clock = 148800,
1182 .hdisplay = 1920,
1183 .hsync_start = 1920 + 88,
1184 .hsync_end = 1920 + 88 + 44,
1185 .htotal = 1920 + 88 + 44 + 148,
1186 .vdisplay = 1080,
1187 .vsync_start = 1080 + 4,
1188 .vsync_end = 1080 + 4 + 5,
1189 .vtotal = 1080 + 4 + 5 + 36,
1190 };
1191
1192 static const struct panel_desc auo_t215hvn01 = {
1193 .modes = &auo_t215hvn01_mode,
1194 .num_modes = 1,
1195 .bpc = 8,
1196 .size = {
1197 .width = 430,
1198 .height = 270,
1199 },
1200 .delay = {
1201 .disable = 5,
1202 .unprepare = 1000,
1203 },
1204 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1205 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1206 };
1207
1208 static const struct drm_display_mode avic_tm070ddh03_mode = {
1209 .clock = 51200,
1210 .hdisplay = 1024,
1211 .hsync_start = 1024 + 160,
1212 .hsync_end = 1024 + 160 + 4,
1213 .htotal = 1024 + 160 + 4 + 156,
1214 .vdisplay = 600,
1215 .vsync_start = 600 + 17,
1216 .vsync_end = 600 + 17 + 1,
1217 .vtotal = 600 + 17 + 1 + 17,
1218 };
1219
1220 static const struct panel_desc avic_tm070ddh03 = {
1221 .modes = &avic_tm070ddh03_mode,
1222 .num_modes = 1,
1223 .bpc = 8,
1224 .size = {
1225 .width = 154,
1226 .height = 90,
1227 },
1228 .delay = {
1229 .prepare = 20,
1230 .enable = 200,
1231 .disable = 200,
1232 },
1233 };
1234
1235 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1236 .clock = 30000,
1237 .hdisplay = 800,
1238 .hsync_start = 800 + 40,
1239 .hsync_end = 800 + 40 + 48,
1240 .htotal = 800 + 40 + 48 + 40,
1241 .vdisplay = 480,
1242 .vsync_start = 480 + 13,
1243 .vsync_end = 480 + 13 + 3,
1244 .vtotal = 480 + 13 + 3 + 29,
1245 };
1246
1247 static const struct panel_desc bananapi_s070wv20_ct16 = {
1248 .modes = &bananapi_s070wv20_ct16_mode,
1249 .num_modes = 1,
1250 .bpc = 6,
1251 .size = {
1252 .width = 154,
1253 .height = 86,
1254 },
1255 };
1256
1257 static const struct drm_display_mode boe_hv070wsa_mode = {
1258 .clock = 42105,
1259 .hdisplay = 1024,
1260 .hsync_start = 1024 + 30,
1261 .hsync_end = 1024 + 30 + 30,
1262 .htotal = 1024 + 30 + 30 + 30,
1263 .vdisplay = 600,
1264 .vsync_start = 600 + 10,
1265 .vsync_end = 600 + 10 + 10,
1266 .vtotal = 600 + 10 + 10 + 10,
1267 };
1268
1269 static const struct panel_desc boe_hv070wsa = {
1270 .modes = &boe_hv070wsa_mode,
1271 .num_modes = 1,
1272 .bpc = 8,
1273 .size = {
1274 .width = 154,
1275 .height = 90,
1276 },
1277 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1278 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1279 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1280 };
1281
1282 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
1283 {
1284 .clock = 71900,
1285 .hdisplay = 1280,
1286 .hsync_start = 1280 + 48,
1287 .hsync_end = 1280 + 48 + 32,
1288 .htotal = 1280 + 48 + 32 + 80,
1289 .vdisplay = 800,
1290 .vsync_start = 800 + 3,
1291 .vsync_end = 800 + 3 + 5,
1292 .vtotal = 800 + 3 + 5 + 24,
1293 },
1294 {
1295 .clock = 57500,
1296 .hdisplay = 1280,
1297 .hsync_start = 1280 + 48,
1298 .hsync_end = 1280 + 48 + 32,
1299 .htotal = 1280 + 48 + 32 + 80,
1300 .vdisplay = 800,
1301 .vsync_start = 800 + 3,
1302 .vsync_end = 800 + 3 + 5,
1303 .vtotal = 800 + 3 + 5 + 24,
1304 },
1305 };
1306
1307 static const struct panel_desc boe_nv101wxmn51 = {
1308 .modes = boe_nv101wxmn51_modes,
1309 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1310 .bpc = 8,
1311 .size = {
1312 .width = 217,
1313 .height = 136,
1314 },
1315 .delay = {
1316 .prepare = 210,
1317 .enable = 50,
1318 .unprepare = 160,
1319 },
1320 };
1321
1322 /* Also used for boe_nv133fhm_n62 */
1323 static const struct drm_display_mode boe_nv133fhm_n61_modes = {
1324 .clock = 147840,
1325 .hdisplay = 1920,
1326 .hsync_start = 1920 + 48,
1327 .hsync_end = 1920 + 48 + 32,
1328 .htotal = 1920 + 48 + 32 + 200,
1329 .vdisplay = 1080,
1330 .vsync_start = 1080 + 3,
1331 .vsync_end = 1080 + 3 + 6,
1332 .vtotal = 1080 + 3 + 6 + 31,
1333 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
1334 };
1335
1336 /* Also used for boe_nv133fhm_n62 */
1337 static const struct panel_desc boe_nv133fhm_n61 = {
1338 .modes = &boe_nv133fhm_n61_modes,
1339 .num_modes = 1,
1340 .bpc = 6,
1341 .size = {
1342 .width = 294,
1343 .height = 165,
1344 },
1345 .delay = {
1346 /*
1347 * When power is first given to the panel there's a short
1348 * spike on the HPD line. It was explained that this spike
1349 * was until the TCON data download was complete. On
1350 * one system this was measured at 8 ms. We'll put 15 ms
1351 * in the prepare delay just to be safe and take it away
1352 * from the hpd_absent_delay (which would otherwise be 200 ms)
1353 * to handle this. That means:
1354 * - If HPD isn't hooked up you still have 200 ms delay.
1355 * - If HPD is hooked up we won't try to look at it for the
1356 * first 15 ms.
1357 */
1358 .prepare = 15,
1359 .hpd_absent_delay = 185,
1360
1361 .unprepare = 500,
1362 },
1363 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1364 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1365 .connector_type = DRM_MODE_CONNECTOR_eDP,
1366 };
1367
1368 static const struct drm_display_mode boe_nv140fhmn49_modes[] = {
1369 {
1370 .clock = 148500,
1371 .hdisplay = 1920,
1372 .hsync_start = 1920 + 48,
1373 .hsync_end = 1920 + 48 + 32,
1374 .htotal = 2200,
1375 .vdisplay = 1080,
1376 .vsync_start = 1080 + 3,
1377 .vsync_end = 1080 + 3 + 5,
1378 .vtotal = 1125,
1379 },
1380 };
1381
1382 static const struct panel_desc boe_nv140fhmn49 = {
1383 .modes = boe_nv140fhmn49_modes,
1384 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes),
1385 .bpc = 6,
1386 .size = {
1387 .width = 309,
1388 .height = 174,
1389 },
1390 .delay = {
1391 .prepare = 210,
1392 .enable = 50,
1393 .unprepare = 160,
1394 },
1395 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1396 .connector_type = DRM_MODE_CONNECTOR_eDP,
1397 };
1398
1399 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1400 .clock = 9000,
1401 .hdisplay = 480,
1402 .hsync_start = 480 + 5,
1403 .hsync_end = 480 + 5 + 5,
1404 .htotal = 480 + 5 + 5 + 40,
1405 .vdisplay = 272,
1406 .vsync_start = 272 + 8,
1407 .vsync_end = 272 + 8 + 8,
1408 .vtotal = 272 + 8 + 8 + 8,
1409 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1410 };
1411
1412 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1413 .modes = &cdtech_s043wq26h_ct7_mode,
1414 .num_modes = 1,
1415 .bpc = 8,
1416 .size = {
1417 .width = 95,
1418 .height = 54,
1419 },
1420 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1421 };
1422
1423 /* S070PWS19HP-FC21 2017/04/22 */
1424 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1425 .clock = 51200,
1426 .hdisplay = 1024,
1427 .hsync_start = 1024 + 160,
1428 .hsync_end = 1024 + 160 + 20,
1429 .htotal = 1024 + 160 + 20 + 140,
1430 .vdisplay = 600,
1431 .vsync_start = 600 + 12,
1432 .vsync_end = 600 + 12 + 3,
1433 .vtotal = 600 + 12 + 3 + 20,
1434 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1435 };
1436
1437 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1438 .modes = &cdtech_s070pws19hp_fc21_mode,
1439 .num_modes = 1,
1440 .bpc = 6,
1441 .size = {
1442 .width = 154,
1443 .height = 86,
1444 },
1445 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1446 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1447 .connector_type = DRM_MODE_CONNECTOR_DPI,
1448 };
1449
1450 /* S070SWV29HG-DC44 2017/09/21 */
1451 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1452 .clock = 33300,
1453 .hdisplay = 800,
1454 .hsync_start = 800 + 210,
1455 .hsync_end = 800 + 210 + 2,
1456 .htotal = 800 + 210 + 2 + 44,
1457 .vdisplay = 480,
1458 .vsync_start = 480 + 22,
1459 .vsync_end = 480 + 22 + 2,
1460 .vtotal = 480 + 22 + 2 + 21,
1461 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1462 };
1463
1464 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1465 .modes = &cdtech_s070swv29hg_dc44_mode,
1466 .num_modes = 1,
1467 .bpc = 6,
1468 .size = {
1469 .width = 154,
1470 .height = 86,
1471 },
1472 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1473 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1474 .connector_type = DRM_MODE_CONNECTOR_DPI,
1475 };
1476
1477 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1478 .clock = 35000,
1479 .hdisplay = 800,
1480 .hsync_start = 800 + 40,
1481 .hsync_end = 800 + 40 + 40,
1482 .htotal = 800 + 40 + 40 + 48,
1483 .vdisplay = 480,
1484 .vsync_start = 480 + 29,
1485 .vsync_end = 480 + 29 + 13,
1486 .vtotal = 480 + 29 + 13 + 3,
1487 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1488 };
1489
1490 static const struct panel_desc cdtech_s070wv95_ct16 = {
1491 .modes = &cdtech_s070wv95_ct16_mode,
1492 .num_modes = 1,
1493 .bpc = 8,
1494 .size = {
1495 .width = 154,
1496 .height = 85,
1497 },
1498 };
1499
1500 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1501 .pixelclock = { 68900000, 71100000, 73400000 },
1502 .hactive = { 1280, 1280, 1280 },
1503 .hfront_porch = { 65, 80, 95 },
1504 .hback_porch = { 64, 79, 94 },
1505 .hsync_len = { 1, 1, 1 },
1506 .vactive = { 800, 800, 800 },
1507 .vfront_porch = { 7, 11, 14 },
1508 .vback_porch = { 7, 11, 14 },
1509 .vsync_len = { 1, 1, 1 },
1510 .flags = DISPLAY_FLAGS_DE_HIGH,
1511 };
1512
1513 static const struct panel_desc chefree_ch101olhlwh_002 = {
1514 .timings = &chefree_ch101olhlwh_002_timing,
1515 .num_timings = 1,
1516 .bpc = 8,
1517 .size = {
1518 .width = 217,
1519 .height = 135,
1520 },
1521 .delay = {
1522 .enable = 200,
1523 .disable = 200,
1524 },
1525 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1526 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1527 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1528 };
1529
1530 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1531 .clock = 66770,
1532 .hdisplay = 800,
1533 .hsync_start = 800 + 49,
1534 .hsync_end = 800 + 49 + 33,
1535 .htotal = 800 + 49 + 33 + 17,
1536 .vdisplay = 1280,
1537 .vsync_start = 1280 + 1,
1538 .vsync_end = 1280 + 1 + 7,
1539 .vtotal = 1280 + 1 + 7 + 15,
1540 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1541 };
1542
1543 static const struct panel_desc chunghwa_claa070wp03xg = {
1544 .modes = &chunghwa_claa070wp03xg_mode,
1545 .num_modes = 1,
1546 .bpc = 6,
1547 .size = {
1548 .width = 94,
1549 .height = 150,
1550 },
1551 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1552 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1553 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1554 };
1555
1556 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1557 .clock = 72070,
1558 .hdisplay = 1366,
1559 .hsync_start = 1366 + 58,
1560 .hsync_end = 1366 + 58 + 58,
1561 .htotal = 1366 + 58 + 58 + 58,
1562 .vdisplay = 768,
1563 .vsync_start = 768 + 4,
1564 .vsync_end = 768 + 4 + 4,
1565 .vtotal = 768 + 4 + 4 + 4,
1566 };
1567
1568 static const struct panel_desc chunghwa_claa101wa01a = {
1569 .modes = &chunghwa_claa101wa01a_mode,
1570 .num_modes = 1,
1571 .bpc = 6,
1572 .size = {
1573 .width = 220,
1574 .height = 120,
1575 },
1576 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1577 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1578 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1579 };
1580
1581 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1582 .clock = 69300,
1583 .hdisplay = 1366,
1584 .hsync_start = 1366 + 48,
1585 .hsync_end = 1366 + 48 + 32,
1586 .htotal = 1366 + 48 + 32 + 20,
1587 .vdisplay = 768,
1588 .vsync_start = 768 + 16,
1589 .vsync_end = 768 + 16 + 8,
1590 .vtotal = 768 + 16 + 8 + 16,
1591 };
1592
1593 static const struct panel_desc chunghwa_claa101wb01 = {
1594 .modes = &chunghwa_claa101wb01_mode,
1595 .num_modes = 1,
1596 .bpc = 6,
1597 .size = {
1598 .width = 223,
1599 .height = 125,
1600 },
1601 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1602 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1603 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1604 };
1605
1606 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1607 .clock = 33260,
1608 .hdisplay = 800,
1609 .hsync_start = 800 + 40,
1610 .hsync_end = 800 + 40 + 128,
1611 .htotal = 800 + 40 + 128 + 88,
1612 .vdisplay = 480,
1613 .vsync_start = 480 + 10,
1614 .vsync_end = 480 + 10 + 2,
1615 .vtotal = 480 + 10 + 2 + 33,
1616 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1617 };
1618
1619 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1620 .modes = &dataimage_scf0700c48ggu18_mode,
1621 .num_modes = 1,
1622 .bpc = 8,
1623 .size = {
1624 .width = 152,
1625 .height = 91,
1626 },
1627 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1628 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1629 };
1630
1631 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1632 .pixelclock = { 45000000, 51200000, 57000000 },
1633 .hactive = { 1024, 1024, 1024 },
1634 .hfront_porch = { 100, 106, 113 },
1635 .hback_porch = { 100, 106, 113 },
1636 .hsync_len = { 100, 108, 114 },
1637 .vactive = { 600, 600, 600 },
1638 .vfront_porch = { 8, 11, 15 },
1639 .vback_porch = { 8, 11, 15 },
1640 .vsync_len = { 9, 13, 15 },
1641 .flags = DISPLAY_FLAGS_DE_HIGH,
1642 };
1643
1644 static const struct panel_desc dlc_dlc0700yzg_1 = {
1645 .timings = &dlc_dlc0700yzg_1_timing,
1646 .num_timings = 1,
1647 .bpc = 6,
1648 .size = {
1649 .width = 154,
1650 .height = 86,
1651 },
1652 .delay = {
1653 .prepare = 30,
1654 .enable = 200,
1655 .disable = 200,
1656 },
1657 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1658 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1659 };
1660
1661 static const struct display_timing dlc_dlc1010gig_timing = {
1662 .pixelclock = { 68900000, 71100000, 73400000 },
1663 .hactive = { 1280, 1280, 1280 },
1664 .hfront_porch = { 43, 53, 63 },
1665 .hback_porch = { 43, 53, 63 },
1666 .hsync_len = { 44, 54, 64 },
1667 .vactive = { 800, 800, 800 },
1668 .vfront_porch = { 5, 8, 11 },
1669 .vback_porch = { 5, 8, 11 },
1670 .vsync_len = { 5, 7, 11 },
1671 .flags = DISPLAY_FLAGS_DE_HIGH,
1672 };
1673
1674 static const struct panel_desc dlc_dlc1010gig = {
1675 .timings = &dlc_dlc1010gig_timing,
1676 .num_timings = 1,
1677 .bpc = 8,
1678 .size = {
1679 .width = 216,
1680 .height = 135,
1681 },
1682 .delay = {
1683 .prepare = 60,
1684 .enable = 150,
1685 .disable = 100,
1686 .unprepare = 60,
1687 },
1688 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1689 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1690 };
1691
1692 static const struct drm_display_mode edt_et035012dm6_mode = {
1693 .clock = 6500,
1694 .hdisplay = 320,
1695 .hsync_start = 320 + 20,
1696 .hsync_end = 320 + 20 + 30,
1697 .htotal = 320 + 20 + 68,
1698 .vdisplay = 240,
1699 .vsync_start = 240 + 4,
1700 .vsync_end = 240 + 4 + 4,
1701 .vtotal = 240 + 4 + 4 + 14,
1702 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1703 };
1704
1705 static const struct panel_desc edt_et035012dm6 = {
1706 .modes = &edt_et035012dm6_mode,
1707 .num_modes = 1,
1708 .bpc = 8,
1709 .size = {
1710 .width = 70,
1711 .height = 52,
1712 },
1713 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1714 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1715 };
1716
1717 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1718 .clock = 10870,
1719 .hdisplay = 480,
1720 .hsync_start = 480 + 8,
1721 .hsync_end = 480 + 8 + 4,
1722 .htotal = 480 + 8 + 4 + 41,
1723
1724 /*
1725 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1726 * fb_align
1727 */
1728
1729 .vdisplay = 288,
1730 .vsync_start = 288 + 2,
1731 .vsync_end = 288 + 2 + 4,
1732 .vtotal = 288 + 2 + 4 + 10,
1733 };
1734
1735 static const struct panel_desc edt_etm043080dh6gp = {
1736 .modes = &edt_etm043080dh6gp_mode,
1737 .num_modes = 1,
1738 .bpc = 8,
1739 .size = {
1740 .width = 100,
1741 .height = 65,
1742 },
1743 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1744 .connector_type = DRM_MODE_CONNECTOR_DPI,
1745 };
1746
1747 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1748 .clock = 9000,
1749 .hdisplay = 480,
1750 .hsync_start = 480 + 2,
1751 .hsync_end = 480 + 2 + 41,
1752 .htotal = 480 + 2 + 41 + 2,
1753 .vdisplay = 272,
1754 .vsync_start = 272 + 2,
1755 .vsync_end = 272 + 2 + 10,
1756 .vtotal = 272 + 2 + 10 + 2,
1757 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1758 };
1759
1760 static const struct panel_desc edt_etm0430g0dh6 = {
1761 .modes = &edt_etm0430g0dh6_mode,
1762 .num_modes = 1,
1763 .bpc = 6,
1764 .size = {
1765 .width = 95,
1766 .height = 54,
1767 },
1768 };
1769
1770 static const struct drm_display_mode edt_et057090dhu_mode = {
1771 .clock = 25175,
1772 .hdisplay = 640,
1773 .hsync_start = 640 + 16,
1774 .hsync_end = 640 + 16 + 30,
1775 .htotal = 640 + 16 + 30 + 114,
1776 .vdisplay = 480,
1777 .vsync_start = 480 + 10,
1778 .vsync_end = 480 + 10 + 3,
1779 .vtotal = 480 + 10 + 3 + 32,
1780 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1781 };
1782
1783 static const struct panel_desc edt_et057090dhu = {
1784 .modes = &edt_et057090dhu_mode,
1785 .num_modes = 1,
1786 .bpc = 6,
1787 .size = {
1788 .width = 115,
1789 .height = 86,
1790 },
1791 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1792 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1793 .connector_type = DRM_MODE_CONNECTOR_DPI,
1794 };
1795
1796 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1797 .clock = 33260,
1798 .hdisplay = 800,
1799 .hsync_start = 800 + 40,
1800 .hsync_end = 800 + 40 + 128,
1801 .htotal = 800 + 40 + 128 + 88,
1802 .vdisplay = 480,
1803 .vsync_start = 480 + 10,
1804 .vsync_end = 480 + 10 + 2,
1805 .vtotal = 480 + 10 + 2 + 33,
1806 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1807 };
1808
1809 static const struct panel_desc edt_etm0700g0dh6 = {
1810 .modes = &edt_etm0700g0dh6_mode,
1811 .num_modes = 1,
1812 .bpc = 6,
1813 .size = {
1814 .width = 152,
1815 .height = 91,
1816 },
1817 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1818 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1819 };
1820
1821 static const struct panel_desc edt_etm0700g0bdh6 = {
1822 .modes = &edt_etm0700g0dh6_mode,
1823 .num_modes = 1,
1824 .bpc = 6,
1825 .size = {
1826 .width = 152,
1827 .height = 91,
1828 },
1829 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1830 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1831 };
1832
1833 static const struct display_timing evervision_vgg804821_timing = {
1834 .pixelclock = { 27600000, 33300000, 50000000 },
1835 .hactive = { 800, 800, 800 },
1836 .hfront_porch = { 40, 66, 70 },
1837 .hback_porch = { 40, 67, 70 },
1838 .hsync_len = { 40, 67, 70 },
1839 .vactive = { 480, 480, 480 },
1840 .vfront_porch = { 6, 10, 10 },
1841 .vback_porch = { 7, 11, 11 },
1842 .vsync_len = { 7, 11, 11 },
1843 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1844 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1845 DISPLAY_FLAGS_SYNC_NEGEDGE,
1846 };
1847
1848 static const struct panel_desc evervision_vgg804821 = {
1849 .timings = &evervision_vgg804821_timing,
1850 .num_timings = 1,
1851 .bpc = 8,
1852 .size = {
1853 .width = 108,
1854 .height = 64,
1855 },
1856 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1857 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1858 };
1859
1860 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1861 .clock = 32260,
1862 .hdisplay = 800,
1863 .hsync_start = 800 + 168,
1864 .hsync_end = 800 + 168 + 64,
1865 .htotal = 800 + 168 + 64 + 88,
1866 .vdisplay = 480,
1867 .vsync_start = 480 + 37,
1868 .vsync_end = 480 + 37 + 2,
1869 .vtotal = 480 + 37 + 2 + 8,
1870 };
1871
1872 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1873 .modes = &foxlink_fl500wvr00_a0t_mode,
1874 .num_modes = 1,
1875 .bpc = 8,
1876 .size = {
1877 .width = 108,
1878 .height = 65,
1879 },
1880 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1881 };
1882
1883 static const struct drm_display_mode frida_frd350h54004_modes[] = {
1884 { /* 60 Hz */
1885 .clock = 6000,
1886 .hdisplay = 320,
1887 .hsync_start = 320 + 44,
1888 .hsync_end = 320 + 44 + 16,
1889 .htotal = 320 + 44 + 16 + 20,
1890 .vdisplay = 240,
1891 .vsync_start = 240 + 2,
1892 .vsync_end = 240 + 2 + 6,
1893 .vtotal = 240 + 2 + 6 + 2,
1894 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1895 },
1896 { /* 50 Hz */
1897 .clock = 5400,
1898 .hdisplay = 320,
1899 .hsync_start = 320 + 56,
1900 .hsync_end = 320 + 56 + 16,
1901 .htotal = 320 + 56 + 16 + 40,
1902 .vdisplay = 240,
1903 .vsync_start = 240 + 2,
1904 .vsync_end = 240 + 2 + 6,
1905 .vtotal = 240 + 2 + 6 + 2,
1906 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1907 },
1908 };
1909
1910 static const struct panel_desc frida_frd350h54004 = {
1911 .modes = frida_frd350h54004_modes,
1912 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
1913 .bpc = 8,
1914 .size = {
1915 .width = 77,
1916 .height = 64,
1917 },
1918 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1919 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1920 .connector_type = DRM_MODE_CONNECTOR_DPI,
1921 };
1922
1923 static const struct drm_display_mode friendlyarm_hd702e_mode = {
1924 .clock = 67185,
1925 .hdisplay = 800,
1926 .hsync_start = 800 + 20,
1927 .hsync_end = 800 + 20 + 24,
1928 .htotal = 800 + 20 + 24 + 20,
1929 .vdisplay = 1280,
1930 .vsync_start = 1280 + 4,
1931 .vsync_end = 1280 + 4 + 8,
1932 .vtotal = 1280 + 4 + 8 + 4,
1933 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1934 };
1935
1936 static const struct panel_desc friendlyarm_hd702e = {
1937 .modes = &friendlyarm_hd702e_mode,
1938 .num_modes = 1,
1939 .size = {
1940 .width = 94,
1941 .height = 151,
1942 },
1943 };
1944
1945 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1946 .clock = 9000,
1947 .hdisplay = 480,
1948 .hsync_start = 480 + 5,
1949 .hsync_end = 480 + 5 + 1,
1950 .htotal = 480 + 5 + 1 + 40,
1951 .vdisplay = 272,
1952 .vsync_start = 272 + 8,
1953 .vsync_end = 272 + 8 + 1,
1954 .vtotal = 272 + 8 + 1 + 8,
1955 };
1956
1957 static const struct panel_desc giantplus_gpg482739qs5 = {
1958 .modes = &giantplus_gpg482739qs5_mode,
1959 .num_modes = 1,
1960 .bpc = 8,
1961 .size = {
1962 .width = 95,
1963 .height = 54,
1964 },
1965 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1966 };
1967
1968 static const struct display_timing giantplus_gpm940b0_timing = {
1969 .pixelclock = { 13500000, 27000000, 27500000 },
1970 .hactive = { 320, 320, 320 },
1971 .hfront_porch = { 14, 686, 718 },
1972 .hback_porch = { 50, 70, 255 },
1973 .hsync_len = { 1, 1, 1 },
1974 .vactive = { 240, 240, 240 },
1975 .vfront_porch = { 1, 1, 179 },
1976 .vback_porch = { 1, 21, 31 },
1977 .vsync_len = { 1, 1, 6 },
1978 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1979 };
1980
1981 static const struct panel_desc giantplus_gpm940b0 = {
1982 .timings = &giantplus_gpm940b0_timing,
1983 .num_timings = 1,
1984 .bpc = 8,
1985 .size = {
1986 .width = 60,
1987 .height = 45,
1988 },
1989 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
1990 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1991 };
1992
1993 static const struct display_timing hannstar_hsd070pww1_timing = {
1994 .pixelclock = { 64300000, 71100000, 82000000 },
1995 .hactive = { 1280, 1280, 1280 },
1996 .hfront_porch = { 1, 1, 10 },
1997 .hback_porch = { 1, 1, 10 },
1998 /*
1999 * According to the data sheet, the minimum horizontal blanking interval
2000 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2001 * minimum working horizontal blanking interval to be 60 clocks.
2002 */
2003 .hsync_len = { 58, 158, 661 },
2004 .vactive = { 800, 800, 800 },
2005 .vfront_porch = { 1, 1, 10 },
2006 .vback_porch = { 1, 1, 10 },
2007 .vsync_len = { 1, 21, 203 },
2008 .flags = DISPLAY_FLAGS_DE_HIGH,
2009 };
2010
2011 static const struct panel_desc hannstar_hsd070pww1 = {
2012 .timings = &hannstar_hsd070pww1_timing,
2013 .num_timings = 1,
2014 .bpc = 6,
2015 .size = {
2016 .width = 151,
2017 .height = 94,
2018 },
2019 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2020 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2021 };
2022
2023 static const struct display_timing hannstar_hsd100pxn1_timing = {
2024 .pixelclock = { 55000000, 65000000, 75000000 },
2025 .hactive = { 1024, 1024, 1024 },
2026 .hfront_porch = { 40, 40, 40 },
2027 .hback_porch = { 220, 220, 220 },
2028 .hsync_len = { 20, 60, 100 },
2029 .vactive = { 768, 768, 768 },
2030 .vfront_porch = { 7, 7, 7 },
2031 .vback_porch = { 21, 21, 21 },
2032 .vsync_len = { 10, 10, 10 },
2033 .flags = DISPLAY_FLAGS_DE_HIGH,
2034 };
2035
2036 static const struct panel_desc hannstar_hsd100pxn1 = {
2037 .timings = &hannstar_hsd100pxn1_timing,
2038 .num_timings = 1,
2039 .bpc = 6,
2040 .size = {
2041 .width = 203,
2042 .height = 152,
2043 },
2044 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2045 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2046 };
2047
2048 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2049 .clock = 33333,
2050 .hdisplay = 800,
2051 .hsync_start = 800 + 85,
2052 .hsync_end = 800 + 85 + 86,
2053 .htotal = 800 + 85 + 86 + 85,
2054 .vdisplay = 480,
2055 .vsync_start = 480 + 16,
2056 .vsync_end = 480 + 16 + 13,
2057 .vtotal = 480 + 16 + 13 + 16,
2058 };
2059
2060 static const struct panel_desc hitachi_tx23d38vm0caa = {
2061 .modes = &hitachi_tx23d38vm0caa_mode,
2062 .num_modes = 1,
2063 .bpc = 6,
2064 .size = {
2065 .width = 195,
2066 .height = 117,
2067 },
2068 .delay = {
2069 .enable = 160,
2070 .disable = 160,
2071 },
2072 };
2073
2074 static const struct drm_display_mode innolux_at043tn24_mode = {
2075 .clock = 9000,
2076 .hdisplay = 480,
2077 .hsync_start = 480 + 2,
2078 .hsync_end = 480 + 2 + 41,
2079 .htotal = 480 + 2 + 41 + 2,
2080 .vdisplay = 272,
2081 .vsync_start = 272 + 2,
2082 .vsync_end = 272 + 2 + 10,
2083 .vtotal = 272 + 2 + 10 + 2,
2084 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2085 };
2086
2087 static const struct panel_desc innolux_at043tn24 = {
2088 .modes = &innolux_at043tn24_mode,
2089 .num_modes = 1,
2090 .bpc = 8,
2091 .size = {
2092 .width = 95,
2093 .height = 54,
2094 },
2095 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2096 .connector_type = DRM_MODE_CONNECTOR_DPI,
2097 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2098 };
2099
2100 static const struct drm_display_mode innolux_at070tn92_mode = {
2101 .clock = 33333,
2102 .hdisplay = 800,
2103 .hsync_start = 800 + 210,
2104 .hsync_end = 800 + 210 + 20,
2105 .htotal = 800 + 210 + 20 + 46,
2106 .vdisplay = 480,
2107 .vsync_start = 480 + 22,
2108 .vsync_end = 480 + 22 + 10,
2109 .vtotal = 480 + 22 + 23 + 10,
2110 };
2111
2112 static const struct panel_desc innolux_at070tn92 = {
2113 .modes = &innolux_at070tn92_mode,
2114 .num_modes = 1,
2115 .size = {
2116 .width = 154,
2117 .height = 86,
2118 },
2119 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2120 };
2121
2122 static const struct display_timing innolux_g070y2_l01_timing = {
2123 .pixelclock = { 28000000, 29500000, 32000000 },
2124 .hactive = { 800, 800, 800 },
2125 .hfront_porch = { 61, 91, 141 },
2126 .hback_porch = { 60, 90, 140 },
2127 .hsync_len = { 12, 12, 12 },
2128 .vactive = { 480, 480, 480 },
2129 .vfront_porch = { 4, 9, 30 },
2130 .vback_porch = { 4, 8, 28 },
2131 .vsync_len = { 2, 2, 2 },
2132 .flags = DISPLAY_FLAGS_DE_HIGH,
2133 };
2134
2135 static const struct panel_desc innolux_g070y2_l01 = {
2136 .timings = &innolux_g070y2_l01_timing,
2137 .num_timings = 1,
2138 .bpc = 8,
2139 .size = {
2140 .width = 152,
2141 .height = 91,
2142 },
2143 .delay = {
2144 .prepare = 10,
2145 .enable = 100,
2146 .disable = 100,
2147 .unprepare = 800,
2148 },
2149 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2150 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2151 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2152 };
2153
2154 static const struct display_timing innolux_g101ice_l01_timing = {
2155 .pixelclock = { 60400000, 71100000, 74700000 },
2156 .hactive = { 1280, 1280, 1280 },
2157 .hfront_porch = { 30, 60, 70 },
2158 .hback_porch = { 30, 60, 70 },
2159 .hsync_len = { 22, 40, 60 },
2160 .vactive = { 800, 800, 800 },
2161 .vfront_porch = { 3, 8, 14 },
2162 .vback_porch = { 3, 8, 14 },
2163 .vsync_len = { 4, 7, 12 },
2164 .flags = DISPLAY_FLAGS_DE_HIGH,
2165 };
2166
2167 static const struct panel_desc innolux_g101ice_l01 = {
2168 .timings = &innolux_g101ice_l01_timing,
2169 .num_timings = 1,
2170 .bpc = 8,
2171 .size = {
2172 .width = 217,
2173 .height = 135,
2174 },
2175 .delay = {
2176 .enable = 200,
2177 .disable = 200,
2178 },
2179 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2180 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2181 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2182 };
2183
2184 static const struct display_timing innolux_g121i1_l01_timing = {
2185 .pixelclock = { 67450000, 71000000, 74550000 },
2186 .hactive = { 1280, 1280, 1280 },
2187 .hfront_porch = { 40, 80, 160 },
2188 .hback_porch = { 39, 79, 159 },
2189 .hsync_len = { 1, 1, 1 },
2190 .vactive = { 800, 800, 800 },
2191 .vfront_porch = { 5, 11, 100 },
2192 .vback_porch = { 4, 11, 99 },
2193 .vsync_len = { 1, 1, 1 },
2194 };
2195
2196 static const struct panel_desc innolux_g121i1_l01 = {
2197 .timings = &innolux_g121i1_l01_timing,
2198 .num_timings = 1,
2199 .bpc = 6,
2200 .size = {
2201 .width = 261,
2202 .height = 163,
2203 },
2204 .delay = {
2205 .enable = 200,
2206 .disable = 20,
2207 },
2208 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2209 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2210 };
2211
2212 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2213 .clock = 65000,
2214 .hdisplay = 1024,
2215 .hsync_start = 1024 + 0,
2216 .hsync_end = 1024 + 1,
2217 .htotal = 1024 + 0 + 1 + 320,
2218 .vdisplay = 768,
2219 .vsync_start = 768 + 38,
2220 .vsync_end = 768 + 38 + 1,
2221 .vtotal = 768 + 38 + 1 + 0,
2222 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2223 };
2224
2225 static const struct panel_desc innolux_g121x1_l03 = {
2226 .modes = &innolux_g121x1_l03_mode,
2227 .num_modes = 1,
2228 .bpc = 6,
2229 .size = {
2230 .width = 246,
2231 .height = 185,
2232 },
2233 .delay = {
2234 .enable = 200,
2235 .unprepare = 200,
2236 .disable = 400,
2237 },
2238 };
2239
2240 /*
2241 * Datasheet specifies that at 60 Hz refresh rate:
2242 * - total horizontal time: { 1506, 1592, 1716 }
2243 * - total vertical time: { 788, 800, 868 }
2244 *
2245 * ...but doesn't go into exactly how that should be split into a front
2246 * porch, back porch, or sync length. For now we'll leave a single setting
2247 * here which allows a bit of tweaking of the pixel clock at the expense of
2248 * refresh rate.
2249 */
2250 static const struct display_timing innolux_n116bge_timing = {
2251 .pixelclock = { 72600000, 76420000, 80240000 },
2252 .hactive = { 1366, 1366, 1366 },
2253 .hfront_porch = { 136, 136, 136 },
2254 .hback_porch = { 60, 60, 60 },
2255 .hsync_len = { 30, 30, 30 },
2256 .vactive = { 768, 768, 768 },
2257 .vfront_porch = { 8, 8, 8 },
2258 .vback_porch = { 12, 12, 12 },
2259 .vsync_len = { 12, 12, 12 },
2260 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2261 };
2262
2263 static const struct panel_desc innolux_n116bge = {
2264 .timings = &innolux_n116bge_timing,
2265 .num_timings = 1,
2266 .bpc = 6,
2267 .size = {
2268 .width = 256,
2269 .height = 144,
2270 },
2271 };
2272
2273 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2274 .clock = 69300,
2275 .hdisplay = 1366,
2276 .hsync_start = 1366 + 16,
2277 .hsync_end = 1366 + 16 + 34,
2278 .htotal = 1366 + 16 + 34 + 50,
2279 .vdisplay = 768,
2280 .vsync_start = 768 + 2,
2281 .vsync_end = 768 + 2 + 6,
2282 .vtotal = 768 + 2 + 6 + 12,
2283 };
2284
2285 static const struct panel_desc innolux_n156bge_l21 = {
2286 .modes = &innolux_n156bge_l21_mode,
2287 .num_modes = 1,
2288 .bpc = 6,
2289 .size = {
2290 .width = 344,
2291 .height = 193,
2292 },
2293 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2294 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2295 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2296 };
2297
2298 static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
2299 .clock = 206016,
2300 .hdisplay = 2160,
2301 .hsync_start = 2160 + 48,
2302 .hsync_end = 2160 + 48 + 32,
2303 .htotal = 2160 + 48 + 32 + 80,
2304 .vdisplay = 1440,
2305 .vsync_start = 1440 + 3,
2306 .vsync_end = 1440 + 3 + 10,
2307 .vtotal = 1440 + 3 + 10 + 27,
2308 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2309 };
2310
2311 static const struct panel_desc innolux_p120zdg_bf1 = {
2312 .modes = &innolux_p120zdg_bf1_mode,
2313 .num_modes = 1,
2314 .bpc = 8,
2315 .size = {
2316 .width = 254,
2317 .height = 169,
2318 },
2319 .delay = {
2320 .hpd_absent_delay = 200,
2321 .unprepare = 500,
2322 },
2323 };
2324
2325 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2326 .clock = 51501,
2327 .hdisplay = 1024,
2328 .hsync_start = 1024 + 128,
2329 .hsync_end = 1024 + 128 + 64,
2330 .htotal = 1024 + 128 + 64 + 128,
2331 .vdisplay = 600,
2332 .vsync_start = 600 + 16,
2333 .vsync_end = 600 + 16 + 4,
2334 .vtotal = 600 + 16 + 4 + 16,
2335 };
2336
2337 static const struct panel_desc innolux_zj070na_01p = {
2338 .modes = &innolux_zj070na_01p_mode,
2339 .num_modes = 1,
2340 .bpc = 6,
2341 .size = {
2342 .width = 154,
2343 .height = 90,
2344 },
2345 };
2346
2347 static const struct drm_display_mode ivo_m133nwf4_r0_mode = {
2348 .clock = 138778,
2349 .hdisplay = 1920,
2350 .hsync_start = 1920 + 24,
2351 .hsync_end = 1920 + 24 + 48,
2352 .htotal = 1920 + 24 + 48 + 88,
2353 .vdisplay = 1080,
2354 .vsync_start = 1080 + 3,
2355 .vsync_end = 1080 + 3 + 12,
2356 .vtotal = 1080 + 3 + 12 + 17,
2357 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2358 };
2359
2360 static const struct panel_desc ivo_m133nwf4_r0 = {
2361 .modes = &ivo_m133nwf4_r0_mode,
2362 .num_modes = 1,
2363 .bpc = 8,
2364 .size = {
2365 .width = 294,
2366 .height = 165,
2367 },
2368 .delay = {
2369 .hpd_absent_delay = 200,
2370 .unprepare = 500,
2371 },
2372 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2373 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2374 .connector_type = DRM_MODE_CONNECTOR_eDP,
2375 };
2376
2377 static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = {
2378 .clock = 81000,
2379 .hdisplay = 1366,
2380 .hsync_start = 1366 + 40,
2381 .hsync_end = 1366 + 40 + 32,
2382 .htotal = 1366 + 40 + 32 + 62,
2383 .vdisplay = 768,
2384 .vsync_start = 768 + 5,
2385 .vsync_end = 768 + 5 + 5,
2386 .vtotal = 768 + 5 + 5 + 122,
2387 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2388 };
2389
2390 static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = {
2391 .modes = &kingdisplay_kd116n21_30nv_a010_mode,
2392 .num_modes = 1,
2393 .bpc = 6,
2394 .size = {
2395 .width = 256,
2396 .height = 144,
2397 },
2398 .delay = {
2399 .hpd_absent_delay = 200,
2400 },
2401 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2402 .connector_type = DRM_MODE_CONNECTOR_eDP,
2403 };
2404
2405 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2406 .pixelclock = { 5580000, 5850000, 6200000 },
2407 .hactive = { 320, 320, 320 },
2408 .hfront_porch = { 30, 30, 30 },
2409 .hback_porch = { 30, 30, 30 },
2410 .hsync_len = { 1, 5, 17 },
2411 .vactive = { 240, 240, 240 },
2412 .vfront_porch = { 6, 6, 6 },
2413 .vback_porch = { 5, 5, 5 },
2414 .vsync_len = { 1, 2, 11 },
2415 .flags = DISPLAY_FLAGS_DE_HIGH,
2416 };
2417
2418 static const struct panel_desc koe_tx14d24vm1bpa = {
2419 .timings = &koe_tx14d24vm1bpa_timing,
2420 .num_timings = 1,
2421 .bpc = 6,
2422 .size = {
2423 .width = 115,
2424 .height = 86,
2425 },
2426 };
2427
2428 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2429 .pixelclock = { 151820000, 156720000, 159780000 },
2430 .hactive = { 1920, 1920, 1920 },
2431 .hfront_porch = { 105, 130, 142 },
2432 .hback_porch = { 45, 70, 82 },
2433 .hsync_len = { 30, 30, 30 },
2434 .vactive = { 1200, 1200, 1200},
2435 .vfront_porch = { 3, 5, 10 },
2436 .vback_porch = { 2, 5, 10 },
2437 .vsync_len = { 5, 5, 5 },
2438 };
2439
2440 static const struct panel_desc koe_tx26d202vm0bwa = {
2441 .timings = &koe_tx26d202vm0bwa_timing,
2442 .num_timings = 1,
2443 .bpc = 8,
2444 .size = {
2445 .width = 217,
2446 .height = 136,
2447 },
2448 .delay = {
2449 .prepare = 1000,
2450 .enable = 1000,
2451 .unprepare = 1000,
2452 .disable = 1000,
2453 },
2454 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2455 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2456 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2457 };
2458
2459 static const struct display_timing koe_tx31d200vm0baa_timing = {
2460 .pixelclock = { 39600000, 43200000, 48000000 },
2461 .hactive = { 1280, 1280, 1280 },
2462 .hfront_porch = { 16, 36, 56 },
2463 .hback_porch = { 16, 36, 56 },
2464 .hsync_len = { 8, 8, 8 },
2465 .vactive = { 480, 480, 480 },
2466 .vfront_porch = { 6, 21, 33 },
2467 .vback_porch = { 6, 21, 33 },
2468 .vsync_len = { 8, 8, 8 },
2469 .flags = DISPLAY_FLAGS_DE_HIGH,
2470 };
2471
2472 static const struct panel_desc koe_tx31d200vm0baa = {
2473 .timings = &koe_tx31d200vm0baa_timing,
2474 .num_timings = 1,
2475 .bpc = 6,
2476 .size = {
2477 .width = 292,
2478 .height = 109,
2479 },
2480 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2481 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2482 };
2483
2484 static const struct display_timing kyo_tcg121xglp_timing = {
2485 .pixelclock = { 52000000, 65000000, 71000000 },
2486 .hactive = { 1024, 1024, 1024 },
2487 .hfront_porch = { 2, 2, 2 },
2488 .hback_porch = { 2, 2, 2 },
2489 .hsync_len = { 86, 124, 244 },
2490 .vactive = { 768, 768, 768 },
2491 .vfront_porch = { 2, 2, 2 },
2492 .vback_porch = { 2, 2, 2 },
2493 .vsync_len = { 6, 34, 73 },
2494 .flags = DISPLAY_FLAGS_DE_HIGH,
2495 };
2496
2497 static const struct panel_desc kyo_tcg121xglp = {
2498 .timings = &kyo_tcg121xglp_timing,
2499 .num_timings = 1,
2500 .bpc = 8,
2501 .size = {
2502 .width = 246,
2503 .height = 184,
2504 },
2505 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2506 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2507 };
2508
2509 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2510 .clock = 7000,
2511 .hdisplay = 320,
2512 .hsync_start = 320 + 20,
2513 .hsync_end = 320 + 20 + 30,
2514 .htotal = 320 + 20 + 30 + 38,
2515 .vdisplay = 240,
2516 .vsync_start = 240 + 4,
2517 .vsync_end = 240 + 4 + 3,
2518 .vtotal = 240 + 4 + 3 + 15,
2519 };
2520
2521 static const struct panel_desc lemaker_bl035_rgb_002 = {
2522 .modes = &lemaker_bl035_rgb_002_mode,
2523 .num_modes = 1,
2524 .size = {
2525 .width = 70,
2526 .height = 52,
2527 },
2528 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2529 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2530 };
2531
2532 static const struct drm_display_mode lg_lb070wv8_mode = {
2533 .clock = 33246,
2534 .hdisplay = 800,
2535 .hsync_start = 800 + 88,
2536 .hsync_end = 800 + 88 + 80,
2537 .htotal = 800 + 88 + 80 + 88,
2538 .vdisplay = 480,
2539 .vsync_start = 480 + 10,
2540 .vsync_end = 480 + 10 + 25,
2541 .vtotal = 480 + 10 + 25 + 10,
2542 };
2543
2544 static const struct panel_desc lg_lb070wv8 = {
2545 .modes = &lg_lb070wv8_mode,
2546 .num_modes = 1,
2547 .bpc = 8,
2548 .size = {
2549 .width = 151,
2550 .height = 91,
2551 },
2552 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2553 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2554 };
2555
2556 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
2557 .clock = 200000,
2558 .hdisplay = 1536,
2559 .hsync_start = 1536 + 12,
2560 .hsync_end = 1536 + 12 + 16,
2561 .htotal = 1536 + 12 + 16 + 48,
2562 .vdisplay = 2048,
2563 .vsync_start = 2048 + 8,
2564 .vsync_end = 2048 + 8 + 4,
2565 .vtotal = 2048 + 8 + 4 + 8,
2566 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2567 };
2568
2569 static const struct panel_desc lg_lp079qx1_sp0v = {
2570 .modes = &lg_lp079qx1_sp0v_mode,
2571 .num_modes = 1,
2572 .size = {
2573 .width = 129,
2574 .height = 171,
2575 },
2576 };
2577
2578 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
2579 .clock = 205210,
2580 .hdisplay = 2048,
2581 .hsync_start = 2048 + 150,
2582 .hsync_end = 2048 + 150 + 5,
2583 .htotal = 2048 + 150 + 5 + 5,
2584 .vdisplay = 1536,
2585 .vsync_start = 1536 + 3,
2586 .vsync_end = 1536 + 3 + 1,
2587 .vtotal = 1536 + 3 + 1 + 9,
2588 };
2589
2590 static const struct panel_desc lg_lp097qx1_spa1 = {
2591 .modes = &lg_lp097qx1_spa1_mode,
2592 .num_modes = 1,
2593 .size = {
2594 .width = 208,
2595 .height = 147,
2596 },
2597 };
2598
2599 static const struct drm_display_mode lg_lp120up1_mode = {
2600 .clock = 162300,
2601 .hdisplay = 1920,
2602 .hsync_start = 1920 + 40,
2603 .hsync_end = 1920 + 40 + 40,
2604 .htotal = 1920 + 40 + 40+ 80,
2605 .vdisplay = 1280,
2606 .vsync_start = 1280 + 4,
2607 .vsync_end = 1280 + 4 + 4,
2608 .vtotal = 1280 + 4 + 4 + 12,
2609 };
2610
2611 static const struct panel_desc lg_lp120up1 = {
2612 .modes = &lg_lp120up1_mode,
2613 .num_modes = 1,
2614 .bpc = 8,
2615 .size = {
2616 .width = 267,
2617 .height = 183,
2618 },
2619 .connector_type = DRM_MODE_CONNECTOR_eDP,
2620 };
2621
2622 static const struct drm_display_mode lg_lp129qe_mode = {
2623 .clock = 285250,
2624 .hdisplay = 2560,
2625 .hsync_start = 2560 + 48,
2626 .hsync_end = 2560 + 48 + 32,
2627 .htotal = 2560 + 48 + 32 + 80,
2628 .vdisplay = 1700,
2629 .vsync_start = 1700 + 3,
2630 .vsync_end = 1700 + 3 + 10,
2631 .vtotal = 1700 + 3 + 10 + 36,
2632 };
2633
2634 static const struct panel_desc lg_lp129qe = {
2635 .modes = &lg_lp129qe_mode,
2636 .num_modes = 1,
2637 .bpc = 8,
2638 .size = {
2639 .width = 272,
2640 .height = 181,
2641 },
2642 };
2643
2644 static const struct display_timing logictechno_lt161010_2nh_timing = {
2645 .pixelclock = { 26400000, 33300000, 46800000 },
2646 .hactive = { 800, 800, 800 },
2647 .hfront_porch = { 16, 210, 354 },
2648 .hback_porch = { 46, 46, 46 },
2649 .hsync_len = { 1, 20, 40 },
2650 .vactive = { 480, 480, 480 },
2651 .vfront_porch = { 7, 22, 147 },
2652 .vback_porch = { 23, 23, 23 },
2653 .vsync_len = { 1, 10, 20 },
2654 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2655 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2656 DISPLAY_FLAGS_SYNC_POSEDGE,
2657 };
2658
2659 static const struct panel_desc logictechno_lt161010_2nh = {
2660 .timings = &logictechno_lt161010_2nh_timing,
2661 .num_timings = 1,
2662 .bpc = 6,
2663 .size = {
2664 .width = 154,
2665 .height = 86,
2666 },
2667 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2668 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2669 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2670 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2671 .connector_type = DRM_MODE_CONNECTOR_DPI,
2672 };
2673
2674 static const struct display_timing logictechno_lt170410_2whc_timing = {
2675 .pixelclock = { 68900000, 71100000, 73400000 },
2676 .hactive = { 1280, 1280, 1280 },
2677 .hfront_porch = { 23, 60, 71 },
2678 .hback_porch = { 23, 60, 71 },
2679 .hsync_len = { 15, 40, 47 },
2680 .vactive = { 800, 800, 800 },
2681 .vfront_porch = { 5, 7, 10 },
2682 .vback_porch = { 5, 7, 10 },
2683 .vsync_len = { 6, 9, 12 },
2684 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2685 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2686 DISPLAY_FLAGS_SYNC_POSEDGE,
2687 };
2688
2689 static const struct panel_desc logictechno_lt170410_2whc = {
2690 .timings = &logictechno_lt170410_2whc_timing,
2691 .num_timings = 1,
2692 .bpc = 8,
2693 .size = {
2694 .width = 217,
2695 .height = 136,
2696 },
2697 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2698 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2699 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2700 };
2701
2702 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2703 .clock = 30400,
2704 .hdisplay = 800,
2705 .hsync_start = 800 + 0,
2706 .hsync_end = 800 + 1,
2707 .htotal = 800 + 0 + 1 + 160,
2708 .vdisplay = 480,
2709 .vsync_start = 480 + 0,
2710 .vsync_end = 480 + 48 + 1,
2711 .vtotal = 480 + 48 + 1 + 0,
2712 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2713 };
2714
2715 static const struct drm_display_mode logicpd_type_28_mode = {
2716 .clock = 9107,
2717 .hdisplay = 480,
2718 .hsync_start = 480 + 3,
2719 .hsync_end = 480 + 3 + 42,
2720 .htotal = 480 + 3 + 42 + 2,
2721
2722 .vdisplay = 272,
2723 .vsync_start = 272 + 2,
2724 .vsync_end = 272 + 2 + 11,
2725 .vtotal = 272 + 2 + 11 + 3,
2726 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2727 };
2728
2729 static const struct panel_desc logicpd_type_28 = {
2730 .modes = &logicpd_type_28_mode,
2731 .num_modes = 1,
2732 .bpc = 8,
2733 .size = {
2734 .width = 105,
2735 .height = 67,
2736 },
2737 .delay = {
2738 .prepare = 200,
2739 .enable = 200,
2740 .unprepare = 200,
2741 .disable = 200,
2742 },
2743 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2744 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2745 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2746 .connector_type = DRM_MODE_CONNECTOR_DPI,
2747 };
2748
2749 static const struct panel_desc mitsubishi_aa070mc01 = {
2750 .modes = &mitsubishi_aa070mc01_mode,
2751 .num_modes = 1,
2752 .bpc = 8,
2753 .size = {
2754 .width = 152,
2755 .height = 91,
2756 },
2757
2758 .delay = {
2759 .enable = 200,
2760 .unprepare = 200,
2761 .disable = 400,
2762 },
2763 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2764 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2765 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2766 };
2767
2768 static const struct display_timing nec_nl12880bc20_05_timing = {
2769 .pixelclock = { 67000000, 71000000, 75000000 },
2770 .hactive = { 1280, 1280, 1280 },
2771 .hfront_porch = { 2, 30, 30 },
2772 .hback_porch = { 6, 100, 100 },
2773 .hsync_len = { 2, 30, 30 },
2774 .vactive = { 800, 800, 800 },
2775 .vfront_porch = { 5, 5, 5 },
2776 .vback_porch = { 11, 11, 11 },
2777 .vsync_len = { 7, 7, 7 },
2778 };
2779
2780 static const struct panel_desc nec_nl12880bc20_05 = {
2781 .timings = &nec_nl12880bc20_05_timing,
2782 .num_timings = 1,
2783 .bpc = 8,
2784 .size = {
2785 .width = 261,
2786 .height = 163,
2787 },
2788 .delay = {
2789 .enable = 50,
2790 .disable = 50,
2791 },
2792 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2793 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2794 };
2795
2796 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2797 .clock = 10870,
2798 .hdisplay = 480,
2799 .hsync_start = 480 + 2,
2800 .hsync_end = 480 + 2 + 41,
2801 .htotal = 480 + 2 + 41 + 2,
2802 .vdisplay = 272,
2803 .vsync_start = 272 + 2,
2804 .vsync_end = 272 + 2 + 4,
2805 .vtotal = 272 + 2 + 4 + 2,
2806 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2807 };
2808
2809 static const struct panel_desc nec_nl4827hc19_05b = {
2810 .modes = &nec_nl4827hc19_05b_mode,
2811 .num_modes = 1,
2812 .bpc = 8,
2813 .size = {
2814 .width = 95,
2815 .height = 54,
2816 },
2817 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2818 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2819 };
2820
2821 static const struct drm_display_mode netron_dy_e231732_mode = {
2822 .clock = 66000,
2823 .hdisplay = 1024,
2824 .hsync_start = 1024 + 160,
2825 .hsync_end = 1024 + 160 + 70,
2826 .htotal = 1024 + 160 + 70 + 90,
2827 .vdisplay = 600,
2828 .vsync_start = 600 + 127,
2829 .vsync_end = 600 + 127 + 20,
2830 .vtotal = 600 + 127 + 20 + 3,
2831 };
2832
2833 static const struct panel_desc netron_dy_e231732 = {
2834 .modes = &netron_dy_e231732_mode,
2835 .num_modes = 1,
2836 .size = {
2837 .width = 154,
2838 .height = 87,
2839 },
2840 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2841 };
2842
2843 static const struct drm_display_mode neweast_wjfh116008a_modes[] = {
2844 {
2845 .clock = 138500,
2846 .hdisplay = 1920,
2847 .hsync_start = 1920 + 48,
2848 .hsync_end = 1920 + 48 + 32,
2849 .htotal = 1920 + 48 + 32 + 80,
2850 .vdisplay = 1080,
2851 .vsync_start = 1080 + 3,
2852 .vsync_end = 1080 + 3 + 5,
2853 .vtotal = 1080 + 3 + 5 + 23,
2854 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2855 }, {
2856 .clock = 110920,
2857 .hdisplay = 1920,
2858 .hsync_start = 1920 + 48,
2859 .hsync_end = 1920 + 48 + 32,
2860 .htotal = 1920 + 48 + 32 + 80,
2861 .vdisplay = 1080,
2862 .vsync_start = 1080 + 3,
2863 .vsync_end = 1080 + 3 + 5,
2864 .vtotal = 1080 + 3 + 5 + 23,
2865 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2866 }
2867 };
2868
2869 static const struct panel_desc neweast_wjfh116008a = {
2870 .modes = neweast_wjfh116008a_modes,
2871 .num_modes = 2,
2872 .bpc = 6,
2873 .size = {
2874 .width = 260,
2875 .height = 150,
2876 },
2877 .delay = {
2878 .prepare = 110,
2879 .enable = 20,
2880 .unprepare = 500,
2881 },
2882 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2883 .connector_type = DRM_MODE_CONNECTOR_eDP,
2884 };
2885
2886 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2887 .clock = 9000,
2888 .hdisplay = 480,
2889 .hsync_start = 480 + 2,
2890 .hsync_end = 480 + 2 + 41,
2891 .htotal = 480 + 2 + 41 + 2,
2892 .vdisplay = 272,
2893 .vsync_start = 272 + 2,
2894 .vsync_end = 272 + 2 + 10,
2895 .vtotal = 272 + 2 + 10 + 2,
2896 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2897 };
2898
2899 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2900 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2901 .num_modes = 1,
2902 .bpc = 8,
2903 .size = {
2904 .width = 95,
2905 .height = 54,
2906 },
2907 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2908 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2909 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2910 .connector_type = DRM_MODE_CONNECTOR_DPI,
2911 };
2912
2913 static const struct display_timing nlt_nl192108ac18_02d_timing = {
2914 .pixelclock = { 130000000, 148350000, 163000000 },
2915 .hactive = { 1920, 1920, 1920 },
2916 .hfront_porch = { 80, 100, 100 },
2917 .hback_porch = { 100, 120, 120 },
2918 .hsync_len = { 50, 60, 60 },
2919 .vactive = { 1080, 1080, 1080 },
2920 .vfront_porch = { 12, 30, 30 },
2921 .vback_porch = { 4, 10, 10 },
2922 .vsync_len = { 4, 5, 5 },
2923 };
2924
2925 static const struct panel_desc nlt_nl192108ac18_02d = {
2926 .timings = &nlt_nl192108ac18_02d_timing,
2927 .num_timings = 1,
2928 .bpc = 8,
2929 .size = {
2930 .width = 344,
2931 .height = 194,
2932 },
2933 .delay = {
2934 .unprepare = 500,
2935 },
2936 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2937 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2938 };
2939
2940 static const struct drm_display_mode nvd_9128_mode = {
2941 .clock = 29500,
2942 .hdisplay = 800,
2943 .hsync_start = 800 + 130,
2944 .hsync_end = 800 + 130 + 98,
2945 .htotal = 800 + 0 + 130 + 98,
2946 .vdisplay = 480,
2947 .vsync_start = 480 + 10,
2948 .vsync_end = 480 + 10 + 50,
2949 .vtotal = 480 + 0 + 10 + 50,
2950 };
2951
2952 static const struct panel_desc nvd_9128 = {
2953 .modes = &nvd_9128_mode,
2954 .num_modes = 1,
2955 .bpc = 8,
2956 .size = {
2957 .width = 156,
2958 .height = 88,
2959 },
2960 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2961 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2962 };
2963
2964 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2965 .pixelclock = { 30000000, 30000000, 40000000 },
2966 .hactive = { 800, 800, 800 },
2967 .hfront_porch = { 40, 40, 40 },
2968 .hback_porch = { 40, 40, 40 },
2969 .hsync_len = { 1, 48, 48 },
2970 .vactive = { 480, 480, 480 },
2971 .vfront_porch = { 13, 13, 13 },
2972 .vback_porch = { 29, 29, 29 },
2973 .vsync_len = { 3, 3, 3 },
2974 .flags = DISPLAY_FLAGS_DE_HIGH,
2975 };
2976
2977 static const struct panel_desc okaya_rs800480t_7x0gp = {
2978 .timings = &okaya_rs800480t_7x0gp_timing,
2979 .num_timings = 1,
2980 .bpc = 6,
2981 .size = {
2982 .width = 154,
2983 .height = 87,
2984 },
2985 .delay = {
2986 .prepare = 41,
2987 .enable = 50,
2988 .unprepare = 41,
2989 .disable = 50,
2990 },
2991 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2992 };
2993
2994 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
2995 .clock = 9000,
2996 .hdisplay = 480,
2997 .hsync_start = 480 + 5,
2998 .hsync_end = 480 + 5 + 30,
2999 .htotal = 480 + 5 + 30 + 10,
3000 .vdisplay = 272,
3001 .vsync_start = 272 + 8,
3002 .vsync_end = 272 + 8 + 5,
3003 .vtotal = 272 + 8 + 5 + 3,
3004 };
3005
3006 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3007 .modes = &olimex_lcd_olinuxino_43ts_mode,
3008 .num_modes = 1,
3009 .size = {
3010 .width = 95,
3011 .height = 54,
3012 },
3013 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3014 };
3015
3016 /*
3017 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3018 * pixel clocks, but this is the timing that was being used in the Adafruit
3019 * installation instructions.
3020 */
3021 static const struct drm_display_mode ontat_yx700wv03_mode = {
3022 .clock = 29500,
3023 .hdisplay = 800,
3024 .hsync_start = 824,
3025 .hsync_end = 896,
3026 .htotal = 992,
3027 .vdisplay = 480,
3028 .vsync_start = 483,
3029 .vsync_end = 493,
3030 .vtotal = 500,
3031 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3032 };
3033
3034 /*
3035 * Specification at:
3036 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3037 */
3038 static const struct panel_desc ontat_yx700wv03 = {
3039 .modes = &ontat_yx700wv03_mode,
3040 .num_modes = 1,
3041 .bpc = 8,
3042 .size = {
3043 .width = 154,
3044 .height = 83,
3045 },
3046 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3047 };
3048
3049 static const struct drm_display_mode ortustech_com37h3m_mode = {
3050 .clock = 22230,
3051 .hdisplay = 480,
3052 .hsync_start = 480 + 40,
3053 .hsync_end = 480 + 40 + 10,
3054 .htotal = 480 + 40 + 10 + 40,
3055 .vdisplay = 640,
3056 .vsync_start = 640 + 4,
3057 .vsync_end = 640 + 4 + 2,
3058 .vtotal = 640 + 4 + 2 + 4,
3059 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3060 };
3061
3062 static const struct panel_desc ortustech_com37h3m = {
3063 .modes = &ortustech_com37h3m_mode,
3064 .num_modes = 1,
3065 .bpc = 8,
3066 .size = {
3067 .width = 56, /* 56.16mm */
3068 .height = 75, /* 74.88mm */
3069 },
3070 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3071 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3072 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3073 };
3074
3075 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3076 .clock = 25000,
3077 .hdisplay = 480,
3078 .hsync_start = 480 + 10,
3079 .hsync_end = 480 + 10 + 10,
3080 .htotal = 480 + 10 + 10 + 15,
3081 .vdisplay = 800,
3082 .vsync_start = 800 + 3,
3083 .vsync_end = 800 + 3 + 3,
3084 .vtotal = 800 + 3 + 3 + 3,
3085 };
3086
3087 static const struct panel_desc ortustech_com43h4m85ulc = {
3088 .modes = &ortustech_com43h4m85ulc_mode,
3089 .num_modes = 1,
3090 .bpc = 6,
3091 .size = {
3092 .width = 56,
3093 .height = 93,
3094 },
3095 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3096 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3097 .connector_type = DRM_MODE_CONNECTOR_DPI,
3098 };
3099
3100 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3101 .clock = 33000,
3102 .hdisplay = 800,
3103 .hsync_start = 800 + 210,
3104 .hsync_end = 800 + 210 + 30,
3105 .htotal = 800 + 210 + 30 + 16,
3106 .vdisplay = 480,
3107 .vsync_start = 480 + 22,
3108 .vsync_end = 480 + 22 + 13,
3109 .vtotal = 480 + 22 + 13 + 10,
3110 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3111 };
3112
3113 static const struct panel_desc osddisplays_osd070t1718_19ts = {
3114 .modes = &osddisplays_osd070t1718_19ts_mode,
3115 .num_modes = 1,
3116 .bpc = 8,
3117 .size = {
3118 .width = 152,
3119 .height = 91,
3120 },
3121 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3122 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3123 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3124 .connector_type = DRM_MODE_CONNECTOR_DPI,
3125 };
3126
3127 static const struct drm_display_mode pda_91_00156_a0_mode = {
3128 .clock = 33300,
3129 .hdisplay = 800,
3130 .hsync_start = 800 + 1,
3131 .hsync_end = 800 + 1 + 64,
3132 .htotal = 800 + 1 + 64 + 64,
3133 .vdisplay = 480,
3134 .vsync_start = 480 + 1,
3135 .vsync_end = 480 + 1 + 23,
3136 .vtotal = 480 + 1 + 23 + 22,
3137 };
3138
3139 static const struct panel_desc pda_91_00156_a0 = {
3140 .modes = &pda_91_00156_a0_mode,
3141 .num_modes = 1,
3142 .size = {
3143 .width = 152,
3144 .height = 91,
3145 },
3146 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3147 };
3148
3149 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3150 .clock = 24750,
3151 .hdisplay = 800,
3152 .hsync_start = 800 + 54,
3153 .hsync_end = 800 + 54 + 2,
3154 .htotal = 800 + 54 + 2 + 44,
3155 .vdisplay = 480,
3156 .vsync_start = 480 + 49,
3157 .vsync_end = 480 + 49 + 2,
3158 .vtotal = 480 + 49 + 2 + 22,
3159 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3160 };
3161
3162 static const struct panel_desc powertip_ph800480t013_idf02 = {
3163 .modes = &powertip_ph800480t013_idf02_mode,
3164 .num_modes = 1,
3165 .size = {
3166 .width = 152,
3167 .height = 91,
3168 },
3169 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3170 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3171 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3172 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3173 .connector_type = DRM_MODE_CONNECTOR_DPI,
3174 };
3175
3176 static const struct drm_display_mode qd43003c0_40_mode = {
3177 .clock = 9000,
3178 .hdisplay = 480,
3179 .hsync_start = 480 + 8,
3180 .hsync_end = 480 + 8 + 4,
3181 .htotal = 480 + 8 + 4 + 39,
3182 .vdisplay = 272,
3183 .vsync_start = 272 + 4,
3184 .vsync_end = 272 + 4 + 10,
3185 .vtotal = 272 + 4 + 10 + 2,
3186 };
3187
3188 static const struct panel_desc qd43003c0_40 = {
3189 .modes = &qd43003c0_40_mode,
3190 .num_modes = 1,
3191 .bpc = 8,
3192 .size = {
3193 .width = 95,
3194 .height = 53,
3195 },
3196 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3197 };
3198
3199 static const struct display_timing rocktech_rk070er9427_timing = {
3200 .pixelclock = { 26400000, 33300000, 46800000 },
3201 .hactive = { 800, 800, 800 },
3202 .hfront_porch = { 16, 210, 354 },
3203 .hback_porch = { 46, 46, 46 },
3204 .hsync_len = { 1, 1, 1 },
3205 .vactive = { 480, 480, 480 },
3206 .vfront_porch = { 7, 22, 147 },
3207 .vback_porch = { 23, 23, 23 },
3208 .vsync_len = { 1, 1, 1 },
3209 .flags = DISPLAY_FLAGS_DE_HIGH,
3210 };
3211
3212 static const struct panel_desc rocktech_rk070er9427 = {
3213 .timings = &rocktech_rk070er9427_timing,
3214 .num_timings = 1,
3215 .bpc = 6,
3216 .size = {
3217 .width = 154,
3218 .height = 86,
3219 },
3220 .delay = {
3221 .prepare = 41,
3222 .enable = 50,
3223 .unprepare = 41,
3224 .disable = 50,
3225 },
3226 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3227 };
3228
3229 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3230 .clock = 71100,
3231 .hdisplay = 1280,
3232 .hsync_start = 1280 + 48,
3233 .hsync_end = 1280 + 48 + 32,
3234 .htotal = 1280 + 48 + 32 + 80,
3235 .vdisplay = 800,
3236 .vsync_start = 800 + 2,
3237 .vsync_end = 800 + 2 + 5,
3238 .vtotal = 800 + 2 + 5 + 16,
3239 };
3240
3241 static const struct panel_desc rocktech_rk101ii01d_ct = {
3242 .modes = &rocktech_rk101ii01d_ct_mode,
3243 .num_modes = 1,
3244 .size = {
3245 .width = 217,
3246 .height = 136,
3247 },
3248 .delay = {
3249 .prepare = 50,
3250 .disable = 50,
3251 },
3252 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3253 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3254 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3255 };
3256
3257 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
3258 .clock = 271560,
3259 .hdisplay = 2560,
3260 .hsync_start = 2560 + 48,
3261 .hsync_end = 2560 + 48 + 32,
3262 .htotal = 2560 + 48 + 32 + 80,
3263 .vdisplay = 1600,
3264 .vsync_start = 1600 + 2,
3265 .vsync_end = 1600 + 2 + 5,
3266 .vtotal = 1600 + 2 + 5 + 57,
3267 };
3268
3269 static const struct panel_desc samsung_lsn122dl01_c01 = {
3270 .modes = &samsung_lsn122dl01_c01_mode,
3271 .num_modes = 1,
3272 .size = {
3273 .width = 263,
3274 .height = 164,
3275 },
3276 };
3277
3278 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3279 .clock = 54030,
3280 .hdisplay = 1024,
3281 .hsync_start = 1024 + 24,
3282 .hsync_end = 1024 + 24 + 136,
3283 .htotal = 1024 + 24 + 136 + 160,
3284 .vdisplay = 600,
3285 .vsync_start = 600 + 3,
3286 .vsync_end = 600 + 3 + 6,
3287 .vtotal = 600 + 3 + 6 + 61,
3288 };
3289
3290 static const struct panel_desc samsung_ltn101nt05 = {
3291 .modes = &samsung_ltn101nt05_mode,
3292 .num_modes = 1,
3293 .bpc = 6,
3294 .size = {
3295 .width = 223,
3296 .height = 125,
3297 },
3298 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3299 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3300 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3301 };
3302
3303 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
3304 .clock = 76300,
3305 .hdisplay = 1366,
3306 .hsync_start = 1366 + 64,
3307 .hsync_end = 1366 + 64 + 48,
3308 .htotal = 1366 + 64 + 48 + 128,
3309 .vdisplay = 768,
3310 .vsync_start = 768 + 2,
3311 .vsync_end = 768 + 2 + 5,
3312 .vtotal = 768 + 2 + 5 + 17,
3313 };
3314
3315 static const struct panel_desc samsung_ltn140at29_301 = {
3316 .modes = &samsung_ltn140at29_301_mode,
3317 .num_modes = 1,
3318 .bpc = 6,
3319 .size = {
3320 .width = 320,
3321 .height = 187,
3322 },
3323 };
3324
3325 static const struct display_timing satoz_sat050at40h12r2_timing = {
3326 .pixelclock = {33300000, 33300000, 50000000},
3327 .hactive = {800, 800, 800},
3328 .hfront_porch = {16, 210, 354},
3329 .hback_porch = {46, 46, 46},
3330 .hsync_len = {1, 1, 40},
3331 .vactive = {480, 480, 480},
3332 .vfront_porch = {7, 22, 147},
3333 .vback_porch = {23, 23, 23},
3334 .vsync_len = {1, 1, 20},
3335 };
3336
3337 static const struct panel_desc satoz_sat050at40h12r2 = {
3338 .timings = &satoz_sat050at40h12r2_timing,
3339 .num_timings = 1,
3340 .bpc = 8,
3341 .size = {
3342 .width = 108,
3343 .height = 65,
3344 },
3345 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3346 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3347 };
3348
3349 static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
3350 .clock = 168480,
3351 .hdisplay = 1920,
3352 .hsync_start = 1920 + 48,
3353 .hsync_end = 1920 + 48 + 32,
3354 .htotal = 1920 + 48 + 32 + 80,
3355 .vdisplay = 1280,
3356 .vsync_start = 1280 + 3,
3357 .vsync_end = 1280 + 3 + 10,
3358 .vtotal = 1280 + 3 + 10 + 57,
3359 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3360 };
3361
3362 static const struct panel_desc sharp_ld_d5116z01b = {
3363 .modes = &sharp_ld_d5116z01b_mode,
3364 .num_modes = 1,
3365 .bpc = 8,
3366 .size = {
3367 .width = 260,
3368 .height = 120,
3369 },
3370 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3371 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
3372 };
3373
3374 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3375 .clock = 33260,
3376 .hdisplay = 800,
3377 .hsync_start = 800 + 64,
3378 .hsync_end = 800 + 64 + 128,
3379 .htotal = 800 + 64 + 128 + 64,
3380 .vdisplay = 480,
3381 .vsync_start = 480 + 8,
3382 .vsync_end = 480 + 8 + 2,
3383 .vtotal = 480 + 8 + 2 + 35,
3384 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3385 };
3386
3387 static const struct panel_desc sharp_lq070y3dg3b = {
3388 .modes = &sharp_lq070y3dg3b_mode,
3389 .num_modes = 1,
3390 .bpc = 8,
3391 .size = {
3392 .width = 152, /* 152.4mm */
3393 .height = 91, /* 91.4mm */
3394 },
3395 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3396 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3397 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3398 };
3399
3400 static const struct drm_display_mode sharp_lq035q7db03_mode = {
3401 .clock = 5500,
3402 .hdisplay = 240,
3403 .hsync_start = 240 + 16,
3404 .hsync_end = 240 + 16 + 7,
3405 .htotal = 240 + 16 + 7 + 5,
3406 .vdisplay = 320,
3407 .vsync_start = 320 + 9,
3408 .vsync_end = 320 + 9 + 1,
3409 .vtotal = 320 + 9 + 1 + 7,
3410 };
3411
3412 static const struct panel_desc sharp_lq035q7db03 = {
3413 .modes = &sharp_lq035q7db03_mode,
3414 .num_modes = 1,
3415 .bpc = 6,
3416 .size = {
3417 .width = 54,
3418 .height = 72,
3419 },
3420 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3421 };
3422
3423 static const struct display_timing sharp_lq101k1ly04_timing = {
3424 .pixelclock = { 60000000, 65000000, 80000000 },
3425 .hactive = { 1280, 1280, 1280 },
3426 .hfront_porch = { 20, 20, 20 },
3427 .hback_porch = { 20, 20, 20 },
3428 .hsync_len = { 10, 10, 10 },
3429 .vactive = { 800, 800, 800 },
3430 .vfront_porch = { 4, 4, 4 },
3431 .vback_porch = { 4, 4, 4 },
3432 .vsync_len = { 4, 4, 4 },
3433 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3434 };
3435
3436 static const struct panel_desc sharp_lq101k1ly04 = {
3437 .timings = &sharp_lq101k1ly04_timing,
3438 .num_timings = 1,
3439 .bpc = 8,
3440 .size = {
3441 .width = 217,
3442 .height = 136,
3443 },
3444 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3445 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3446 };
3447
3448 static const struct display_timing sharp_lq123p1jx31_timing = {
3449 .pixelclock = { 252750000, 252750000, 266604720 },
3450 .hactive = { 2400, 2400, 2400 },
3451 .hfront_porch = { 48, 48, 48 },
3452 .hback_porch = { 80, 80, 84 },
3453 .hsync_len = { 32, 32, 32 },
3454 .vactive = { 1600, 1600, 1600 },
3455 .vfront_porch = { 3, 3, 3 },
3456 .vback_porch = { 33, 33, 120 },
3457 .vsync_len = { 10, 10, 10 },
3458 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
3459 };
3460
3461 static const struct panel_desc sharp_lq123p1jx31 = {
3462 .timings = &sharp_lq123p1jx31_timing,
3463 .num_timings = 1,
3464 .bpc = 8,
3465 .size = {
3466 .width = 259,
3467 .height = 173,
3468 },
3469 .delay = {
3470 .prepare = 110,
3471 .enable = 50,
3472 .unprepare = 550,
3473 },
3474 };
3475
3476 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
3477 { /* 50 Hz */
3478 .clock = 3000,
3479 .hdisplay = 240,
3480 .hsync_start = 240 + 58,
3481 .hsync_end = 240 + 58 + 1,
3482 .htotal = 240 + 58 + 1 + 1,
3483 .vdisplay = 160,
3484 .vsync_start = 160 + 24,
3485 .vsync_end = 160 + 24 + 10,
3486 .vtotal = 160 + 24 + 10 + 6,
3487 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3488 },
3489 { /* 60 Hz */
3490 .clock = 3000,
3491 .hdisplay = 240,
3492 .hsync_start = 240 + 8,
3493 .hsync_end = 240 + 8 + 1,
3494 .htotal = 240 + 8 + 1 + 1,
3495 .vdisplay = 160,
3496 .vsync_start = 160 + 24,
3497 .vsync_end = 160 + 24 + 10,
3498 .vtotal = 160 + 24 + 10 + 6,
3499 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3500 },
3501 };
3502
3503 static const struct panel_desc sharp_ls020b1dd01d = {
3504 .modes = sharp_ls020b1dd01d_modes,
3505 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
3506 .bpc = 6,
3507 .size = {
3508 .width = 42,
3509 .height = 28,
3510 },
3511 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3512 .bus_flags = DRM_BUS_FLAG_DE_HIGH
3513 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
3514 | DRM_BUS_FLAG_SHARP_SIGNALS,
3515 };
3516
3517 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3518 .clock = 33300,
3519 .hdisplay = 800,
3520 .hsync_start = 800 + 1,
3521 .hsync_end = 800 + 1 + 64,
3522 .htotal = 800 + 1 + 64 + 64,
3523 .vdisplay = 480,
3524 .vsync_start = 480 + 1,
3525 .vsync_end = 480 + 1 + 23,
3526 .vtotal = 480 + 1 + 23 + 22,
3527 };
3528
3529 static const struct panel_desc shelly_sca07010_bfn_lnn = {
3530 .modes = &shelly_sca07010_bfn_lnn_mode,
3531 .num_modes = 1,
3532 .size = {
3533 .width = 152,
3534 .height = 91,
3535 },
3536 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3537 };
3538
3539 static const struct drm_display_mode starry_kr070pe2t_mode = {
3540 .clock = 33000,
3541 .hdisplay = 800,
3542 .hsync_start = 800 + 209,
3543 .hsync_end = 800 + 209 + 1,
3544 .htotal = 800 + 209 + 1 + 45,
3545 .vdisplay = 480,
3546 .vsync_start = 480 + 22,
3547 .vsync_end = 480 + 22 + 1,
3548 .vtotal = 480 + 22 + 1 + 22,
3549 };
3550
3551 static const struct panel_desc starry_kr070pe2t = {
3552 .modes = &starry_kr070pe2t_mode,
3553 .num_modes = 1,
3554 .bpc = 8,
3555 .size = {
3556 .width = 152,
3557 .height = 86,
3558 },
3559 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3560 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3561 .connector_type = DRM_MODE_CONNECTOR_DPI,
3562 };
3563
3564 static const struct drm_display_mode starry_kr122ea0sra_mode = {
3565 .clock = 147000,
3566 .hdisplay = 1920,
3567 .hsync_start = 1920 + 16,
3568 .hsync_end = 1920 + 16 + 16,
3569 .htotal = 1920 + 16 + 16 + 32,
3570 .vdisplay = 1200,
3571 .vsync_start = 1200 + 15,
3572 .vsync_end = 1200 + 15 + 2,
3573 .vtotal = 1200 + 15 + 2 + 18,
3574 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3575 };
3576
3577 static const struct panel_desc starry_kr122ea0sra = {
3578 .modes = &starry_kr122ea0sra_mode,
3579 .num_modes = 1,
3580 .size = {
3581 .width = 263,
3582 .height = 164,
3583 },
3584 .delay = {
3585 .prepare = 10 + 200,
3586 .enable = 50,
3587 .unprepare = 10 + 500,
3588 },
3589 };
3590
3591 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3592 .clock = 30000,
3593 .hdisplay = 800,
3594 .hsync_start = 800 + 39,
3595 .hsync_end = 800 + 39 + 47,
3596 .htotal = 800 + 39 + 47 + 39,
3597 .vdisplay = 480,
3598 .vsync_start = 480 + 13,
3599 .vsync_end = 480 + 13 + 2,
3600 .vtotal = 480 + 13 + 2 + 29,
3601 };
3602
3603 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3604 .modes = &tfc_s9700rtwv43tr_01b_mode,
3605 .num_modes = 1,
3606 .bpc = 8,
3607 .size = {
3608 .width = 155,
3609 .height = 90,
3610 },
3611 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3612 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3613 };
3614
3615 static const struct display_timing tianma_tm070jdhg30_timing = {
3616 .pixelclock = { 62600000, 68200000, 78100000 },
3617 .hactive = { 1280, 1280, 1280 },
3618 .hfront_porch = { 15, 64, 159 },
3619 .hback_porch = { 5, 5, 5 },
3620 .hsync_len = { 1, 1, 256 },
3621 .vactive = { 800, 800, 800 },
3622 .vfront_porch = { 3, 40, 99 },
3623 .vback_porch = { 2, 2, 2 },
3624 .vsync_len = { 1, 1, 128 },
3625 .flags = DISPLAY_FLAGS_DE_HIGH,
3626 };
3627
3628 static const struct panel_desc tianma_tm070jdhg30 = {
3629 .timings = &tianma_tm070jdhg30_timing,
3630 .num_timings = 1,
3631 .bpc = 8,
3632 .size = {
3633 .width = 151,
3634 .height = 95,
3635 },
3636 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3637 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3638 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3639 };
3640
3641 static const struct panel_desc tianma_tm070jvhg33 = {
3642 .timings = &tianma_tm070jdhg30_timing,
3643 .num_timings = 1,
3644 .bpc = 8,
3645 .size = {
3646 .width = 150,
3647 .height = 94,
3648 },
3649 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3650 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3651 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3652 };
3653
3654 static const struct display_timing tianma_tm070rvhg71_timing = {
3655 .pixelclock = { 27700000, 29200000, 39600000 },
3656 .hactive = { 800, 800, 800 },
3657 .hfront_porch = { 12, 40, 212 },
3658 .hback_porch = { 88, 88, 88 },
3659 .hsync_len = { 1, 1, 40 },
3660 .vactive = { 480, 480, 480 },
3661 .vfront_porch = { 1, 13, 88 },
3662 .vback_porch = { 32, 32, 32 },
3663 .vsync_len = { 1, 1, 3 },
3664 .flags = DISPLAY_FLAGS_DE_HIGH,
3665 };
3666
3667 static const struct panel_desc tianma_tm070rvhg71 = {
3668 .timings = &tianma_tm070rvhg71_timing,
3669 .num_timings = 1,
3670 .bpc = 8,
3671 .size = {
3672 .width = 154,
3673 .height = 86,
3674 },
3675 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3676 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3677 };
3678
3679 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3680 {
3681 .clock = 10000,
3682 .hdisplay = 320,
3683 .hsync_start = 320 + 50,
3684 .hsync_end = 320 + 50 + 6,
3685 .htotal = 320 + 50 + 6 + 38,
3686 .vdisplay = 240,
3687 .vsync_start = 240 + 3,
3688 .vsync_end = 240 + 3 + 1,
3689 .vtotal = 240 + 3 + 1 + 17,
3690 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3691 },
3692 };
3693
3694 static const struct panel_desc ti_nspire_cx_lcd_panel = {
3695 .modes = ti_nspire_cx_lcd_mode,
3696 .num_modes = 1,
3697 .bpc = 8,
3698 .size = {
3699 .width = 65,
3700 .height = 49,
3701 },
3702 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3703 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3704 };
3705
3706 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3707 {
3708 .clock = 10000,
3709 .hdisplay = 320,
3710 .hsync_start = 320 + 6,
3711 .hsync_end = 320 + 6 + 6,
3712 .htotal = 320 + 6 + 6 + 6,
3713 .vdisplay = 240,
3714 .vsync_start = 240 + 0,
3715 .vsync_end = 240 + 0 + 1,
3716 .vtotal = 240 + 0 + 1 + 0,
3717 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3718 },
3719 };
3720
3721 static const struct panel_desc ti_nspire_classic_lcd_panel = {
3722 .modes = ti_nspire_classic_lcd_mode,
3723 .num_modes = 1,
3724 /* The grayscale panel has 8 bit for the color .. Y (black) */
3725 .bpc = 8,
3726 .size = {
3727 .width = 71,
3728 .height = 53,
3729 },
3730 /* This is the grayscale bus format */
3731 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
3732 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3733 };
3734
3735 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3736 .clock = 79500,
3737 .hdisplay = 1280,
3738 .hsync_start = 1280 + 192,
3739 .hsync_end = 1280 + 192 + 128,
3740 .htotal = 1280 + 192 + 128 + 64,
3741 .vdisplay = 768,
3742 .vsync_start = 768 + 20,
3743 .vsync_end = 768 + 20 + 7,
3744 .vtotal = 768 + 20 + 7 + 3,
3745 };
3746
3747 static const struct panel_desc toshiba_lt089ac29000 = {
3748 .modes = &toshiba_lt089ac29000_mode,
3749 .num_modes = 1,
3750 .size = {
3751 .width = 194,
3752 .height = 116,
3753 },
3754 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3755 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3756 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3757 };
3758
3759 static const struct drm_display_mode tpk_f07a_0102_mode = {
3760 .clock = 33260,
3761 .hdisplay = 800,
3762 .hsync_start = 800 + 40,
3763 .hsync_end = 800 + 40 + 128,
3764 .htotal = 800 + 40 + 128 + 88,
3765 .vdisplay = 480,
3766 .vsync_start = 480 + 10,
3767 .vsync_end = 480 + 10 + 2,
3768 .vtotal = 480 + 10 + 2 + 33,
3769 };
3770
3771 static const struct panel_desc tpk_f07a_0102 = {
3772 .modes = &tpk_f07a_0102_mode,
3773 .num_modes = 1,
3774 .size = {
3775 .width = 152,
3776 .height = 91,
3777 },
3778 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3779 };
3780
3781 static const struct drm_display_mode tpk_f10a_0102_mode = {
3782 .clock = 45000,
3783 .hdisplay = 1024,
3784 .hsync_start = 1024 + 176,
3785 .hsync_end = 1024 + 176 + 5,
3786 .htotal = 1024 + 176 + 5 + 88,
3787 .vdisplay = 600,
3788 .vsync_start = 600 + 20,
3789 .vsync_end = 600 + 20 + 5,
3790 .vtotal = 600 + 20 + 5 + 25,
3791 };
3792
3793 static const struct panel_desc tpk_f10a_0102 = {
3794 .modes = &tpk_f10a_0102_mode,
3795 .num_modes = 1,
3796 .size = {
3797 .width = 223,
3798 .height = 125,
3799 },
3800 };
3801
3802 static const struct display_timing urt_umsh_8596md_timing = {
3803 .pixelclock = { 33260000, 33260000, 33260000 },
3804 .hactive = { 800, 800, 800 },
3805 .hfront_porch = { 41, 41, 41 },
3806 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3807 .hsync_len = { 71, 128, 128 },
3808 .vactive = { 480, 480, 480 },
3809 .vfront_porch = { 10, 10, 10 },
3810 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3811 .vsync_len = { 2, 2, 2 },
3812 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3813 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3814 };
3815
3816 static const struct panel_desc urt_umsh_8596md_lvds = {
3817 .timings = &urt_umsh_8596md_timing,
3818 .num_timings = 1,
3819 .bpc = 6,
3820 .size = {
3821 .width = 152,
3822 .height = 91,
3823 },
3824 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3825 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3826 };
3827
3828 static const struct panel_desc urt_umsh_8596md_parallel = {
3829 .timings = &urt_umsh_8596md_timing,
3830 .num_timings = 1,
3831 .bpc = 6,
3832 .size = {
3833 .width = 152,
3834 .height = 91,
3835 },
3836 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3837 };
3838
3839 static const struct drm_display_mode vl050_8048nt_c01_mode = {
3840 .clock = 33333,
3841 .hdisplay = 800,
3842 .hsync_start = 800 + 210,
3843 .hsync_end = 800 + 210 + 20,
3844 .htotal = 800 + 210 + 20 + 46,
3845 .vdisplay = 480,
3846 .vsync_start = 480 + 22,
3847 .vsync_end = 480 + 22 + 10,
3848 .vtotal = 480 + 22 + 10 + 23,
3849 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3850 };
3851
3852 static const struct panel_desc vl050_8048nt_c01 = {
3853 .modes = &vl050_8048nt_c01_mode,
3854 .num_modes = 1,
3855 .bpc = 8,
3856 .size = {
3857 .width = 120,
3858 .height = 76,
3859 },
3860 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3861 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3862 };
3863
3864 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3865 .clock = 6410,
3866 .hdisplay = 320,
3867 .hsync_start = 320 + 20,
3868 .hsync_end = 320 + 20 + 30,
3869 .htotal = 320 + 20 + 30 + 38,
3870 .vdisplay = 240,
3871 .vsync_start = 240 + 4,
3872 .vsync_end = 240 + 4 + 3,
3873 .vtotal = 240 + 4 + 3 + 15,
3874 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3875 };
3876
3877 static const struct panel_desc winstar_wf35ltiacd = {
3878 .modes = &winstar_wf35ltiacd_mode,
3879 .num_modes = 1,
3880 .bpc = 8,
3881 .size = {
3882 .width = 70,
3883 .height = 53,
3884 },
3885 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3886 };
3887
3888 static const struct drm_display_mode arm_rtsm_mode[] = {
3889 {
3890 .clock = 65000,
3891 .hdisplay = 1024,
3892 .hsync_start = 1024 + 24,
3893 .hsync_end = 1024 + 24 + 136,
3894 .htotal = 1024 + 24 + 136 + 160,
3895 .vdisplay = 768,
3896 .vsync_start = 768 + 3,
3897 .vsync_end = 768 + 3 + 6,
3898 .vtotal = 768 + 3 + 6 + 29,
3899 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3900 },
3901 };
3902
3903 static const struct panel_desc arm_rtsm = {
3904 .modes = arm_rtsm_mode,
3905 .num_modes = 1,
3906 .bpc = 8,
3907 .size = {
3908 .width = 400,
3909 .height = 300,
3910 },
3911 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3912 };
3913
3914 static const struct of_device_id platform_of_match[] = {
3915 {
3916 .compatible = "ampire,am-1280800n3tzqw-t00h",
3917 .data = &ire_am_1280800n3tzqw_t00h,
3918 }, {
3919 .compatible = "ampire,am-480272h3tmqw-t01h",
3920 .data = &ire_am_480272h3tmqw_t01h,
3921 }, {
3922 .compatible = "ampire,am800480r3tmqwa1h",
3923 .data = &ire_am800480r3tmqwa1h,
3924 }, {
3925 .compatible = "arm,rtsm-display",
3926 .data = &arm_rtsm,
3927 }, {
3928 .compatible = "armadeus,st0700-adapt",
3929 .data = &armadeus_st0700_adapt,
3930 }, {
3931 .compatible = "auo,b101aw03",
3932 .data = &auo_b101aw03,
3933 }, {
3934 .compatible = "auo,b101ean01",
3935 .data = &auo_b101ean01,
3936 }, {
3937 .compatible = "auo,b101xtn01",
3938 .data = &auo_b101xtn01,
3939 }, {
3940 .compatible = "auo,b116xa01",
3941 .data = &auo_b116xak01,
3942 }, {
3943 .compatible = "auo,b116xw03",
3944 .data = &auo_b116xw03,
3945 }, {
3946 .compatible = "auo,b133htn01",
3947 .data = &auo_b133htn01,
3948 }, {
3949 .compatible = "auo,b133xtn01",
3950 .data = &auo_b133xtn01,
3951 }, {
3952 .compatible = "auo,g070vvn01",
3953 .data = &auo_g070vvn01,
3954 }, {
3955 .compatible = "auo,g101evn010",
3956 .data = &auo_g101evn010,
3957 }, {
3958 .compatible = "auo,g104sn02",
3959 .data = &auo_g104sn02,
3960 }, {
3961 .compatible = "auo,g121ean01",
3962 .data = &auo_g121ean01,
3963 }, {
3964 .compatible = "auo,g133han01",
3965 .data = &auo_g133han01,
3966 }, {
3967 .compatible = "auo,g156xtn01",
3968 .data = &auo_g156xtn01,
3969 }, {
3970 .compatible = "auo,g185han01",
3971 .data = &auo_g185han01,
3972 }, {
3973 .compatible = "auo,g190ean01",
3974 .data = &auo_g190ean01,
3975 }, {
3976 .compatible = "auo,p320hvn03",
3977 .data = &auo_p320hvn03,
3978 }, {
3979 .compatible = "auo,t215hvn01",
3980 .data = &auo_t215hvn01,
3981 }, {
3982 .compatible = "avic,tm070ddh03",
3983 .data = &avic_tm070ddh03,
3984 }, {
3985 .compatible = "bananapi,s070wv20-ct16",
3986 .data = &bananapi_s070wv20_ct16,
3987 }, {
3988 .compatible = "boe,hv070wsa-100",
3989 .data = &boe_hv070wsa
3990 }, {
3991 .compatible = "boe,nv101wxmn51",
3992 .data = &boe_nv101wxmn51,
3993 }, {
3994 .compatible = "boe,nv133fhm-n61",
3995 .data = &boe_nv133fhm_n61,
3996 }, {
3997 .compatible = "boe,nv133fhm-n62",
3998 .data = &boe_nv133fhm_n61,
3999 }, {
4000 .compatible = "boe,nv140fhmn49",
4001 .data = &boe_nv140fhmn49,
4002 }, {
4003 .compatible = "cdtech,s043wq26h-ct7",
4004 .data = &cdtech_s043wq26h_ct7,
4005 }, {
4006 .compatible = "cdtech,s070pws19hp-fc21",
4007 .data = &cdtech_s070pws19hp_fc21,
4008 }, {
4009 .compatible = "cdtech,s070swv29hg-dc44",
4010 .data = &cdtech_s070swv29hg_dc44,
4011 }, {
4012 .compatible = "cdtech,s070wv95-ct16",
4013 .data = &cdtech_s070wv95_ct16,
4014 }, {
4015 .compatible = "chefree,ch101olhlwh-002",
4016 .data = &chefree_ch101olhlwh_002,
4017 }, {
4018 .compatible = "chunghwa,claa070wp03xg",
4019 .data = &chunghwa_claa070wp03xg,
4020 }, {
4021 .compatible = "chunghwa,claa101wa01a",
4022 .data = &chunghwa_claa101wa01a
4023 }, {
4024 .compatible = "chunghwa,claa101wb01",
4025 .data = &chunghwa_claa101wb01
4026 }, {
4027 .compatible = "dataimage,scf0700c48ggu18",
4028 .data = &dataimage_scf0700c48ggu18,
4029 }, {
4030 .compatible = "dlc,dlc0700yzg-1",
4031 .data = &dlc_dlc0700yzg_1,
4032 }, {
4033 .compatible = "dlc,dlc1010gig",
4034 .data = &dlc_dlc1010gig,
4035 }, {
4036 .compatible = "edt,et035012dm6",
4037 .data = &edt_et035012dm6,
4038 }, {
4039 .compatible = "edt,etm043080dh6gp",
4040 .data = &edt_etm043080dh6gp,
4041 }, {
4042 .compatible = "edt,etm0430g0dh6",
4043 .data = &edt_etm0430g0dh6,
4044 }, {
4045 .compatible = "edt,et057090dhu",
4046 .data = &edt_et057090dhu,
4047 }, {
4048 .compatible = "edt,et070080dh6",
4049 .data = &edt_etm0700g0dh6,
4050 }, {
4051 .compatible = "edt,etm0700g0dh6",
4052 .data = &edt_etm0700g0dh6,
4053 }, {
4054 .compatible = "edt,etm0700g0bdh6",
4055 .data = &edt_etm0700g0bdh6,
4056 }, {
4057 .compatible = "edt,etm0700g0edh6",
4058 .data = &edt_etm0700g0bdh6,
4059 }, {
4060 .compatible = "evervision,vgg804821",
4061 .data = &evervision_vgg804821,
4062 }, {
4063 .compatible = "foxlink,fl500wvr00-a0t",
4064 .data = &foxlink_fl500wvr00_a0t,
4065 }, {
4066 .compatible = "frida,frd350h54004",
4067 .data = &frida_frd350h54004,
4068 }, {
4069 .compatible = "friendlyarm,hd702e",
4070 .data = &friendlyarm_hd702e,
4071 }, {
4072 .compatible = "giantplus,gpg482739qs5",
4073 .data = &giantplus_gpg482739qs5
4074 }, {
4075 .compatible = "giantplus,gpm940b0",
4076 .data = &giantplus_gpm940b0,
4077 }, {
4078 .compatible = "hannstar,hsd070pww1",
4079 .data = &hannstar_hsd070pww1,
4080 }, {
4081 .compatible = "hannstar,hsd100pxn1",
4082 .data = &hannstar_hsd100pxn1,
4083 }, {
4084 .compatible = "hit,tx23d38vm0caa",
4085 .data = &hitachi_tx23d38vm0caa
4086 }, {
4087 .compatible = "innolux,at043tn24",
4088 .data = &innolux_at043tn24,
4089 }, {
4090 .compatible = "innolux,at070tn92",
4091 .data = &innolux_at070tn92,
4092 }, {
4093 .compatible = "innolux,g070y2-l01",
4094 .data = &innolux_g070y2_l01,
4095 }, {
4096 .compatible = "innolux,g101ice-l01",
4097 .data = &innolux_g101ice_l01
4098 }, {
4099 .compatible = "innolux,g121i1-l01",
4100 .data = &innolux_g121i1_l01
4101 }, {
4102 .compatible = "innolux,g121x1-l03",
4103 .data = &innolux_g121x1_l03,
4104 }, {
4105 .compatible = "innolux,n116bge",
4106 .data = &innolux_n116bge,
4107 }, {
4108 .compatible = "innolux,n156bge-l21",
4109 .data = &innolux_n156bge_l21,
4110 }, {
4111 .compatible = "innolux,p120zdg-bf1",
4112 .data = &innolux_p120zdg_bf1,
4113 }, {
4114 .compatible = "innolux,zj070na-01p",
4115 .data = &innolux_zj070na_01p,
4116 }, {
4117 .compatible = "ivo,m133nwf4-r0",
4118 .data = &ivo_m133nwf4_r0,
4119 }, {
4120 .compatible = "kingdisplay,kd116n21-30nv-a010",
4121 .data = &kingdisplay_kd116n21_30nv_a010,
4122 }, {
4123 .compatible = "koe,tx14d24vm1bpa",
4124 .data = &koe_tx14d24vm1bpa,
4125 }, {
4126 .compatible = "koe,tx26d202vm0bwa",
4127 .data = &koe_tx26d202vm0bwa,
4128 }, {
4129 .compatible = "koe,tx31d200vm0baa",
4130 .data = &koe_tx31d200vm0baa,
4131 }, {
4132 .compatible = "kyo,tcg121xglp",
4133 .data = &kyo_tcg121xglp,
4134 }, {
4135 .compatible = "lemaker,bl035-rgb-002",
4136 .data = &lemaker_bl035_rgb_002,
4137 }, {
4138 .compatible = "lg,lb070wv8",
4139 .data = &lg_lb070wv8,
4140 }, {
4141 .compatible = "lg,lp079qx1-sp0v",
4142 .data = &lg_lp079qx1_sp0v,
4143 }, {
4144 .compatible = "lg,lp097qx1-spa1",
4145 .data = &lg_lp097qx1_spa1,
4146 }, {
4147 .compatible = "lg,lp120up1",
4148 .data = &lg_lp120up1,
4149 }, {
4150 .compatible = "lg,lp129qe",
4151 .data = &lg_lp129qe,
4152 }, {
4153 .compatible = "logicpd,type28",
4154 .data = &logicpd_type_28,
4155 }, {
4156 .compatible = "logictechno,lt161010-2nhc",
4157 .data = &logictechno_lt161010_2nh,
4158 }, {
4159 .compatible = "logictechno,lt161010-2nhr",
4160 .data = &logictechno_lt161010_2nh,
4161 }, {
4162 .compatible = "logictechno,lt170410-2whc",
4163 .data = &logictechno_lt170410_2whc,
4164 }, {
4165 .compatible = "mitsubishi,aa070mc01-ca1",
4166 .data = &mitsubishi_aa070mc01,
4167 }, {
4168 .compatible = "nec,nl12880bc20-05",
4169 .data = &nec_nl12880bc20_05,
4170 }, {
4171 .compatible = "nec,nl4827hc19-05b",
4172 .data = &nec_nl4827hc19_05b,
4173 }, {
4174 .compatible = "netron-dy,e231732",
4175 .data = &netron_dy_e231732,
4176 }, {
4177 .compatible = "neweast,wjfh116008a",
4178 .data = &neweast_wjfh116008a,
4179 }, {
4180 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4181 .data = &newhaven_nhd_43_480272ef_atxl,
4182 }, {
4183 .compatible = "nlt,nl192108ac18-02d",
4184 .data = &nlt_nl192108ac18_02d,
4185 }, {
4186 .compatible = "nvd,9128",
4187 .data = &nvd_9128,
4188 }, {
4189 .compatible = "okaya,rs800480t-7x0gp",
4190 .data = &okaya_rs800480t_7x0gp,
4191 }, {
4192 .compatible = "olimex,lcd-olinuxino-43-ts",
4193 .data = &olimex_lcd_olinuxino_43ts,
4194 }, {
4195 .compatible = "ontat,yx700wv03",
4196 .data = &ontat_yx700wv03,
4197 }, {
4198 .compatible = "ortustech,com37h3m05dtc",
4199 .data = &ortustech_com37h3m,
4200 }, {
4201 .compatible = "ortustech,com37h3m99dtc",
4202 .data = &ortustech_com37h3m,
4203 }, {
4204 .compatible = "ortustech,com43h4m85ulc",
4205 .data = &ortustech_com43h4m85ulc,
4206 }, {
4207 .compatible = "osddisplays,osd070t1718-19ts",
4208 .data = &osddisplays_osd070t1718_19ts,
4209 }, {
4210 .compatible = "pda,91-00156-a0",
4211 .data = &pda_91_00156_a0,
4212 }, {
4213 .compatible = "powertip,ph800480t013-idf02",
4214 .data = &powertip_ph800480t013_idf02,
4215 }, {
4216 .compatible = "qiaodian,qd43003c0-40",
4217 .data = &qd43003c0_40,
4218 }, {
4219 .compatible = "rocktech,rk070er9427",
4220 .data = &rocktech_rk070er9427,
4221 }, {
4222 .compatible = "rocktech,rk101ii01d-ct",
4223 .data = &rocktech_rk101ii01d_ct,
4224 }, {
4225 .compatible = "samsung,lsn122dl01-c01",
4226 .data = &samsung_lsn122dl01_c01,
4227 }, {
4228 .compatible = "samsung,ltn101nt05",
4229 .data = &samsung_ltn101nt05,
4230 }, {
4231 .compatible = "samsung,ltn140at29-301",
4232 .data = &samsung_ltn140at29_301,
4233 }, {
4234 .compatible = "satoz,sat050at40h12r2",
4235 .data = &satoz_sat050at40h12r2,
4236 }, {
4237 .compatible = "sharp,ld-d5116z01b",
4238 .data = &sharp_ld_d5116z01b,
4239 }, {
4240 .compatible = "sharp,lq035q7db03",
4241 .data = &sharp_lq035q7db03,
4242 }, {
4243 .compatible = "sharp,lq070y3dg3b",
4244 .data = &sharp_lq070y3dg3b,
4245 }, {
4246 .compatible = "sharp,lq101k1ly04",
4247 .data = &sharp_lq101k1ly04,
4248 }, {
4249 .compatible = "sharp,lq123p1jx31",
4250 .data = &sharp_lq123p1jx31,
4251 }, {
4252 .compatible = "sharp,ls020b1dd01d",
4253 .data = &sharp_ls020b1dd01d,
4254 }, {
4255 .compatible = "shelly,sca07010-bfn-lnn",
4256 .data = &shelly_sca07010_bfn_lnn,
4257 }, {
4258 .compatible = "starry,kr070pe2t",
4259 .data = &starry_kr070pe2t,
4260 }, {
4261 .compatible = "starry,kr122ea0sra",
4262 .data = &starry_kr122ea0sra,
4263 }, {
4264 .compatible = "tfc,s9700rtwv43tr-01b",
4265 .data = &tfc_s9700rtwv43tr_01b,
4266 }, {
4267 .compatible = "tianma,tm070jdhg30",
4268 .data = &tianma_tm070jdhg30,
4269 }, {
4270 .compatible = "tianma,tm070jvhg33",
4271 .data = &tianma_tm070jvhg33,
4272 }, {
4273 .compatible = "tianma,tm070rvhg71",
4274 .data = &tianma_tm070rvhg71,
4275 }, {
4276 .compatible = "ti,nspire-cx-lcd-panel",
4277 .data = &ti_nspire_cx_lcd_panel,
4278 }, {
4279 .compatible = "ti,nspire-classic-lcd-panel",
4280 .data = &ti_nspire_classic_lcd_panel,
4281 }, {
4282 .compatible = "toshiba,lt089ac29000",
4283 .data = &toshiba_lt089ac29000,
4284 }, {
4285 .compatible = "tpk,f07a-0102",
4286 .data = &tpk_f07a_0102,
4287 }, {
4288 .compatible = "tpk,f10a-0102",
4289 .data = &tpk_f10a_0102,
4290 }, {
4291 .compatible = "urt,umsh-8596md-t",
4292 .data = &urt_umsh_8596md_parallel,
4293 }, {
4294 .compatible = "urt,umsh-8596md-1t",
4295 .data = &urt_umsh_8596md_parallel,
4296 }, {
4297 .compatible = "urt,umsh-8596md-7t",
4298 .data = &urt_umsh_8596md_parallel,
4299 }, {
4300 .compatible = "urt,umsh-8596md-11t",
4301 .data = &urt_umsh_8596md_lvds,
4302 }, {
4303 .compatible = "urt,umsh-8596md-19t",
4304 .data = &urt_umsh_8596md_lvds,
4305 }, {
4306 .compatible = "urt,umsh-8596md-20t",
4307 .data = &urt_umsh_8596md_parallel,
4308 }, {
4309 .compatible = "vxt,vl050-8048nt-c01",
4310 .data = &vl050_8048nt_c01,
4311 }, {
4312 .compatible = "winstar,wf35ltiacd",
4313 .data = &winstar_wf35ltiacd,
4314 }, {
4315 /* Must be the last entry */
4316 .compatible = "panel-dpi",
4317 .data = &panel_dpi,
4318 }, {
4319 /* sentinel */
4320 }
4321 };
4322 MODULE_DEVICE_TABLE(of, platform_of_match);
4323
panel_simple_platform_probe(struct platform_device * pdev)4324 static int panel_simple_platform_probe(struct platform_device *pdev)
4325 {
4326 const struct of_device_id *id;
4327
4328 id = of_match_node(platform_of_match, pdev->dev.of_node);
4329 if (!id)
4330 return -ENODEV;
4331
4332 return panel_simple_probe(&pdev->dev, id->data);
4333 }
4334
panel_simple_platform_remove(struct platform_device * pdev)4335 static int panel_simple_platform_remove(struct platform_device *pdev)
4336 {
4337 return panel_simple_remove(&pdev->dev);
4338 }
4339
panel_simple_platform_shutdown(struct platform_device * pdev)4340 static void panel_simple_platform_shutdown(struct platform_device *pdev)
4341 {
4342 panel_simple_shutdown(&pdev->dev);
4343 }
4344
4345 static struct platform_driver panel_simple_platform_driver = {
4346 .driver = {
4347 .name = "panel-simple",
4348 .of_match_table = platform_of_match,
4349 },
4350 .probe = panel_simple_platform_probe,
4351 .remove = panel_simple_platform_remove,
4352 .shutdown = panel_simple_platform_shutdown,
4353 };
4354
4355 struct panel_desc_dsi {
4356 struct panel_desc desc;
4357
4358 unsigned long flags;
4359 enum mipi_dsi_pixel_format format;
4360 unsigned int lanes;
4361 };
4362
4363 static const struct drm_display_mode auo_b080uan01_mode = {
4364 .clock = 154500,
4365 .hdisplay = 1200,
4366 .hsync_start = 1200 + 62,
4367 .hsync_end = 1200 + 62 + 4,
4368 .htotal = 1200 + 62 + 4 + 62,
4369 .vdisplay = 1920,
4370 .vsync_start = 1920 + 9,
4371 .vsync_end = 1920 + 9 + 2,
4372 .vtotal = 1920 + 9 + 2 + 8,
4373 };
4374
4375 static const struct panel_desc_dsi auo_b080uan01 = {
4376 .desc = {
4377 .modes = &auo_b080uan01_mode,
4378 .num_modes = 1,
4379 .bpc = 8,
4380 .size = {
4381 .width = 108,
4382 .height = 272,
4383 },
4384 .connector_type = DRM_MODE_CONNECTOR_DSI,
4385 },
4386 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4387 .format = MIPI_DSI_FMT_RGB888,
4388 .lanes = 4,
4389 };
4390
4391 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4392 .clock = 160000,
4393 .hdisplay = 1200,
4394 .hsync_start = 1200 + 120,
4395 .hsync_end = 1200 + 120 + 20,
4396 .htotal = 1200 + 120 + 20 + 21,
4397 .vdisplay = 1920,
4398 .vsync_start = 1920 + 21,
4399 .vsync_end = 1920 + 21 + 3,
4400 .vtotal = 1920 + 21 + 3 + 18,
4401 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4402 };
4403
4404 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4405 .desc = {
4406 .modes = &boe_tv080wum_nl0_mode,
4407 .num_modes = 1,
4408 .size = {
4409 .width = 107,
4410 .height = 172,
4411 },
4412 .connector_type = DRM_MODE_CONNECTOR_DSI,
4413 },
4414 .flags = MIPI_DSI_MODE_VIDEO |
4415 MIPI_DSI_MODE_VIDEO_BURST |
4416 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4417 .format = MIPI_DSI_FMT_RGB888,
4418 .lanes = 4,
4419 };
4420
4421 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4422 .clock = 71000,
4423 .hdisplay = 800,
4424 .hsync_start = 800 + 32,
4425 .hsync_end = 800 + 32 + 1,
4426 .htotal = 800 + 32 + 1 + 57,
4427 .vdisplay = 1280,
4428 .vsync_start = 1280 + 28,
4429 .vsync_end = 1280 + 28 + 1,
4430 .vtotal = 1280 + 28 + 1 + 14,
4431 };
4432
4433 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4434 .desc = {
4435 .modes = &lg_ld070wx3_sl01_mode,
4436 .num_modes = 1,
4437 .bpc = 8,
4438 .size = {
4439 .width = 94,
4440 .height = 151,
4441 },
4442 .connector_type = DRM_MODE_CONNECTOR_DSI,
4443 },
4444 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4445 .format = MIPI_DSI_FMT_RGB888,
4446 .lanes = 4,
4447 };
4448
4449 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4450 .clock = 67000,
4451 .hdisplay = 720,
4452 .hsync_start = 720 + 12,
4453 .hsync_end = 720 + 12 + 4,
4454 .htotal = 720 + 12 + 4 + 112,
4455 .vdisplay = 1280,
4456 .vsync_start = 1280 + 8,
4457 .vsync_end = 1280 + 8 + 4,
4458 .vtotal = 1280 + 8 + 4 + 12,
4459 };
4460
4461 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4462 .desc = {
4463 .modes = &lg_lh500wx1_sd03_mode,
4464 .num_modes = 1,
4465 .bpc = 8,
4466 .size = {
4467 .width = 62,
4468 .height = 110,
4469 },
4470 .connector_type = DRM_MODE_CONNECTOR_DSI,
4471 },
4472 .flags = MIPI_DSI_MODE_VIDEO,
4473 .format = MIPI_DSI_FMT_RGB888,
4474 .lanes = 4,
4475 };
4476
4477 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4478 .clock = 157200,
4479 .hdisplay = 1920,
4480 .hsync_start = 1920 + 154,
4481 .hsync_end = 1920 + 154 + 16,
4482 .htotal = 1920 + 154 + 16 + 32,
4483 .vdisplay = 1200,
4484 .vsync_start = 1200 + 17,
4485 .vsync_end = 1200 + 17 + 2,
4486 .vtotal = 1200 + 17 + 2 + 16,
4487 };
4488
4489 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4490 .desc = {
4491 .modes = &panasonic_vvx10f004b00_mode,
4492 .num_modes = 1,
4493 .bpc = 8,
4494 .size = {
4495 .width = 217,
4496 .height = 136,
4497 },
4498 .connector_type = DRM_MODE_CONNECTOR_DSI,
4499 },
4500 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4501 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4502 .format = MIPI_DSI_FMT_RGB888,
4503 .lanes = 4,
4504 };
4505
4506 static const struct drm_display_mode lg_acx467akm_7_mode = {
4507 .clock = 150000,
4508 .hdisplay = 1080,
4509 .hsync_start = 1080 + 2,
4510 .hsync_end = 1080 + 2 + 2,
4511 .htotal = 1080 + 2 + 2 + 2,
4512 .vdisplay = 1920,
4513 .vsync_start = 1920 + 2,
4514 .vsync_end = 1920 + 2 + 2,
4515 .vtotal = 1920 + 2 + 2 + 2,
4516 };
4517
4518 static const struct panel_desc_dsi lg_acx467akm_7 = {
4519 .desc = {
4520 .modes = &lg_acx467akm_7_mode,
4521 .num_modes = 1,
4522 .bpc = 8,
4523 .size = {
4524 .width = 62,
4525 .height = 110,
4526 },
4527 .connector_type = DRM_MODE_CONNECTOR_DSI,
4528 },
4529 .flags = 0,
4530 .format = MIPI_DSI_FMT_RGB888,
4531 .lanes = 4,
4532 };
4533
4534 static const struct drm_display_mode osd101t2045_53ts_mode = {
4535 .clock = 154500,
4536 .hdisplay = 1920,
4537 .hsync_start = 1920 + 112,
4538 .hsync_end = 1920 + 112 + 16,
4539 .htotal = 1920 + 112 + 16 + 32,
4540 .vdisplay = 1200,
4541 .vsync_start = 1200 + 16,
4542 .vsync_end = 1200 + 16 + 2,
4543 .vtotal = 1200 + 16 + 2 + 16,
4544 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4545 };
4546
4547 static const struct panel_desc_dsi osd101t2045_53ts = {
4548 .desc = {
4549 .modes = &osd101t2045_53ts_mode,
4550 .num_modes = 1,
4551 .bpc = 8,
4552 .size = {
4553 .width = 217,
4554 .height = 136,
4555 },
4556 .connector_type = DRM_MODE_CONNECTOR_DSI,
4557 },
4558 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4559 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4560 MIPI_DSI_MODE_EOT_PACKET,
4561 .format = MIPI_DSI_FMT_RGB888,
4562 .lanes = 4,
4563 };
4564
4565 static const struct of_device_id dsi_of_match[] = {
4566 {
4567 .compatible = "auo,b080uan01",
4568 .data = &auo_b080uan01
4569 }, {
4570 .compatible = "boe,tv080wum-nl0",
4571 .data = &boe_tv080wum_nl0
4572 }, {
4573 .compatible = "lg,ld070wx3-sl01",
4574 .data = &lg_ld070wx3_sl01
4575 }, {
4576 .compatible = "lg,lh500wx1-sd03",
4577 .data = &lg_lh500wx1_sd03
4578 }, {
4579 .compatible = "panasonic,vvx10f004b00",
4580 .data = &panasonic_vvx10f004b00
4581 }, {
4582 .compatible = "lg,acx467akm-7",
4583 .data = &lg_acx467akm_7
4584 }, {
4585 .compatible = "osddisplays,osd101t2045-53ts",
4586 .data = &osd101t2045_53ts
4587 }, {
4588 /* sentinel */
4589 }
4590 };
4591 MODULE_DEVICE_TABLE(of, dsi_of_match);
4592
panel_simple_dsi_probe(struct mipi_dsi_device * dsi)4593 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4594 {
4595 const struct panel_desc_dsi *desc;
4596 const struct of_device_id *id;
4597 int err;
4598
4599 id = of_match_node(dsi_of_match, dsi->dev.of_node);
4600 if (!id)
4601 return -ENODEV;
4602
4603 desc = id->data;
4604
4605 err = panel_simple_probe(&dsi->dev, &desc->desc);
4606 if (err < 0)
4607 return err;
4608
4609 dsi->mode_flags = desc->flags;
4610 dsi->format = desc->format;
4611 dsi->lanes = desc->lanes;
4612
4613 err = mipi_dsi_attach(dsi);
4614 if (err) {
4615 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
4616
4617 drm_panel_remove(&panel->base);
4618 }
4619
4620 return err;
4621 }
4622
panel_simple_dsi_remove(struct mipi_dsi_device * dsi)4623 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4624 {
4625 int err;
4626
4627 err = mipi_dsi_detach(dsi);
4628 if (err < 0)
4629 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4630
4631 return panel_simple_remove(&dsi->dev);
4632 }
4633
panel_simple_dsi_shutdown(struct mipi_dsi_device * dsi)4634 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4635 {
4636 panel_simple_shutdown(&dsi->dev);
4637 }
4638
4639 static struct mipi_dsi_driver panel_simple_dsi_driver = {
4640 .driver = {
4641 .name = "panel-simple-dsi",
4642 .of_match_table = dsi_of_match,
4643 },
4644 .probe = panel_simple_dsi_probe,
4645 .remove = panel_simple_dsi_remove,
4646 .shutdown = panel_simple_dsi_shutdown,
4647 };
4648
panel_simple_init(void)4649 static int __init panel_simple_init(void)
4650 {
4651 int err;
4652
4653 err = platform_driver_register(&panel_simple_platform_driver);
4654 if (err < 0)
4655 return err;
4656
4657 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4658 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
4659 if (err < 0)
4660 return err;
4661 }
4662
4663 return 0;
4664 }
4665 module_init(panel_simple_init);
4666
panel_simple_exit(void)4667 static void __exit panel_simple_exit(void)
4668 {
4669 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4670 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4671
4672 platform_driver_unregister(&panel_simple_platform_driver);
4673 }
4674 module_exit(panel_simple_exit);
4675
4676 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4677 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4678 MODULE_LICENSE("GPL and additional rights");
4679