1 /*
2 * Copyright (c) 2016 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/platform_device.h>
34 #include <linux/acpi.h>
35 #include <linux/etherdevice.h>
36 #include <linux/interrupt.h>
37 #include <linux/of.h>
38 #include <linux/of_platform.h>
39 #include <rdma/ib_umem.h>
40 #include "hns_roce_common.h"
41 #include "hns_roce_device.h"
42 #include "hns_roce_cmd.h"
43 #include "hns_roce_hem.h"
44 #include "hns_roce_hw_v1.h"
45
set_data_seg(struct hns_roce_wqe_data_seg * dseg,struct ib_sge * sg)46 static void set_data_seg(struct hns_roce_wqe_data_seg *dseg, struct ib_sge *sg)
47 {
48 dseg->lkey = cpu_to_le32(sg->lkey);
49 dseg->addr = cpu_to_le64(sg->addr);
50 dseg->len = cpu_to_le32(sg->length);
51 }
52
set_raddr_seg(struct hns_roce_wqe_raddr_seg * rseg,u64 remote_addr,u32 rkey)53 static void set_raddr_seg(struct hns_roce_wqe_raddr_seg *rseg, u64 remote_addr,
54 u32 rkey)
55 {
56 rseg->raddr = cpu_to_le64(remote_addr);
57 rseg->rkey = cpu_to_le32(rkey);
58 rseg->len = 0;
59 }
60
hns_roce_v1_post_send(struct ib_qp * ibqp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr)61 static int hns_roce_v1_post_send(struct ib_qp *ibqp,
62 const struct ib_send_wr *wr,
63 const struct ib_send_wr **bad_wr)
64 {
65 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
66 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
67 struct hns_roce_ud_send_wqe *ud_sq_wqe = NULL;
68 struct hns_roce_wqe_ctrl_seg *ctrl = NULL;
69 struct hns_roce_wqe_data_seg *dseg = NULL;
70 struct hns_roce_qp *qp = to_hr_qp(ibqp);
71 struct device *dev = &hr_dev->pdev->dev;
72 struct hns_roce_sq_db sq_db = {};
73 int ps_opcode, i;
74 unsigned long flags = 0;
75 void *wqe = NULL;
76 __le32 doorbell[2];
77 int ret = 0;
78 int loopback;
79 u32 wqe_idx;
80 int nreq;
81 u8 *smac;
82
83 if (unlikely(ibqp->qp_type != IB_QPT_GSI &&
84 ibqp->qp_type != IB_QPT_RC)) {
85 dev_err(dev, "un-supported QP type\n");
86 *bad_wr = NULL;
87 return -EOPNOTSUPP;
88 }
89
90 spin_lock_irqsave(&qp->sq.lock, flags);
91
92 for (nreq = 0; wr; ++nreq, wr = wr->next) {
93 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
94 ret = -ENOMEM;
95 *bad_wr = wr;
96 goto out;
97 }
98
99 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1);
100
101 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
102 dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
103 wr->num_sge, qp->sq.max_gs);
104 ret = -EINVAL;
105 *bad_wr = wr;
106 goto out;
107 }
108
109 wqe = hns_roce_get_send_wqe(qp, wqe_idx);
110 qp->sq.wrid[wqe_idx] = wr->wr_id;
111
112 /* Corresponding to the RC and RD type wqe process separately */
113 if (ibqp->qp_type == IB_QPT_GSI) {
114 ud_sq_wqe = wqe;
115 roce_set_field(ud_sq_wqe->dmac_h,
116 UD_SEND_WQE_U32_4_DMAC_0_M,
117 UD_SEND_WQE_U32_4_DMAC_0_S,
118 ah->av.mac[0]);
119 roce_set_field(ud_sq_wqe->dmac_h,
120 UD_SEND_WQE_U32_4_DMAC_1_M,
121 UD_SEND_WQE_U32_4_DMAC_1_S,
122 ah->av.mac[1]);
123 roce_set_field(ud_sq_wqe->dmac_h,
124 UD_SEND_WQE_U32_4_DMAC_2_M,
125 UD_SEND_WQE_U32_4_DMAC_2_S,
126 ah->av.mac[2]);
127 roce_set_field(ud_sq_wqe->dmac_h,
128 UD_SEND_WQE_U32_4_DMAC_3_M,
129 UD_SEND_WQE_U32_4_DMAC_3_S,
130 ah->av.mac[3]);
131
132 roce_set_field(ud_sq_wqe->u32_8,
133 UD_SEND_WQE_U32_8_DMAC_4_M,
134 UD_SEND_WQE_U32_8_DMAC_4_S,
135 ah->av.mac[4]);
136 roce_set_field(ud_sq_wqe->u32_8,
137 UD_SEND_WQE_U32_8_DMAC_5_M,
138 UD_SEND_WQE_U32_8_DMAC_5_S,
139 ah->av.mac[5]);
140
141 smac = (u8 *)hr_dev->dev_addr[qp->port];
142 loopback = ether_addr_equal_unaligned(ah->av.mac,
143 smac) ? 1 : 0;
144 roce_set_bit(ud_sq_wqe->u32_8,
145 UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S,
146 loopback);
147
148 roce_set_field(ud_sq_wqe->u32_8,
149 UD_SEND_WQE_U32_8_OPERATION_TYPE_M,
150 UD_SEND_WQE_U32_8_OPERATION_TYPE_S,
151 HNS_ROCE_WQE_OPCODE_SEND);
152 roce_set_field(ud_sq_wqe->u32_8,
153 UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M,
154 UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S,
155 2);
156 roce_set_bit(ud_sq_wqe->u32_8,
157 UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S,
158 1);
159
160 ud_sq_wqe->u32_8 |= (wr->send_flags & IB_SEND_SIGNALED ?
161 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
162 (wr->send_flags & IB_SEND_SOLICITED ?
163 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
164 ((wr->opcode == IB_WR_SEND_WITH_IMM) ?
165 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0);
166
167 roce_set_field(ud_sq_wqe->u32_16,
168 UD_SEND_WQE_U32_16_DEST_QP_M,
169 UD_SEND_WQE_U32_16_DEST_QP_S,
170 ud_wr(wr)->remote_qpn);
171 roce_set_field(ud_sq_wqe->u32_16,
172 UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M,
173 UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S,
174 ah->av.stat_rate);
175
176 roce_set_field(ud_sq_wqe->u32_36,
177 UD_SEND_WQE_U32_36_FLOW_LABEL_M,
178 UD_SEND_WQE_U32_36_FLOW_LABEL_S,
179 ah->av.flowlabel);
180 roce_set_field(ud_sq_wqe->u32_36,
181 UD_SEND_WQE_U32_36_PRIORITY_M,
182 UD_SEND_WQE_U32_36_PRIORITY_S,
183 ah->av.sl);
184 roce_set_field(ud_sq_wqe->u32_36,
185 UD_SEND_WQE_U32_36_SGID_INDEX_M,
186 UD_SEND_WQE_U32_36_SGID_INDEX_S,
187 hns_get_gid_index(hr_dev, qp->phy_port,
188 ah->av.gid_index));
189
190 roce_set_field(ud_sq_wqe->u32_40,
191 UD_SEND_WQE_U32_40_HOP_LIMIT_M,
192 UD_SEND_WQE_U32_40_HOP_LIMIT_S,
193 ah->av.hop_limit);
194 roce_set_field(ud_sq_wqe->u32_40,
195 UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M,
196 UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S,
197 ah->av.tclass);
198
199 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN);
200
201 ud_sq_wqe->va0_l =
202 cpu_to_le32((u32)wr->sg_list[0].addr);
203 ud_sq_wqe->va0_h =
204 cpu_to_le32((wr->sg_list[0].addr) >> 32);
205 ud_sq_wqe->l_key0 =
206 cpu_to_le32(wr->sg_list[0].lkey);
207
208 ud_sq_wqe->va1_l =
209 cpu_to_le32((u32)wr->sg_list[1].addr);
210 ud_sq_wqe->va1_h =
211 cpu_to_le32((wr->sg_list[1].addr) >> 32);
212 ud_sq_wqe->l_key1 =
213 cpu_to_le32(wr->sg_list[1].lkey);
214 } else if (ibqp->qp_type == IB_QPT_RC) {
215 u32 tmp_len = 0;
216
217 ctrl = wqe;
218 memset(ctrl, 0, sizeof(struct hns_roce_wqe_ctrl_seg));
219 for (i = 0; i < wr->num_sge; i++)
220 tmp_len += wr->sg_list[i].length;
221
222 ctrl->msg_length =
223 cpu_to_le32(le32_to_cpu(ctrl->msg_length) + tmp_len);
224
225 ctrl->sgl_pa_h = 0;
226 ctrl->flag = 0;
227
228 switch (wr->opcode) {
229 case IB_WR_SEND_WITH_IMM:
230 case IB_WR_RDMA_WRITE_WITH_IMM:
231 ctrl->imm_data = wr->ex.imm_data;
232 break;
233 case IB_WR_SEND_WITH_INV:
234 ctrl->inv_key =
235 cpu_to_le32(wr->ex.invalidate_rkey);
236 break;
237 default:
238 ctrl->imm_data = 0;
239 break;
240 }
241
242 /* Ctrl field, ctrl set type: sig, solic, imm, fence */
243 /* SO wait for conforming application scenarios */
244 ctrl->flag |= (wr->send_flags & IB_SEND_SIGNALED ?
245 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
246 (wr->send_flags & IB_SEND_SOLICITED ?
247 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
248 ((wr->opcode == IB_WR_SEND_WITH_IMM ||
249 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) ?
250 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0) |
251 (wr->send_flags & IB_SEND_FENCE ?
252 (cpu_to_le32(HNS_ROCE_WQE_FENCE)) : 0);
253
254 wqe += sizeof(struct hns_roce_wqe_ctrl_seg);
255
256 switch (wr->opcode) {
257 case IB_WR_RDMA_READ:
258 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_READ;
259 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
260 rdma_wr(wr)->rkey);
261 break;
262 case IB_WR_RDMA_WRITE:
263 case IB_WR_RDMA_WRITE_WITH_IMM:
264 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_WRITE;
265 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
266 rdma_wr(wr)->rkey);
267 break;
268 case IB_WR_SEND:
269 case IB_WR_SEND_WITH_INV:
270 case IB_WR_SEND_WITH_IMM:
271 ps_opcode = HNS_ROCE_WQE_OPCODE_SEND;
272 break;
273 case IB_WR_LOCAL_INV:
274 case IB_WR_ATOMIC_CMP_AND_SWP:
275 case IB_WR_ATOMIC_FETCH_AND_ADD:
276 case IB_WR_LSO:
277 default:
278 ps_opcode = HNS_ROCE_WQE_OPCODE_MASK;
279 break;
280 }
281 ctrl->flag |= cpu_to_le32(ps_opcode);
282 wqe += sizeof(struct hns_roce_wqe_raddr_seg);
283
284 dseg = wqe;
285 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
286 if (le32_to_cpu(ctrl->msg_length) >
287 hr_dev->caps.max_sq_inline) {
288 ret = -EINVAL;
289 *bad_wr = wr;
290 dev_err(dev, "inline len(1-%d)=%d, illegal",
291 ctrl->msg_length,
292 hr_dev->caps.max_sq_inline);
293 goto out;
294 }
295 for (i = 0; i < wr->num_sge; i++) {
296 memcpy(wqe, ((void *) (uintptr_t)
297 wr->sg_list[i].addr),
298 wr->sg_list[i].length);
299 wqe += wr->sg_list[i].length;
300 }
301 ctrl->flag |= cpu_to_le32(HNS_ROCE_WQE_INLINE);
302 } else {
303 /* sqe num is two */
304 for (i = 0; i < wr->num_sge; i++)
305 set_data_seg(dseg + i, wr->sg_list + i);
306
307 ctrl->flag |= cpu_to_le32(wr->num_sge <<
308 HNS_ROCE_WQE_SGE_NUM_BIT);
309 }
310 }
311 }
312
313 out:
314 /* Set DB return */
315 if (likely(nreq)) {
316 qp->sq.head += nreq;
317 /* Memory barrier */
318 wmb();
319
320 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SQ_HEAD_M,
321 SQ_DOORBELL_U32_4_SQ_HEAD_S,
322 (qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)));
323 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SL_M,
324 SQ_DOORBELL_U32_4_SL_S, qp->sl);
325 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_PORT_M,
326 SQ_DOORBELL_U32_4_PORT_S, qp->phy_port);
327 roce_set_field(sq_db.u32_8, SQ_DOORBELL_U32_8_QPN_M,
328 SQ_DOORBELL_U32_8_QPN_S, qp->doorbell_qpn);
329 roce_set_bit(sq_db.u32_8, SQ_DOORBELL_HW_SYNC_S, 1);
330
331 doorbell[0] = sq_db.u32_4;
332 doorbell[1] = sq_db.u32_8;
333
334 hns_roce_write64_k(doorbell, qp->sq.db_reg_l);
335 }
336
337 spin_unlock_irqrestore(&qp->sq.lock, flags);
338
339 return ret;
340 }
341
hns_roce_v1_post_recv(struct ib_qp * ibqp,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)342 static int hns_roce_v1_post_recv(struct ib_qp *ibqp,
343 const struct ib_recv_wr *wr,
344 const struct ib_recv_wr **bad_wr)
345 {
346 struct hns_roce_rq_wqe_ctrl *ctrl = NULL;
347 struct hns_roce_wqe_data_seg *scat = NULL;
348 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
349 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
350 struct device *dev = &hr_dev->pdev->dev;
351 struct hns_roce_rq_db rq_db = {};
352 __le32 doorbell[2] = {0};
353 unsigned long flags = 0;
354 unsigned int wqe_idx;
355 int ret = 0;
356 int nreq = 0;
357 int i = 0;
358 u32 reg_val;
359
360 spin_lock_irqsave(&hr_qp->rq.lock, flags);
361
362 for (nreq = 0; wr; ++nreq, wr = wr->next) {
363 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
364 hr_qp->ibqp.recv_cq)) {
365 ret = -ENOMEM;
366 *bad_wr = wr;
367 goto out;
368 }
369
370 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
371
372 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
373 dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
374 wr->num_sge, hr_qp->rq.max_gs);
375 ret = -EINVAL;
376 *bad_wr = wr;
377 goto out;
378 }
379
380 ctrl = hns_roce_get_recv_wqe(hr_qp, wqe_idx);
381
382 roce_set_field(ctrl->rwqe_byte_12,
383 RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M,
384 RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S,
385 wr->num_sge);
386
387 scat = (struct hns_roce_wqe_data_seg *)(ctrl + 1);
388
389 for (i = 0; i < wr->num_sge; i++)
390 set_data_seg(scat + i, wr->sg_list + i);
391
392 hr_qp->rq.wrid[wqe_idx] = wr->wr_id;
393 }
394
395 out:
396 if (likely(nreq)) {
397 hr_qp->rq.head += nreq;
398 /* Memory barrier */
399 wmb();
400
401 if (ibqp->qp_type == IB_QPT_GSI) {
402 __le32 tmp;
403
404 /* SW update GSI rq header */
405 reg_val = roce_read(to_hr_dev(ibqp->device),
406 ROCEE_QP1C_CFG3_0_REG +
407 QP1C_CFGN_OFFSET * hr_qp->phy_port);
408 tmp = cpu_to_le32(reg_val);
409 roce_set_field(tmp,
410 ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M,
411 ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S,
412 hr_qp->rq.head);
413 reg_val = le32_to_cpu(tmp);
414 roce_write(to_hr_dev(ibqp->device),
415 ROCEE_QP1C_CFG3_0_REG +
416 QP1C_CFGN_OFFSET * hr_qp->phy_port, reg_val);
417 } else {
418 roce_set_field(rq_db.u32_4, RQ_DOORBELL_U32_4_RQ_HEAD_M,
419 RQ_DOORBELL_U32_4_RQ_HEAD_S,
420 hr_qp->rq.head);
421 roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_QPN_M,
422 RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
423 roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_CMD_M,
424 RQ_DOORBELL_U32_8_CMD_S, 1);
425 roce_set_bit(rq_db.u32_8, RQ_DOORBELL_U32_8_HW_SYNC_S,
426 1);
427
428 doorbell[0] = rq_db.u32_4;
429 doorbell[1] = rq_db.u32_8;
430
431 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
432 }
433 }
434 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
435
436 return ret;
437 }
438
hns_roce_set_db_event_mode(struct hns_roce_dev * hr_dev,int sdb_mode,int odb_mode)439 static void hns_roce_set_db_event_mode(struct hns_roce_dev *hr_dev,
440 int sdb_mode, int odb_mode)
441 {
442 __le32 tmp;
443 u32 val;
444
445 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
446 tmp = cpu_to_le32(val);
447 roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S, sdb_mode);
448 roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode);
449 val = le32_to_cpu(tmp);
450 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
451 }
452
hns_roce_v1_set_hem(struct hns_roce_dev * hr_dev,struct hns_roce_hem_table * table,int obj,int step_idx)453 static int hns_roce_v1_set_hem(struct hns_roce_dev *hr_dev,
454 struct hns_roce_hem_table *table, int obj,
455 int step_idx)
456 {
457 spinlock_t *lock = &hr_dev->bt_cmd_lock;
458 struct device *dev = hr_dev->dev;
459 struct hns_roce_hem_iter iter;
460 void __iomem *bt_cmd;
461 __le32 bt_cmd_val[2];
462 __le32 bt_cmd_h = 0;
463 unsigned long flags;
464 __le32 bt_cmd_l;
465 int ret = 0;
466 u64 bt_ba;
467 long end;
468
469 /* Find the HEM(Hardware Entry Memory) entry */
470 unsigned long i = (obj & (table->num_obj - 1)) /
471 (table->table_chunk_size / table->obj_size);
472
473 switch (table->type) {
474 case HEM_TYPE_QPC:
475 case HEM_TYPE_MTPT:
476 case HEM_TYPE_CQC:
477 case HEM_TYPE_SRQC:
478 roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
479 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, table->type);
480 break;
481 default:
482 return ret;
483 }
484
485 roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
486 ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
487 roce_set_bit(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
488 roce_set_bit(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
489
490 /* Currently iter only a chunk */
491 for (hns_roce_hem_first(table->hem[i], &iter);
492 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
493 bt_ba = hns_roce_hem_addr(&iter) >> HNS_HW_PAGE_SHIFT;
494
495 spin_lock_irqsave(lock, flags);
496
497 bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
498
499 end = HW_SYNC_TIMEOUT_MSECS;
500 while (end > 0) {
501 if (!(readl(bt_cmd) >> BT_CMD_SYNC_SHIFT))
502 break;
503
504 mdelay(HW_SYNC_SLEEP_TIME_INTERVAL);
505 end -= HW_SYNC_SLEEP_TIME_INTERVAL;
506 }
507
508 if (end <= 0) {
509 dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
510 spin_unlock_irqrestore(lock, flags);
511 return -EBUSY;
512 }
513
514 bt_cmd_l = cpu_to_le32(bt_ba);
515 roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
516 ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S,
517 upper_32_bits(bt_ba));
518
519 bt_cmd_val[0] = bt_cmd_l;
520 bt_cmd_val[1] = bt_cmd_h;
521 hns_roce_write64_k(bt_cmd_val,
522 hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
523 spin_unlock_irqrestore(lock, flags);
524 }
525
526 return ret;
527 }
528
hns_roce_set_db_ext_mode(struct hns_roce_dev * hr_dev,u32 sdb_mode,u32 odb_mode)529 static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode,
530 u32 odb_mode)
531 {
532 __le32 tmp;
533 u32 val;
534
535 /* Configure SDB/ODB extend mode */
536 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
537 tmp = cpu_to_le32(val);
538 roce_set_bit(tmp, ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S, sdb_mode);
539 roce_set_bit(tmp, ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S, odb_mode);
540 val = le32_to_cpu(tmp);
541 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
542 }
543
hns_roce_set_sdb(struct hns_roce_dev * hr_dev,u32 sdb_alept,u32 sdb_alful)544 static void hns_roce_set_sdb(struct hns_roce_dev *hr_dev, u32 sdb_alept,
545 u32 sdb_alful)
546 {
547 __le32 tmp;
548 u32 val;
549
550 /* Configure SDB */
551 val = roce_read(hr_dev, ROCEE_DB_SQ_WL_REG);
552 tmp = cpu_to_le32(val);
553 roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M,
554 ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S, sdb_alful);
555 roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M,
556 ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S, sdb_alept);
557 val = le32_to_cpu(tmp);
558 roce_write(hr_dev, ROCEE_DB_SQ_WL_REG, val);
559 }
560
hns_roce_set_odb(struct hns_roce_dev * hr_dev,u32 odb_alept,u32 odb_alful)561 static void hns_roce_set_odb(struct hns_roce_dev *hr_dev, u32 odb_alept,
562 u32 odb_alful)
563 {
564 __le32 tmp;
565 u32 val;
566
567 /* Configure ODB */
568 val = roce_read(hr_dev, ROCEE_DB_OTHERS_WL_REG);
569 tmp = cpu_to_le32(val);
570 roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M,
571 ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S, odb_alful);
572 roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M,
573 ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S, odb_alept);
574 val = le32_to_cpu(tmp);
575 roce_write(hr_dev, ROCEE_DB_OTHERS_WL_REG, val);
576 }
577
hns_roce_set_sdb_ext(struct hns_roce_dev * hr_dev,u32 ext_sdb_alept,u32 ext_sdb_alful)578 static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept,
579 u32 ext_sdb_alful)
580 {
581 struct hns_roce_v1_priv *priv = hr_dev->priv;
582 struct hns_roce_db_table *db = &priv->db_table;
583 struct device *dev = &hr_dev->pdev->dev;
584 dma_addr_t sdb_dma_addr;
585 __le32 tmp;
586 u32 val;
587
588 /* Configure extend SDB threshold */
589 roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_EMPTY_REG, ext_sdb_alept);
590 roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_REG, ext_sdb_alful);
591
592 /* Configure extend SDB base addr */
593 sdb_dma_addr = db->ext_db->sdb_buf_list->map;
594 roce_write(hr_dev, ROCEE_EXT_DB_SQ_REG, (u32)(sdb_dma_addr >> 12));
595
596 /* Configure extend SDB depth */
597 val = roce_read(hr_dev, ROCEE_EXT_DB_SQ_H_REG);
598 tmp = cpu_to_le32(val);
599 roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M,
600 ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S,
601 db->ext_db->esdb_dep);
602 /*
603 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
604 * using 4K page, and shift more 32 because of
605 * caculating the high 32 bit value evaluated to hardware.
606 */
607 roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M,
608 ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S, sdb_dma_addr >> 44);
609 val = le32_to_cpu(tmp);
610 roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val);
611
612 dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep);
613 dev_dbg(dev, "ext SDB threshold: empty: 0x%x, ful: 0x%x\n",
614 ext_sdb_alept, ext_sdb_alful);
615 }
616
hns_roce_set_odb_ext(struct hns_roce_dev * hr_dev,u32 ext_odb_alept,u32 ext_odb_alful)617 static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept,
618 u32 ext_odb_alful)
619 {
620 struct hns_roce_v1_priv *priv = hr_dev->priv;
621 struct hns_roce_db_table *db = &priv->db_table;
622 struct device *dev = &hr_dev->pdev->dev;
623 dma_addr_t odb_dma_addr;
624 __le32 tmp;
625 u32 val;
626
627 /* Configure extend ODB threshold */
628 roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG, ext_odb_alept);
629 roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_REG, ext_odb_alful);
630
631 /* Configure extend ODB base addr */
632 odb_dma_addr = db->ext_db->odb_buf_list->map;
633 roce_write(hr_dev, ROCEE_EXT_DB_OTH_REG, (u32)(odb_dma_addr >> 12));
634
635 /* Configure extend ODB depth */
636 val = roce_read(hr_dev, ROCEE_EXT_DB_OTH_H_REG);
637 tmp = cpu_to_le32(val);
638 roce_set_field(tmp, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M,
639 ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S,
640 db->ext_db->eodb_dep);
641 roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M,
642 ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S,
643 db->ext_db->eodb_dep);
644 val = le32_to_cpu(tmp);
645 roce_write(hr_dev, ROCEE_EXT_DB_OTH_H_REG, val);
646
647 dev_dbg(dev, "ext ODB depth: 0x%x\n", db->ext_db->eodb_dep);
648 dev_dbg(dev, "ext ODB threshold: empty: 0x%x, ful: 0x%x\n",
649 ext_odb_alept, ext_odb_alful);
650 }
651
hns_roce_db_ext_init(struct hns_roce_dev * hr_dev,u32 sdb_ext_mod,u32 odb_ext_mod)652 static int hns_roce_db_ext_init(struct hns_roce_dev *hr_dev, u32 sdb_ext_mod,
653 u32 odb_ext_mod)
654 {
655 struct hns_roce_v1_priv *priv = hr_dev->priv;
656 struct hns_roce_db_table *db = &priv->db_table;
657 struct device *dev = &hr_dev->pdev->dev;
658 dma_addr_t sdb_dma_addr;
659 dma_addr_t odb_dma_addr;
660 int ret = 0;
661
662 db->ext_db = kmalloc(sizeof(*db->ext_db), GFP_KERNEL);
663 if (!db->ext_db)
664 return -ENOMEM;
665
666 if (sdb_ext_mod) {
667 db->ext_db->sdb_buf_list = kmalloc(
668 sizeof(*db->ext_db->sdb_buf_list), GFP_KERNEL);
669 if (!db->ext_db->sdb_buf_list) {
670 ret = -ENOMEM;
671 goto ext_sdb_buf_fail_out;
672 }
673
674 db->ext_db->sdb_buf_list->buf = dma_alloc_coherent(dev,
675 HNS_ROCE_V1_EXT_SDB_SIZE,
676 &sdb_dma_addr, GFP_KERNEL);
677 if (!db->ext_db->sdb_buf_list->buf) {
678 ret = -ENOMEM;
679 goto alloc_sq_db_buf_fail;
680 }
681 db->ext_db->sdb_buf_list->map = sdb_dma_addr;
682
683 db->ext_db->esdb_dep = ilog2(HNS_ROCE_V1_EXT_SDB_DEPTH);
684 hns_roce_set_sdb_ext(hr_dev, HNS_ROCE_V1_EXT_SDB_ALEPT,
685 HNS_ROCE_V1_EXT_SDB_ALFUL);
686 } else
687 hns_roce_set_sdb(hr_dev, HNS_ROCE_V1_SDB_ALEPT,
688 HNS_ROCE_V1_SDB_ALFUL);
689
690 if (odb_ext_mod) {
691 db->ext_db->odb_buf_list = kmalloc(
692 sizeof(*db->ext_db->odb_buf_list), GFP_KERNEL);
693 if (!db->ext_db->odb_buf_list) {
694 ret = -ENOMEM;
695 goto ext_odb_buf_fail_out;
696 }
697
698 db->ext_db->odb_buf_list->buf = dma_alloc_coherent(dev,
699 HNS_ROCE_V1_EXT_ODB_SIZE,
700 &odb_dma_addr, GFP_KERNEL);
701 if (!db->ext_db->odb_buf_list->buf) {
702 ret = -ENOMEM;
703 goto alloc_otr_db_buf_fail;
704 }
705 db->ext_db->odb_buf_list->map = odb_dma_addr;
706
707 db->ext_db->eodb_dep = ilog2(HNS_ROCE_V1_EXT_ODB_DEPTH);
708 hns_roce_set_odb_ext(hr_dev, HNS_ROCE_V1_EXT_ODB_ALEPT,
709 HNS_ROCE_V1_EXT_ODB_ALFUL);
710 } else
711 hns_roce_set_odb(hr_dev, HNS_ROCE_V1_ODB_ALEPT,
712 HNS_ROCE_V1_ODB_ALFUL);
713
714 hns_roce_set_db_ext_mode(hr_dev, sdb_ext_mod, odb_ext_mod);
715
716 return 0;
717
718 alloc_otr_db_buf_fail:
719 kfree(db->ext_db->odb_buf_list);
720
721 ext_odb_buf_fail_out:
722 if (sdb_ext_mod) {
723 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
724 db->ext_db->sdb_buf_list->buf,
725 db->ext_db->sdb_buf_list->map);
726 }
727
728 alloc_sq_db_buf_fail:
729 if (sdb_ext_mod)
730 kfree(db->ext_db->sdb_buf_list);
731
732 ext_sdb_buf_fail_out:
733 kfree(db->ext_db);
734 return ret;
735 }
736
hns_roce_v1_create_lp_qp(struct hns_roce_dev * hr_dev,struct ib_pd * pd)737 static struct hns_roce_qp *hns_roce_v1_create_lp_qp(struct hns_roce_dev *hr_dev,
738 struct ib_pd *pd)
739 {
740 struct device *dev = &hr_dev->pdev->dev;
741 struct ib_qp_init_attr init_attr;
742 struct ib_qp *qp;
743
744 memset(&init_attr, 0, sizeof(struct ib_qp_init_attr));
745 init_attr.qp_type = IB_QPT_RC;
746 init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
747 init_attr.cap.max_recv_wr = HNS_ROCE_MIN_WQE_NUM;
748 init_attr.cap.max_send_wr = HNS_ROCE_MIN_WQE_NUM;
749
750 qp = hns_roce_create_qp(pd, &init_attr, NULL);
751 if (IS_ERR(qp)) {
752 dev_err(dev, "Create loop qp for mr free failed!");
753 return NULL;
754 }
755
756 return to_hr_qp(qp);
757 }
758
hns_roce_v1_rsv_lp_qp(struct hns_roce_dev * hr_dev)759 static int hns_roce_v1_rsv_lp_qp(struct hns_roce_dev *hr_dev)
760 {
761 struct hns_roce_v1_priv *priv = hr_dev->priv;
762 struct hns_roce_free_mr *free_mr = &priv->free_mr;
763 struct hns_roce_caps *caps = &hr_dev->caps;
764 struct ib_device *ibdev = &hr_dev->ib_dev;
765 struct device *dev = &hr_dev->pdev->dev;
766 struct ib_cq_init_attr cq_init_attr;
767 struct ib_qp_attr attr = { 0 };
768 struct hns_roce_qp *hr_qp;
769 struct ib_cq *cq;
770 struct ib_pd *pd;
771 union ib_gid dgid;
772 __be64 subnet_prefix;
773 int attr_mask = 0;
774 int ret;
775 int i, j;
776 u8 queue_en[HNS_ROCE_V1_RESV_QP] = { 0 };
777 u8 phy_port;
778 u8 port = 0;
779 u8 sl;
780
781 /* Reserved cq for loop qp */
782 cq_init_attr.cqe = HNS_ROCE_MIN_WQE_NUM * 2;
783 cq_init_attr.comp_vector = 0;
784
785 cq = rdma_zalloc_drv_obj(ibdev, ib_cq);
786 if (!cq)
787 return -ENOMEM;
788
789 ret = hns_roce_create_cq(cq, &cq_init_attr, NULL);
790 if (ret) {
791 dev_err(dev, "Create cq for reserved loop qp failed!");
792 goto alloc_cq_failed;
793 }
794 free_mr->mr_free_cq = to_hr_cq(cq);
795 free_mr->mr_free_cq->ib_cq.device = &hr_dev->ib_dev;
796 free_mr->mr_free_cq->ib_cq.uobject = NULL;
797 free_mr->mr_free_cq->ib_cq.comp_handler = NULL;
798 free_mr->mr_free_cq->ib_cq.event_handler = NULL;
799 free_mr->mr_free_cq->ib_cq.cq_context = NULL;
800 atomic_set(&free_mr->mr_free_cq->ib_cq.usecnt, 0);
801
802 pd = rdma_zalloc_drv_obj(ibdev, ib_pd);
803 if (!pd) {
804 ret = -ENOMEM;
805 goto alloc_mem_failed;
806 }
807
808 pd->device = ibdev;
809 ret = hns_roce_alloc_pd(pd, NULL);
810 if (ret)
811 goto alloc_pd_failed;
812
813 free_mr->mr_free_pd = to_hr_pd(pd);
814 free_mr->mr_free_pd->ibpd.device = &hr_dev->ib_dev;
815 free_mr->mr_free_pd->ibpd.uobject = NULL;
816 free_mr->mr_free_pd->ibpd.__internal_mr = NULL;
817 atomic_set(&free_mr->mr_free_pd->ibpd.usecnt, 0);
818
819 attr.qp_access_flags = IB_ACCESS_REMOTE_WRITE;
820 attr.pkey_index = 0;
821 attr.min_rnr_timer = 0;
822 /* Disable read ability */
823 attr.max_dest_rd_atomic = 0;
824 attr.max_rd_atomic = 0;
825 /* Use arbitrary values as rq_psn and sq_psn */
826 attr.rq_psn = 0x0808;
827 attr.sq_psn = 0x0808;
828 attr.retry_cnt = 7;
829 attr.rnr_retry = 7;
830 attr.timeout = 0x12;
831 attr.path_mtu = IB_MTU_256;
832 attr.ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
833 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
834 rdma_ah_set_static_rate(&attr.ah_attr, 3);
835
836 subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
837 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
838 phy_port = (i >= HNS_ROCE_MAX_PORTS) ? (i - 2) :
839 (i % HNS_ROCE_MAX_PORTS);
840 sl = i / HNS_ROCE_MAX_PORTS;
841
842 for (j = 0; j < caps->num_ports; j++) {
843 if (hr_dev->iboe.phy_port[j] == phy_port) {
844 queue_en[i] = 1;
845 port = j;
846 break;
847 }
848 }
849
850 if (!queue_en[i])
851 continue;
852
853 free_mr->mr_free_qp[i] = hns_roce_v1_create_lp_qp(hr_dev, pd);
854 if (!free_mr->mr_free_qp[i]) {
855 dev_err(dev, "Create loop qp failed!\n");
856 ret = -ENOMEM;
857 goto create_lp_qp_failed;
858 }
859 hr_qp = free_mr->mr_free_qp[i];
860
861 hr_qp->port = port;
862 hr_qp->phy_port = phy_port;
863 hr_qp->ibqp.qp_type = IB_QPT_RC;
864 hr_qp->ibqp.device = &hr_dev->ib_dev;
865 hr_qp->ibqp.uobject = NULL;
866 atomic_set(&hr_qp->ibqp.usecnt, 0);
867 hr_qp->ibqp.pd = pd;
868 hr_qp->ibqp.recv_cq = cq;
869 hr_qp->ibqp.send_cq = cq;
870
871 rdma_ah_set_port_num(&attr.ah_attr, port + 1);
872 rdma_ah_set_sl(&attr.ah_attr, sl);
873 attr.port_num = port + 1;
874
875 attr.dest_qp_num = hr_qp->qpn;
876 memcpy(rdma_ah_retrieve_dmac(&attr.ah_attr),
877 hr_dev->dev_addr[port],
878 ETH_ALEN);
879
880 memcpy(&dgid.raw, &subnet_prefix, sizeof(u64));
881 memcpy(&dgid.raw[8], hr_dev->dev_addr[port], 3);
882 memcpy(&dgid.raw[13], hr_dev->dev_addr[port] + 3, 3);
883 dgid.raw[11] = 0xff;
884 dgid.raw[12] = 0xfe;
885 dgid.raw[8] ^= 2;
886 rdma_ah_set_dgid_raw(&attr.ah_attr, dgid.raw);
887
888 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
889 IB_QPS_RESET, IB_QPS_INIT);
890 if (ret) {
891 dev_err(dev, "modify qp failed(%d)!\n", ret);
892 goto create_lp_qp_failed;
893 }
894
895 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, IB_QP_DEST_QPN,
896 IB_QPS_INIT, IB_QPS_RTR);
897 if (ret) {
898 dev_err(dev, "modify qp failed(%d)!\n", ret);
899 goto create_lp_qp_failed;
900 }
901
902 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
903 IB_QPS_RTR, IB_QPS_RTS);
904 if (ret) {
905 dev_err(dev, "modify qp failed(%d)!\n", ret);
906 goto create_lp_qp_failed;
907 }
908 }
909
910 return 0;
911
912 create_lp_qp_failed:
913 for (i -= 1; i >= 0; i--) {
914 hr_qp = free_mr->mr_free_qp[i];
915 if (hns_roce_v1_destroy_qp(&hr_qp->ibqp, NULL))
916 dev_err(dev, "Destroy qp %d for mr free failed!\n", i);
917 }
918
919 hns_roce_dealloc_pd(pd, NULL);
920
921 alloc_pd_failed:
922 kfree(pd);
923
924 alloc_mem_failed:
925 hns_roce_destroy_cq(cq, NULL);
926 alloc_cq_failed:
927 kfree(cq);
928 return ret;
929 }
930
hns_roce_v1_release_lp_qp(struct hns_roce_dev * hr_dev)931 static void hns_roce_v1_release_lp_qp(struct hns_roce_dev *hr_dev)
932 {
933 struct hns_roce_v1_priv *priv = hr_dev->priv;
934 struct hns_roce_free_mr *free_mr = &priv->free_mr;
935 struct device *dev = &hr_dev->pdev->dev;
936 struct hns_roce_qp *hr_qp;
937 int ret;
938 int i;
939
940 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
941 hr_qp = free_mr->mr_free_qp[i];
942 if (!hr_qp)
943 continue;
944
945 ret = hns_roce_v1_destroy_qp(&hr_qp->ibqp, NULL);
946 if (ret)
947 dev_err(dev, "Destroy qp %d for mr free failed(%d)!\n",
948 i, ret);
949 }
950
951 hns_roce_destroy_cq(&free_mr->mr_free_cq->ib_cq, NULL);
952 kfree(&free_mr->mr_free_cq->ib_cq);
953 hns_roce_dealloc_pd(&free_mr->mr_free_pd->ibpd, NULL);
954 kfree(&free_mr->mr_free_pd->ibpd);
955 }
956
hns_roce_db_init(struct hns_roce_dev * hr_dev)957 static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
958 {
959 struct hns_roce_v1_priv *priv = hr_dev->priv;
960 struct hns_roce_db_table *db = &priv->db_table;
961 struct device *dev = &hr_dev->pdev->dev;
962 u32 sdb_ext_mod;
963 u32 odb_ext_mod;
964 u32 sdb_evt_mod;
965 u32 odb_evt_mod;
966 int ret;
967
968 memset(db, 0, sizeof(*db));
969
970 /* Default DB mode */
971 sdb_ext_mod = HNS_ROCE_SDB_EXTEND_MODE;
972 odb_ext_mod = HNS_ROCE_ODB_EXTEND_MODE;
973 sdb_evt_mod = HNS_ROCE_SDB_NORMAL_MODE;
974 odb_evt_mod = HNS_ROCE_ODB_POLL_MODE;
975
976 db->sdb_ext_mod = sdb_ext_mod;
977 db->odb_ext_mod = odb_ext_mod;
978
979 /* Init extend DB */
980 ret = hns_roce_db_ext_init(hr_dev, sdb_ext_mod, odb_ext_mod);
981 if (ret) {
982 dev_err(dev, "Failed in extend DB configuration.\n");
983 return ret;
984 }
985
986 hns_roce_set_db_event_mode(hr_dev, sdb_evt_mod, odb_evt_mod);
987
988 return 0;
989 }
990
hns_roce_v1_recreate_lp_qp_work_fn(struct work_struct * work)991 static void hns_roce_v1_recreate_lp_qp_work_fn(struct work_struct *work)
992 {
993 struct hns_roce_recreate_lp_qp_work *lp_qp_work;
994 struct hns_roce_dev *hr_dev;
995
996 lp_qp_work = container_of(work, struct hns_roce_recreate_lp_qp_work,
997 work);
998 hr_dev = to_hr_dev(lp_qp_work->ib_dev);
999
1000 hns_roce_v1_release_lp_qp(hr_dev);
1001
1002 if (hns_roce_v1_rsv_lp_qp(hr_dev))
1003 dev_err(&hr_dev->pdev->dev, "create reserver qp failed\n");
1004
1005 if (lp_qp_work->comp_flag)
1006 complete(lp_qp_work->comp);
1007
1008 kfree(lp_qp_work);
1009 }
1010
hns_roce_v1_recreate_lp_qp(struct hns_roce_dev * hr_dev)1011 static int hns_roce_v1_recreate_lp_qp(struct hns_roce_dev *hr_dev)
1012 {
1013 long end = HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS;
1014 struct hns_roce_v1_priv *priv = hr_dev->priv;
1015 struct hns_roce_free_mr *free_mr = &priv->free_mr;
1016 struct hns_roce_recreate_lp_qp_work *lp_qp_work;
1017 struct device *dev = &hr_dev->pdev->dev;
1018 struct completion comp;
1019
1020 lp_qp_work = kzalloc(sizeof(struct hns_roce_recreate_lp_qp_work),
1021 GFP_KERNEL);
1022 if (!lp_qp_work)
1023 return -ENOMEM;
1024
1025 INIT_WORK(&(lp_qp_work->work), hns_roce_v1_recreate_lp_qp_work_fn);
1026
1027 lp_qp_work->ib_dev = &(hr_dev->ib_dev);
1028 lp_qp_work->comp = ∁
1029 lp_qp_work->comp_flag = 1;
1030
1031 init_completion(lp_qp_work->comp);
1032
1033 queue_work(free_mr->free_mr_wq, &(lp_qp_work->work));
1034
1035 while (end > 0) {
1036 if (try_wait_for_completion(&comp))
1037 return 0;
1038 msleep(HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE);
1039 end -= HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE;
1040 }
1041
1042 lp_qp_work->comp_flag = 0;
1043 if (try_wait_for_completion(&comp))
1044 return 0;
1045
1046 dev_warn(dev, "recreate lp qp failed 20s timeout and return failed!\n");
1047 return -ETIMEDOUT;
1048 }
1049
hns_roce_v1_send_lp_wqe(struct hns_roce_qp * hr_qp)1050 static int hns_roce_v1_send_lp_wqe(struct hns_roce_qp *hr_qp)
1051 {
1052 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
1053 struct device *dev = &hr_dev->pdev->dev;
1054 struct ib_send_wr send_wr;
1055 const struct ib_send_wr *bad_wr;
1056 int ret;
1057
1058 memset(&send_wr, 0, sizeof(send_wr));
1059 send_wr.next = NULL;
1060 send_wr.num_sge = 0;
1061 send_wr.send_flags = 0;
1062 send_wr.sg_list = NULL;
1063 send_wr.wr_id = (unsigned long long)&send_wr;
1064 send_wr.opcode = IB_WR_RDMA_WRITE;
1065
1066 ret = hns_roce_v1_post_send(&hr_qp->ibqp, &send_wr, &bad_wr);
1067 if (ret) {
1068 dev_err(dev, "Post write wqe for mr free failed(%d)!", ret);
1069 return ret;
1070 }
1071
1072 return 0;
1073 }
1074
hns_roce_v1_mr_free_work_fn(struct work_struct * work)1075 static void hns_roce_v1_mr_free_work_fn(struct work_struct *work)
1076 {
1077 unsigned long end =
1078 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1079 struct hns_roce_mr_free_work *mr_work =
1080 container_of(work, struct hns_roce_mr_free_work, work);
1081 struct hns_roce_dev *hr_dev = to_hr_dev(mr_work->ib_dev);
1082 struct hns_roce_v1_priv *priv = hr_dev->priv;
1083 struct hns_roce_free_mr *free_mr = &priv->free_mr;
1084 struct hns_roce_cq *mr_free_cq = free_mr->mr_free_cq;
1085 struct hns_roce_mr *hr_mr = mr_work->mr;
1086 struct device *dev = &hr_dev->pdev->dev;
1087 struct ib_wc wc[HNS_ROCE_V1_RESV_QP];
1088 struct hns_roce_qp *hr_qp;
1089 int ne = 0;
1090 int ret;
1091 int i;
1092
1093 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
1094 hr_qp = free_mr->mr_free_qp[i];
1095 if (!hr_qp)
1096 continue;
1097 ne++;
1098
1099 ret = hns_roce_v1_send_lp_wqe(hr_qp);
1100 if (ret) {
1101 dev_err(dev,
1102 "Send wqe (qp:0x%lx) for mr free failed(%d)!\n",
1103 hr_qp->qpn, ret);
1104 goto free_work;
1105 }
1106 }
1107
1108 if (!ne) {
1109 dev_err(dev, "Reserved loop qp is absent!\n");
1110 goto free_work;
1111 }
1112
1113 do {
1114 ret = hns_roce_v1_poll_cq(&mr_free_cq->ib_cq, ne, wc);
1115 if (ret < 0 && hr_qp) {
1116 dev_err(dev,
1117 "(qp:0x%lx) starts, Poll cqe failed(%d) for mr 0x%x free! Remain %d cqe\n",
1118 hr_qp->qpn, ret, hr_mr->key, ne);
1119 goto free_work;
1120 }
1121 ne -= ret;
1122 usleep_range(HNS_ROCE_V1_FREE_MR_WAIT_VALUE * 1000,
1123 (1 + HNS_ROCE_V1_FREE_MR_WAIT_VALUE) * 1000);
1124 } while (ne && time_before_eq(jiffies, end));
1125
1126 if (ne != 0)
1127 dev_err(dev,
1128 "Poll cqe for mr 0x%x free timeout! Remain %d cqe\n",
1129 hr_mr->key, ne);
1130
1131 free_work:
1132 if (mr_work->comp_flag)
1133 complete(mr_work->comp);
1134 kfree(mr_work);
1135 }
1136
hns_roce_v1_dereg_mr(struct hns_roce_dev * hr_dev,struct hns_roce_mr * mr,struct ib_udata * udata)1137 static int hns_roce_v1_dereg_mr(struct hns_roce_dev *hr_dev,
1138 struct hns_roce_mr *mr, struct ib_udata *udata)
1139 {
1140 struct hns_roce_v1_priv *priv = hr_dev->priv;
1141 struct hns_roce_free_mr *free_mr = &priv->free_mr;
1142 long end = HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS;
1143 struct device *dev = &hr_dev->pdev->dev;
1144 struct hns_roce_mr_free_work *mr_work;
1145 unsigned long start = jiffies;
1146 struct completion comp;
1147 int ret = 0;
1148
1149 if (mr->enabled) {
1150 if (hns_roce_hw_destroy_mpt(hr_dev, NULL,
1151 key_to_hw_index(mr->key) &
1152 (hr_dev->caps.num_mtpts - 1)))
1153 dev_warn(dev, "DESTROY_MPT failed!\n");
1154 }
1155
1156 mr_work = kzalloc(sizeof(*mr_work), GFP_KERNEL);
1157 if (!mr_work) {
1158 ret = -ENOMEM;
1159 goto free_mr;
1160 }
1161
1162 INIT_WORK(&(mr_work->work), hns_roce_v1_mr_free_work_fn);
1163
1164 mr_work->ib_dev = &(hr_dev->ib_dev);
1165 mr_work->comp = ∁
1166 mr_work->comp_flag = 1;
1167 mr_work->mr = (void *)mr;
1168 init_completion(mr_work->comp);
1169
1170 queue_work(free_mr->free_mr_wq, &(mr_work->work));
1171
1172 while (end > 0) {
1173 if (try_wait_for_completion(&comp))
1174 goto free_mr;
1175 msleep(HNS_ROCE_V1_FREE_MR_WAIT_VALUE);
1176 end -= HNS_ROCE_V1_FREE_MR_WAIT_VALUE;
1177 }
1178
1179 mr_work->comp_flag = 0;
1180 if (try_wait_for_completion(&comp))
1181 goto free_mr;
1182
1183 dev_warn(dev, "Free mr work 0x%x over 50s and failed!\n", mr->key);
1184 ret = -ETIMEDOUT;
1185
1186 free_mr:
1187 dev_dbg(dev, "Free mr 0x%x use 0x%x us.\n",
1188 mr->key, jiffies_to_usecs(jiffies) - jiffies_to_usecs(start));
1189
1190 hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
1191 key_to_hw_index(mr->key), 0);
1192 hns_roce_mtr_destroy(hr_dev, &mr->pbl_mtr);
1193 kfree(mr);
1194
1195 return ret;
1196 }
1197
hns_roce_db_free(struct hns_roce_dev * hr_dev)1198 static void hns_roce_db_free(struct hns_roce_dev *hr_dev)
1199 {
1200 struct hns_roce_v1_priv *priv = hr_dev->priv;
1201 struct hns_roce_db_table *db = &priv->db_table;
1202 struct device *dev = &hr_dev->pdev->dev;
1203
1204 if (db->sdb_ext_mod) {
1205 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
1206 db->ext_db->sdb_buf_list->buf,
1207 db->ext_db->sdb_buf_list->map);
1208 kfree(db->ext_db->sdb_buf_list);
1209 }
1210
1211 if (db->odb_ext_mod) {
1212 dma_free_coherent(dev, HNS_ROCE_V1_EXT_ODB_SIZE,
1213 db->ext_db->odb_buf_list->buf,
1214 db->ext_db->odb_buf_list->map);
1215 kfree(db->ext_db->odb_buf_list);
1216 }
1217
1218 kfree(db->ext_db);
1219 }
1220
hns_roce_raq_init(struct hns_roce_dev * hr_dev)1221 static int hns_roce_raq_init(struct hns_roce_dev *hr_dev)
1222 {
1223 struct hns_roce_v1_priv *priv = hr_dev->priv;
1224 struct hns_roce_raq_table *raq = &priv->raq_table;
1225 struct device *dev = &hr_dev->pdev->dev;
1226 dma_addr_t addr;
1227 int raq_shift;
1228 __le32 tmp;
1229 u32 val;
1230 int ret;
1231
1232 raq->e_raq_buf = kzalloc(sizeof(*(raq->e_raq_buf)), GFP_KERNEL);
1233 if (!raq->e_raq_buf)
1234 return -ENOMEM;
1235
1236 raq->e_raq_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_RAQ_SIZE,
1237 &addr, GFP_KERNEL);
1238 if (!raq->e_raq_buf->buf) {
1239 ret = -ENOMEM;
1240 goto err_dma_alloc_raq;
1241 }
1242 raq->e_raq_buf->map = addr;
1243
1244 /* Configure raq extended address. 48bit 4K align */
1245 roce_write(hr_dev, ROCEE_EXT_RAQ_REG, raq->e_raq_buf->map >> 12);
1246
1247 /* Configure raq_shift */
1248 raq_shift = ilog2(HNS_ROCE_V1_RAQ_SIZE / HNS_ROCE_V1_RAQ_ENTRY);
1249 val = roce_read(hr_dev, ROCEE_EXT_RAQ_H_REG);
1250 tmp = cpu_to_le32(val);
1251 roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M,
1252 ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S, raq_shift);
1253 /*
1254 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
1255 * using 4K page, and shift more 32 because of
1256 * caculating the high 32 bit value evaluated to hardware.
1257 */
1258 roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M,
1259 ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S,
1260 raq->e_raq_buf->map >> 44);
1261 val = le32_to_cpu(tmp);
1262 roce_write(hr_dev, ROCEE_EXT_RAQ_H_REG, val);
1263 dev_dbg(dev, "Configure raq_shift 0x%x.\n", val);
1264
1265 /* Configure raq threshold */
1266 val = roce_read(hr_dev, ROCEE_RAQ_WL_REG);
1267 tmp = cpu_to_le32(val);
1268 roce_set_field(tmp, ROCEE_RAQ_WL_ROCEE_RAQ_WL_M,
1269 ROCEE_RAQ_WL_ROCEE_RAQ_WL_S,
1270 HNS_ROCE_V1_EXT_RAQ_WF);
1271 val = le32_to_cpu(tmp);
1272 roce_write(hr_dev, ROCEE_RAQ_WL_REG, val);
1273 dev_dbg(dev, "Configure raq_wl 0x%x.\n", val);
1274
1275 /* Enable extend raq */
1276 val = roce_read(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG);
1277 tmp = cpu_to_le32(val);
1278 roce_set_field(tmp,
1279 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M,
1280 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S,
1281 POL_TIME_INTERVAL_VAL);
1282 roce_set_bit(tmp, ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE, 1);
1283 roce_set_field(tmp,
1284 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M,
1285 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S,
1286 2);
1287 roce_set_bit(tmp,
1288 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S, 1);
1289 val = le32_to_cpu(tmp);
1290 roce_write(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG, val);
1291 dev_dbg(dev, "Configure WrmsPolTimeInterval 0x%x.\n", val);
1292
1293 /* Enable raq drop */
1294 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1295 tmp = cpu_to_le32(val);
1296 roce_set_bit(tmp, ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S, 1);
1297 val = le32_to_cpu(tmp);
1298 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1299 dev_dbg(dev, "Configure GlbCfg = 0x%x.\n", val);
1300
1301 return 0;
1302
1303 err_dma_alloc_raq:
1304 kfree(raq->e_raq_buf);
1305 return ret;
1306 }
1307
hns_roce_raq_free(struct hns_roce_dev * hr_dev)1308 static void hns_roce_raq_free(struct hns_roce_dev *hr_dev)
1309 {
1310 struct hns_roce_v1_priv *priv = hr_dev->priv;
1311 struct hns_roce_raq_table *raq = &priv->raq_table;
1312 struct device *dev = &hr_dev->pdev->dev;
1313
1314 dma_free_coherent(dev, HNS_ROCE_V1_RAQ_SIZE, raq->e_raq_buf->buf,
1315 raq->e_raq_buf->map);
1316 kfree(raq->e_raq_buf);
1317 }
1318
hns_roce_port_enable(struct hns_roce_dev * hr_dev,int enable_flag)1319 static void hns_roce_port_enable(struct hns_roce_dev *hr_dev, int enable_flag)
1320 {
1321 __le32 tmp;
1322 u32 val;
1323
1324 if (enable_flag) {
1325 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1326 /* Open all ports */
1327 tmp = cpu_to_le32(val);
1328 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1329 ROCEE_GLB_CFG_ROCEE_PORT_ST_S,
1330 ALL_PORT_VAL_OPEN);
1331 val = le32_to_cpu(tmp);
1332 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1333 } else {
1334 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1335 /* Close all ports */
1336 tmp = cpu_to_le32(val);
1337 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1338 ROCEE_GLB_CFG_ROCEE_PORT_ST_S, 0x0);
1339 val = le32_to_cpu(tmp);
1340 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1341 }
1342 }
1343
hns_roce_bt_init(struct hns_roce_dev * hr_dev)1344 static int hns_roce_bt_init(struct hns_roce_dev *hr_dev)
1345 {
1346 struct hns_roce_v1_priv *priv = hr_dev->priv;
1347 struct device *dev = &hr_dev->pdev->dev;
1348 int ret;
1349
1350 priv->bt_table.qpc_buf.buf = dma_alloc_coherent(dev,
1351 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.qpc_buf.map,
1352 GFP_KERNEL);
1353 if (!priv->bt_table.qpc_buf.buf)
1354 return -ENOMEM;
1355
1356 priv->bt_table.mtpt_buf.buf = dma_alloc_coherent(dev,
1357 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.mtpt_buf.map,
1358 GFP_KERNEL);
1359 if (!priv->bt_table.mtpt_buf.buf) {
1360 ret = -ENOMEM;
1361 goto err_failed_alloc_mtpt_buf;
1362 }
1363
1364 priv->bt_table.cqc_buf.buf = dma_alloc_coherent(dev,
1365 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.cqc_buf.map,
1366 GFP_KERNEL);
1367 if (!priv->bt_table.cqc_buf.buf) {
1368 ret = -ENOMEM;
1369 goto err_failed_alloc_cqc_buf;
1370 }
1371
1372 return 0;
1373
1374 err_failed_alloc_cqc_buf:
1375 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1376 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1377
1378 err_failed_alloc_mtpt_buf:
1379 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1380 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1381
1382 return ret;
1383 }
1384
hns_roce_bt_free(struct hns_roce_dev * hr_dev)1385 static void hns_roce_bt_free(struct hns_roce_dev *hr_dev)
1386 {
1387 struct hns_roce_v1_priv *priv = hr_dev->priv;
1388 struct device *dev = &hr_dev->pdev->dev;
1389
1390 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1391 priv->bt_table.cqc_buf.buf, priv->bt_table.cqc_buf.map);
1392
1393 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1394 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1395
1396 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1397 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1398 }
1399
hns_roce_tptr_init(struct hns_roce_dev * hr_dev)1400 static int hns_roce_tptr_init(struct hns_roce_dev *hr_dev)
1401 {
1402 struct hns_roce_v1_priv *priv = hr_dev->priv;
1403 struct hns_roce_buf_list *tptr_buf = &priv->tptr_table.tptr_buf;
1404 struct device *dev = &hr_dev->pdev->dev;
1405
1406 /*
1407 * This buffer will be used for CQ's tptr(tail pointer), also
1408 * named ci(customer index). Every CQ will use 2 bytes to save
1409 * cqe ci in hip06. Hardware will read this area to get new ci
1410 * when the queue is almost full.
1411 */
1412 tptr_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1413 &tptr_buf->map, GFP_KERNEL);
1414 if (!tptr_buf->buf)
1415 return -ENOMEM;
1416
1417 hr_dev->tptr_dma_addr = tptr_buf->map;
1418 hr_dev->tptr_size = HNS_ROCE_V1_TPTR_BUF_SIZE;
1419
1420 return 0;
1421 }
1422
hns_roce_tptr_free(struct hns_roce_dev * hr_dev)1423 static void hns_roce_tptr_free(struct hns_roce_dev *hr_dev)
1424 {
1425 struct hns_roce_v1_priv *priv = hr_dev->priv;
1426 struct hns_roce_buf_list *tptr_buf = &priv->tptr_table.tptr_buf;
1427 struct device *dev = &hr_dev->pdev->dev;
1428
1429 dma_free_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1430 tptr_buf->buf, tptr_buf->map);
1431 }
1432
hns_roce_free_mr_init(struct hns_roce_dev * hr_dev)1433 static int hns_roce_free_mr_init(struct hns_roce_dev *hr_dev)
1434 {
1435 struct hns_roce_v1_priv *priv = hr_dev->priv;
1436 struct hns_roce_free_mr *free_mr = &priv->free_mr;
1437 struct device *dev = &hr_dev->pdev->dev;
1438 int ret;
1439
1440 free_mr->free_mr_wq = create_singlethread_workqueue("hns_roce_free_mr");
1441 if (!free_mr->free_mr_wq) {
1442 dev_err(dev, "Create free mr workqueue failed!\n");
1443 return -ENOMEM;
1444 }
1445
1446 ret = hns_roce_v1_rsv_lp_qp(hr_dev);
1447 if (ret) {
1448 dev_err(dev, "Reserved loop qp failed(%d)!\n", ret);
1449 flush_workqueue(free_mr->free_mr_wq);
1450 destroy_workqueue(free_mr->free_mr_wq);
1451 }
1452
1453 return ret;
1454 }
1455
hns_roce_free_mr_free(struct hns_roce_dev * hr_dev)1456 static void hns_roce_free_mr_free(struct hns_roce_dev *hr_dev)
1457 {
1458 struct hns_roce_v1_priv *priv = hr_dev->priv;
1459 struct hns_roce_free_mr *free_mr = &priv->free_mr;
1460
1461 flush_workqueue(free_mr->free_mr_wq);
1462 destroy_workqueue(free_mr->free_mr_wq);
1463
1464 hns_roce_v1_release_lp_qp(hr_dev);
1465 }
1466
1467 /**
1468 * hns_roce_v1_reset - reset RoCE
1469 * @hr_dev: RoCE device struct pointer
1470 * @enable: true -- drop reset, false -- reset
1471 * return 0 - success , negative --fail
1472 */
hns_roce_v1_reset(struct hns_roce_dev * hr_dev,bool dereset)1473 static int hns_roce_v1_reset(struct hns_roce_dev *hr_dev, bool dereset)
1474 {
1475 struct device_node *dsaf_node;
1476 struct device *dev = &hr_dev->pdev->dev;
1477 struct device_node *np = dev->of_node;
1478 struct fwnode_handle *fwnode;
1479 int ret;
1480
1481 /* check if this is DT/ACPI case */
1482 if (dev_of_node(dev)) {
1483 dsaf_node = of_parse_phandle(np, "dsaf-handle", 0);
1484 if (!dsaf_node) {
1485 dev_err(dev, "could not find dsaf-handle\n");
1486 return -EINVAL;
1487 }
1488 fwnode = &dsaf_node->fwnode;
1489 } else if (is_acpi_device_node(dev->fwnode)) {
1490 struct fwnode_reference_args args;
1491
1492 ret = acpi_node_get_property_reference(dev->fwnode,
1493 "dsaf-handle", 0, &args);
1494 if (ret) {
1495 dev_err(dev, "could not find dsaf-handle\n");
1496 return ret;
1497 }
1498 fwnode = args.fwnode;
1499 } else {
1500 dev_err(dev, "cannot read data from DT or ACPI\n");
1501 return -ENXIO;
1502 }
1503
1504 ret = hns_dsaf_roce_reset(fwnode, false);
1505 if (ret)
1506 return ret;
1507
1508 if (dereset) {
1509 msleep(SLEEP_TIME_INTERVAL);
1510 ret = hns_dsaf_roce_reset(fwnode, true);
1511 }
1512
1513 return ret;
1514 }
1515
hns_roce_v1_profile(struct hns_roce_dev * hr_dev)1516 static int hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
1517 {
1518 struct hns_roce_caps *caps = &hr_dev->caps;
1519 int i;
1520
1521 hr_dev->vendor_id = roce_read(hr_dev, ROCEE_VENDOR_ID_REG);
1522 hr_dev->vendor_part_id = roce_read(hr_dev, ROCEE_VENDOR_PART_ID_REG);
1523 hr_dev->sys_image_guid = roce_read(hr_dev, ROCEE_SYS_IMAGE_GUID_L_REG) |
1524 ((u64)roce_read(hr_dev,
1525 ROCEE_SYS_IMAGE_GUID_H_REG) << 32);
1526 hr_dev->hw_rev = HNS_ROCE_HW_VER1;
1527
1528 caps->num_qps = HNS_ROCE_V1_MAX_QP_NUM;
1529 caps->max_wqes = HNS_ROCE_V1_MAX_WQE_NUM;
1530 caps->min_wqes = HNS_ROCE_MIN_WQE_NUM;
1531 caps->num_cqs = HNS_ROCE_V1_MAX_CQ_NUM;
1532 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM;
1533 caps->max_cqes = HNS_ROCE_V1_MAX_CQE_NUM;
1534 caps->max_sq_sg = HNS_ROCE_V1_SG_NUM;
1535 caps->max_rq_sg = HNS_ROCE_V1_SG_NUM;
1536 caps->max_sq_inline = HNS_ROCE_V1_INLINE_SIZE;
1537 caps->num_uars = HNS_ROCE_V1_UAR_NUM;
1538 caps->phy_num_uars = HNS_ROCE_V1_PHY_UAR_NUM;
1539 caps->num_aeq_vectors = HNS_ROCE_V1_AEQE_VEC_NUM;
1540 caps->num_comp_vectors = HNS_ROCE_V1_COMP_VEC_NUM;
1541 caps->num_other_vectors = HNS_ROCE_V1_ABNORMAL_VEC_NUM;
1542 caps->num_mtpts = HNS_ROCE_V1_MAX_MTPT_NUM;
1543 caps->num_mtt_segs = HNS_ROCE_V1_MAX_MTT_SEGS;
1544 caps->num_pds = HNS_ROCE_V1_MAX_PD_NUM;
1545 caps->max_qp_init_rdma = HNS_ROCE_V1_MAX_QP_INIT_RDMA;
1546 caps->max_qp_dest_rdma = HNS_ROCE_V1_MAX_QP_DEST_RDMA;
1547 caps->max_sq_desc_sz = HNS_ROCE_V1_MAX_SQ_DESC_SZ;
1548 caps->max_rq_desc_sz = HNS_ROCE_V1_MAX_RQ_DESC_SZ;
1549 caps->qpc_sz = HNS_ROCE_V1_QPC_SIZE;
1550 caps->irrl_entry_sz = HNS_ROCE_V1_IRRL_ENTRY_SIZE;
1551 caps->cqc_entry_sz = HNS_ROCE_V1_CQC_ENTRY_SIZE;
1552 caps->mtpt_entry_sz = HNS_ROCE_V1_MTPT_ENTRY_SIZE;
1553 caps->mtt_entry_sz = HNS_ROCE_V1_MTT_ENTRY_SIZE;
1554 caps->cqe_sz = HNS_ROCE_V1_CQE_SIZE;
1555 caps->page_size_cap = HNS_ROCE_V1_PAGE_SIZE_SUPPORT;
1556 caps->reserved_lkey = 0;
1557 caps->reserved_pds = 0;
1558 caps->reserved_mrws = 1;
1559 caps->reserved_uars = 0;
1560 caps->reserved_cqs = 0;
1561 caps->reserved_qps = 12; /* 2 SQP per port, six ports total 12 */
1562 caps->chunk_sz = HNS_ROCE_V1_TABLE_CHUNK_SIZE;
1563
1564 for (i = 0; i < caps->num_ports; i++)
1565 caps->pkey_table_len[i] = 1;
1566
1567 for (i = 0; i < caps->num_ports; i++) {
1568 /* Six ports shared 16 GID in v1 engine */
1569 if (i >= (HNS_ROCE_V1_GID_NUM % caps->num_ports))
1570 caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1571 caps->num_ports;
1572 else
1573 caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1574 caps->num_ports + 1;
1575 }
1576
1577 caps->ceqe_depth = HNS_ROCE_V1_COMP_EQE_NUM;
1578 caps->aeqe_depth = HNS_ROCE_V1_ASYNC_EQE_NUM;
1579 caps->local_ca_ack_delay = roce_read(hr_dev, ROCEE_ACK_DELAY_REG);
1580 caps->max_mtu = IB_MTU_2048;
1581
1582 return 0;
1583 }
1584
hns_roce_v1_init(struct hns_roce_dev * hr_dev)1585 static int hns_roce_v1_init(struct hns_roce_dev *hr_dev)
1586 {
1587 int ret;
1588 u32 val;
1589 __le32 tmp;
1590 struct device *dev = &hr_dev->pdev->dev;
1591
1592 /* DMAE user config */
1593 val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG1_REG);
1594 tmp = cpu_to_le32(val);
1595 roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M,
1596 ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S, 0xf);
1597 roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M,
1598 ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S,
1599 1 << PAGES_SHIFT_16);
1600 val = le32_to_cpu(tmp);
1601 roce_write(hr_dev, ROCEE_DMAE_USER_CFG1_REG, val);
1602
1603 val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG2_REG);
1604 tmp = cpu_to_le32(val);
1605 roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M,
1606 ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S, 0xf);
1607 roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M,
1608 ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S,
1609 1 << PAGES_SHIFT_16);
1610
1611 ret = hns_roce_db_init(hr_dev);
1612 if (ret) {
1613 dev_err(dev, "doorbell init failed!\n");
1614 return ret;
1615 }
1616
1617 ret = hns_roce_raq_init(hr_dev);
1618 if (ret) {
1619 dev_err(dev, "raq init failed!\n");
1620 goto error_failed_raq_init;
1621 }
1622
1623 ret = hns_roce_bt_init(hr_dev);
1624 if (ret) {
1625 dev_err(dev, "bt init failed!\n");
1626 goto error_failed_bt_init;
1627 }
1628
1629 ret = hns_roce_tptr_init(hr_dev);
1630 if (ret) {
1631 dev_err(dev, "tptr init failed!\n");
1632 goto error_failed_tptr_init;
1633 }
1634
1635 ret = hns_roce_free_mr_init(hr_dev);
1636 if (ret) {
1637 dev_err(dev, "free mr init failed!\n");
1638 goto error_failed_free_mr_init;
1639 }
1640
1641 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_UP);
1642
1643 return 0;
1644
1645 error_failed_free_mr_init:
1646 hns_roce_tptr_free(hr_dev);
1647
1648 error_failed_tptr_init:
1649 hns_roce_bt_free(hr_dev);
1650
1651 error_failed_bt_init:
1652 hns_roce_raq_free(hr_dev);
1653
1654 error_failed_raq_init:
1655 hns_roce_db_free(hr_dev);
1656 return ret;
1657 }
1658
hns_roce_v1_exit(struct hns_roce_dev * hr_dev)1659 static void hns_roce_v1_exit(struct hns_roce_dev *hr_dev)
1660 {
1661 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
1662 hns_roce_free_mr_free(hr_dev);
1663 hns_roce_tptr_free(hr_dev);
1664 hns_roce_bt_free(hr_dev);
1665 hns_roce_raq_free(hr_dev);
1666 hns_roce_db_free(hr_dev);
1667 }
1668
hns_roce_v1_cmd_pending(struct hns_roce_dev * hr_dev)1669 static int hns_roce_v1_cmd_pending(struct hns_roce_dev *hr_dev)
1670 {
1671 u32 status = readl(hr_dev->reg_base + ROCEE_MB6_REG);
1672
1673 return (!!(status & (1 << HCR_GO_BIT)));
1674 }
1675
hns_roce_v1_post_mbox(struct hns_roce_dev * hr_dev,u64 in_param,u64 out_param,u32 in_modifier,u8 op_modifier,u16 op,u16 token,int event)1676 static int hns_roce_v1_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
1677 u64 out_param, u32 in_modifier, u8 op_modifier,
1678 u16 op, u16 token, int event)
1679 {
1680 u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base + ROCEE_MB1_REG);
1681 unsigned long end;
1682 u32 val = 0;
1683 __le32 tmp;
1684
1685 end = msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS) + jiffies;
1686 while (hns_roce_v1_cmd_pending(hr_dev)) {
1687 if (time_after(jiffies, end)) {
1688 dev_err(hr_dev->dev, "jiffies=%d end=%d\n",
1689 (int)jiffies, (int)end);
1690 return -EAGAIN;
1691 }
1692 cond_resched();
1693 }
1694
1695 tmp = cpu_to_le32(val);
1696 roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_M, ROCEE_MB6_ROCEE_MB_CMD_S,
1697 op);
1698 roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_MDF_M,
1699 ROCEE_MB6_ROCEE_MB_CMD_MDF_S, op_modifier);
1700 roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_EVENT_S, event);
1701 roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_HW_RUN_S, 1);
1702 roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_TOKEN_M,
1703 ROCEE_MB6_ROCEE_MB_TOKEN_S, token);
1704
1705 val = le32_to_cpu(tmp);
1706 writeq(in_param, hcr + 0);
1707 writeq(out_param, hcr + 2);
1708 writel(in_modifier, hcr + 4);
1709 /* Memory barrier */
1710 wmb();
1711
1712 writel(val, hcr + 5);
1713
1714 return 0;
1715 }
1716
hns_roce_v1_chk_mbox(struct hns_roce_dev * hr_dev,unsigned long timeout)1717 static int hns_roce_v1_chk_mbox(struct hns_roce_dev *hr_dev,
1718 unsigned long timeout)
1719 {
1720 u8 __iomem *hcr = hr_dev->reg_base + ROCEE_MB1_REG;
1721 unsigned long end;
1722 u32 status = 0;
1723
1724 end = msecs_to_jiffies(timeout) + jiffies;
1725 while (hns_roce_v1_cmd_pending(hr_dev) && time_before(jiffies, end))
1726 cond_resched();
1727
1728 if (hns_roce_v1_cmd_pending(hr_dev)) {
1729 dev_err(hr_dev->dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
1730 return -ETIMEDOUT;
1731 }
1732
1733 status = le32_to_cpu((__force __le32)
1734 __raw_readl(hcr + HCR_STATUS_OFFSET));
1735 if ((status & STATUS_MASK) != 0x1) {
1736 dev_err(hr_dev->dev, "mailbox status 0x%x!\n", status);
1737 return -EBUSY;
1738 }
1739
1740 return 0;
1741 }
1742
hns_roce_v1_set_gid(struct hns_roce_dev * hr_dev,u8 port,int gid_index,const union ib_gid * gid,const struct ib_gid_attr * attr)1743 static int hns_roce_v1_set_gid(struct hns_roce_dev *hr_dev, u8 port,
1744 int gid_index, const union ib_gid *gid,
1745 const struct ib_gid_attr *attr)
1746 {
1747 unsigned long flags;
1748 u32 *p = NULL;
1749 u8 gid_idx;
1750
1751 gid_idx = hns_get_gid_index(hr_dev, port, gid_index);
1752
1753 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
1754
1755 p = (u32 *)&gid->raw[0];
1756 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_L_0_REG +
1757 (HNS_ROCE_V1_GID_NUM * gid_idx));
1758
1759 p = (u32 *)&gid->raw[4];
1760 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_ML_0_REG +
1761 (HNS_ROCE_V1_GID_NUM * gid_idx));
1762
1763 p = (u32 *)&gid->raw[8];
1764 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_MH_0_REG +
1765 (HNS_ROCE_V1_GID_NUM * gid_idx));
1766
1767 p = (u32 *)&gid->raw[0xc];
1768 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_H_0_REG +
1769 (HNS_ROCE_V1_GID_NUM * gid_idx));
1770
1771 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
1772
1773 return 0;
1774 }
1775
hns_roce_v1_set_mac(struct hns_roce_dev * hr_dev,u8 phy_port,u8 * addr)1776 static int hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
1777 u8 *addr)
1778 {
1779 u32 reg_smac_l;
1780 u16 reg_smac_h;
1781 __le32 tmp;
1782 u16 *p_h;
1783 u32 *p;
1784 u32 val;
1785
1786 /*
1787 * When mac changed, loopback may fail
1788 * because of smac not equal to dmac.
1789 * We Need to release and create reserved qp again.
1790 */
1791 if (hr_dev->hw->dereg_mr) {
1792 int ret;
1793
1794 ret = hns_roce_v1_recreate_lp_qp(hr_dev);
1795 if (ret && ret != -ETIMEDOUT)
1796 return ret;
1797 }
1798
1799 p = (u32 *)(&addr[0]);
1800 reg_smac_l = *p;
1801 roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_SMAC_L_0_REG +
1802 PHY_PORT_OFFSET * phy_port);
1803
1804 val = roce_read(hr_dev,
1805 ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1806 tmp = cpu_to_le32(val);
1807 p_h = (u16 *)(&addr[4]);
1808 reg_smac_h = *p_h;
1809 roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_SMAC_H_M,
1810 ROCEE_SMAC_H_ROCEE_SMAC_H_S, reg_smac_h);
1811 val = le32_to_cpu(tmp);
1812 roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1813 val);
1814
1815 return 0;
1816 }
1817
hns_roce_v1_set_mtu(struct hns_roce_dev * hr_dev,u8 phy_port,enum ib_mtu mtu)1818 static void hns_roce_v1_set_mtu(struct hns_roce_dev *hr_dev, u8 phy_port,
1819 enum ib_mtu mtu)
1820 {
1821 __le32 tmp;
1822 u32 val;
1823
1824 val = roce_read(hr_dev,
1825 ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1826 tmp = cpu_to_le32(val);
1827 roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_PORT_MTU_M,
1828 ROCEE_SMAC_H_ROCEE_PORT_MTU_S, mtu);
1829 val = le32_to_cpu(tmp);
1830 roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1831 val);
1832 }
1833
hns_roce_v1_write_mtpt(struct hns_roce_dev * hr_dev,void * mb_buf,struct hns_roce_mr * mr,unsigned long mtpt_idx)1834 static int hns_roce_v1_write_mtpt(struct hns_roce_dev *hr_dev, void *mb_buf,
1835 struct hns_roce_mr *mr,
1836 unsigned long mtpt_idx)
1837 {
1838 u64 pages[HNS_ROCE_MAX_INNER_MTPT_NUM] = { 0 };
1839 struct ib_device *ibdev = &hr_dev->ib_dev;
1840 struct hns_roce_v1_mpt_entry *mpt_entry;
1841 dma_addr_t pbl_ba;
1842 int count;
1843 int i;
1844
1845 /* MPT filled into mailbox buf */
1846 mpt_entry = (struct hns_roce_v1_mpt_entry *)mb_buf;
1847 memset(mpt_entry, 0, sizeof(*mpt_entry));
1848
1849 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_STATE_M,
1850 MPT_BYTE_4_KEY_STATE_S, KEY_VALID);
1851 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_M,
1852 MPT_BYTE_4_KEY_S, mr->key);
1853 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_PAGE_SIZE_M,
1854 MPT_BYTE_4_PAGE_SIZE_S, MR_SIZE_4K);
1855 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_TYPE_S, 0);
1856 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_BIND_ENABLE_S,
1857 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
1858 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_OWN_S, 0);
1859 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_MEMORY_LOCATION_TYPE_M,
1860 MPT_BYTE_4_MEMORY_LOCATION_TYPE_S, mr->type);
1861 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_ATOMIC_S, 0);
1862 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_LOCAL_WRITE_S,
1863 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1864 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_WRITE_S,
1865 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1866 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_READ_S,
1867 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1868 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_INVAL_ENABLE_S,
1869 0);
1870 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_ADDRESS_TYPE_S, 0);
1871
1872 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1873 MPT_BYTE_12_PBL_ADDR_H_S, 0);
1874 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_MW_BIND_COUNTER_M,
1875 MPT_BYTE_12_MW_BIND_COUNTER_S, 0);
1876
1877 mpt_entry->virt_addr_l = cpu_to_le32((u32)mr->iova);
1878 mpt_entry->virt_addr_h = cpu_to_le32((u32)(mr->iova >> 32));
1879 mpt_entry->length = cpu_to_le32((u32)mr->size);
1880
1881 roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_PD_M,
1882 MPT_BYTE_28_PD_S, mr->pd);
1883 roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_L_KEY_IDX_L_M,
1884 MPT_BYTE_28_L_KEY_IDX_L_S, mtpt_idx);
1885 roce_set_field(mpt_entry->mpt_byte_64, MPT_BYTE_64_L_KEY_IDX_H_M,
1886 MPT_BYTE_64_L_KEY_IDX_H_S, mtpt_idx >> MTPT_IDX_SHIFT);
1887
1888 /* DMA memory register */
1889 if (mr->type == MR_TYPE_DMA)
1890 return 0;
1891
1892 count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages,
1893 ARRAY_SIZE(pages), &pbl_ba);
1894 if (count < 1) {
1895 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.", count);
1896 return -ENOBUFS;
1897 }
1898
1899 /* Register user mr */
1900 for (i = 0; i < count; i++) {
1901 switch (i) {
1902 case 0:
1903 mpt_entry->pa0_l = cpu_to_le32((u32)(pages[i]));
1904 roce_set_field(mpt_entry->mpt_byte_36,
1905 MPT_BYTE_36_PA0_H_M,
1906 MPT_BYTE_36_PA0_H_S,
1907 (u32)(pages[i] >> PAGES_SHIFT_32));
1908 break;
1909 case 1:
1910 roce_set_field(mpt_entry->mpt_byte_36,
1911 MPT_BYTE_36_PA1_L_M,
1912 MPT_BYTE_36_PA1_L_S, (u32)(pages[i]));
1913 roce_set_field(mpt_entry->mpt_byte_40,
1914 MPT_BYTE_40_PA1_H_M,
1915 MPT_BYTE_40_PA1_H_S,
1916 (u32)(pages[i] >> PAGES_SHIFT_24));
1917 break;
1918 case 2:
1919 roce_set_field(mpt_entry->mpt_byte_40,
1920 MPT_BYTE_40_PA2_L_M,
1921 MPT_BYTE_40_PA2_L_S, (u32)(pages[i]));
1922 roce_set_field(mpt_entry->mpt_byte_44,
1923 MPT_BYTE_44_PA2_H_M,
1924 MPT_BYTE_44_PA2_H_S,
1925 (u32)(pages[i] >> PAGES_SHIFT_16));
1926 break;
1927 case 3:
1928 roce_set_field(mpt_entry->mpt_byte_44,
1929 MPT_BYTE_44_PA3_L_M,
1930 MPT_BYTE_44_PA3_L_S, (u32)(pages[i]));
1931 roce_set_field(mpt_entry->mpt_byte_48,
1932 MPT_BYTE_48_PA3_H_M,
1933 MPT_BYTE_48_PA3_H_S,
1934 (u32)(pages[i] >> PAGES_SHIFT_8));
1935 break;
1936 case 4:
1937 mpt_entry->pa4_l = cpu_to_le32((u32)(pages[i]));
1938 roce_set_field(mpt_entry->mpt_byte_56,
1939 MPT_BYTE_56_PA4_H_M,
1940 MPT_BYTE_56_PA4_H_S,
1941 (u32)(pages[i] >> PAGES_SHIFT_32));
1942 break;
1943 case 5:
1944 roce_set_field(mpt_entry->mpt_byte_56,
1945 MPT_BYTE_56_PA5_L_M,
1946 MPT_BYTE_56_PA5_L_S, (u32)(pages[i]));
1947 roce_set_field(mpt_entry->mpt_byte_60,
1948 MPT_BYTE_60_PA5_H_M,
1949 MPT_BYTE_60_PA5_H_S,
1950 (u32)(pages[i] >> PAGES_SHIFT_24));
1951 break;
1952 case 6:
1953 roce_set_field(mpt_entry->mpt_byte_60,
1954 MPT_BYTE_60_PA6_L_M,
1955 MPT_BYTE_60_PA6_L_S, (u32)(pages[i]));
1956 roce_set_field(mpt_entry->mpt_byte_64,
1957 MPT_BYTE_64_PA6_H_M,
1958 MPT_BYTE_64_PA6_H_S,
1959 (u32)(pages[i] >> PAGES_SHIFT_16));
1960 break;
1961 default:
1962 break;
1963 }
1964 }
1965
1966 mpt_entry->pbl_addr_l = cpu_to_le32(pbl_ba);
1967 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1968 MPT_BYTE_12_PBL_ADDR_H_S, upper_32_bits(pbl_ba));
1969
1970 return 0;
1971 }
1972
get_cqe(struct hns_roce_cq * hr_cq,int n)1973 static void *get_cqe(struct hns_roce_cq *hr_cq, int n)
1974 {
1975 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * HNS_ROCE_V1_CQE_SIZE);
1976 }
1977
get_sw_cqe(struct hns_roce_cq * hr_cq,int n)1978 static void *get_sw_cqe(struct hns_roce_cq *hr_cq, int n)
1979 {
1980 struct hns_roce_cqe *hr_cqe = get_cqe(hr_cq, n & hr_cq->ib_cq.cqe);
1981
1982 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
1983 return (roce_get_bit(hr_cqe->cqe_byte_4, CQE_BYTE_4_OWNER_S) ^
1984 !!(n & hr_cq->cq_depth)) ? hr_cqe : NULL;
1985 }
1986
next_cqe_sw(struct hns_roce_cq * hr_cq)1987 static struct hns_roce_cqe *next_cqe_sw(struct hns_roce_cq *hr_cq)
1988 {
1989 return get_sw_cqe(hr_cq, hr_cq->cons_index);
1990 }
1991
hns_roce_v1_cq_set_ci(struct hns_roce_cq * hr_cq,u32 cons_index)1992 static void hns_roce_v1_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
1993 {
1994 __le32 doorbell[2];
1995
1996 doorbell[0] = cpu_to_le32(cons_index & ((hr_cq->cq_depth << 1) - 1));
1997 doorbell[1] = 0;
1998 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
1999 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2000 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2001 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2002 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 0);
2003 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2004 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S, hr_cq->cqn);
2005
2006 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2007 }
2008
__hns_roce_v1_cq_clean(struct hns_roce_cq * hr_cq,u32 qpn,struct hns_roce_srq * srq)2009 static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2010 struct hns_roce_srq *srq)
2011 {
2012 struct hns_roce_cqe *cqe, *dest;
2013 u32 prod_index;
2014 int nfreed = 0;
2015 u8 owner_bit;
2016
2017 for (prod_index = hr_cq->cons_index; get_sw_cqe(hr_cq, prod_index);
2018 ++prod_index) {
2019 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
2020 break;
2021 }
2022
2023 /*
2024 * Now backwards through the CQ, removing CQ entries
2025 * that match our QP by overwriting them with next entries.
2026 */
2027 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
2028 cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe);
2029 if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2030 CQE_BYTE_16_LOCAL_QPN_S) &
2031 HNS_ROCE_CQE_QPN_MASK) == qpn) {
2032 /* In v1 engine, not support SRQ */
2033 ++nfreed;
2034 } else if (nfreed) {
2035 dest = get_cqe(hr_cq, (prod_index + nfreed) &
2036 hr_cq->ib_cq.cqe);
2037 owner_bit = roce_get_bit(dest->cqe_byte_4,
2038 CQE_BYTE_4_OWNER_S);
2039 memcpy(dest, cqe, sizeof(*cqe));
2040 roce_set_bit(dest->cqe_byte_4, CQE_BYTE_4_OWNER_S,
2041 owner_bit);
2042 }
2043 }
2044
2045 if (nfreed) {
2046 hr_cq->cons_index += nfreed;
2047 /*
2048 * Make sure update of buffer contents is done before
2049 * updating consumer index.
2050 */
2051 wmb();
2052
2053 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2054 }
2055 }
2056
hns_roce_v1_cq_clean(struct hns_roce_cq * hr_cq,u32 qpn,struct hns_roce_srq * srq)2057 static void hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2058 struct hns_roce_srq *srq)
2059 {
2060 spin_lock_irq(&hr_cq->lock);
2061 __hns_roce_v1_cq_clean(hr_cq, qpn, srq);
2062 spin_unlock_irq(&hr_cq->lock);
2063 }
2064
hns_roce_v1_write_cqc(struct hns_roce_dev * hr_dev,struct hns_roce_cq * hr_cq,void * mb_buf,u64 * mtts,dma_addr_t dma_handle)2065 static void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
2066 struct hns_roce_cq *hr_cq, void *mb_buf,
2067 u64 *mtts, dma_addr_t dma_handle)
2068 {
2069 struct hns_roce_v1_priv *priv = hr_dev->priv;
2070 struct hns_roce_buf_list *tptr_buf = &priv->tptr_table.tptr_buf;
2071 struct hns_roce_cq_context *cq_context = mb_buf;
2072 dma_addr_t tptr_dma_addr;
2073 int offset;
2074
2075 memset(cq_context, 0, sizeof(*cq_context));
2076
2077 /* Get the tptr for this CQ. */
2078 offset = hr_cq->cqn * HNS_ROCE_V1_TPTR_ENTRY_SIZE;
2079 tptr_dma_addr = tptr_buf->map + offset;
2080 hr_cq->tptr_addr = (u16 *)(tptr_buf->buf + offset);
2081
2082 /* Register cq_context members */
2083 roce_set_field(cq_context->cqc_byte_4,
2084 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M,
2085 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S, CQ_STATE_VALID);
2086 roce_set_field(cq_context->cqc_byte_4, CQ_CONTEXT_CQC_BYTE_4_CQN_M,
2087 CQ_CONTEXT_CQC_BYTE_4_CQN_S, hr_cq->cqn);
2088
2089 cq_context->cq_bt_l = cpu_to_le32((u32)dma_handle);
2090
2091 roce_set_field(cq_context->cqc_byte_12,
2092 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M,
2093 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S,
2094 ((u64)dma_handle >> 32));
2095 roce_set_field(cq_context->cqc_byte_12,
2096 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M,
2097 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S,
2098 ilog2(hr_cq->cq_depth));
2099 roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CEQN_M,
2100 CQ_CONTEXT_CQC_BYTE_12_CEQN_S, hr_cq->vector);
2101
2102 cq_context->cur_cqe_ba0_l = cpu_to_le32((u32)(mtts[0]));
2103
2104 roce_set_field(cq_context->cqc_byte_20,
2105 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M,
2106 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S, (mtts[0]) >> 32);
2107 /* Dedicated hardware, directly set 0 */
2108 roce_set_field(cq_context->cqc_byte_20,
2109 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M,
2110 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S, 0);
2111 /**
2112 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
2113 * using 4K page, and shift more 32 because of
2114 * caculating the high 32 bit value evaluated to hardware.
2115 */
2116 roce_set_field(cq_context->cqc_byte_20,
2117 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M,
2118 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S,
2119 tptr_dma_addr >> 44);
2120
2121 cq_context->cqe_tptr_addr_l = cpu_to_le32((u32)(tptr_dma_addr >> 12));
2122
2123 roce_set_field(cq_context->cqc_byte_32,
2124 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M,
2125 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S, 0);
2126 roce_set_bit(cq_context->cqc_byte_32,
2127 CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S, 0);
2128 roce_set_bit(cq_context->cqc_byte_32,
2129 CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S, 0);
2130 roce_set_bit(cq_context->cqc_byte_32,
2131 CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S, 0);
2132 roce_set_bit(cq_context->cqc_byte_32,
2133 CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S,
2134 0);
2135 /* The initial value of cq's ci is 0 */
2136 roce_set_field(cq_context->cqc_byte_32,
2137 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M,
2138 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0);
2139 }
2140
hns_roce_v1_req_notify_cq(struct ib_cq * ibcq,enum ib_cq_notify_flags flags)2141 static int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq,
2142 enum ib_cq_notify_flags flags)
2143 {
2144 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2145 u32 notification_flag;
2146 __le32 doorbell[2] = {};
2147
2148 notification_flag = (flags & IB_CQ_SOLICITED_MASK) ==
2149 IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL;
2150 /*
2151 * flags = 0; Notification Flag = 1, next
2152 * flags = 1; Notification Flag = 0, solocited
2153 */
2154 doorbell[0] =
2155 cpu_to_le32(hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1));
2156 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2157 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2158 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2159 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2160 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 1);
2161 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2162 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S,
2163 hr_cq->cqn | notification_flag);
2164
2165 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2166
2167 return 0;
2168 }
2169
hns_roce_v1_poll_one(struct hns_roce_cq * hr_cq,struct hns_roce_qp ** cur_qp,struct ib_wc * wc)2170 static int hns_roce_v1_poll_one(struct hns_roce_cq *hr_cq,
2171 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2172 {
2173 int qpn;
2174 int is_send;
2175 u16 wqe_ctr;
2176 u32 status;
2177 u32 opcode;
2178 struct hns_roce_cqe *cqe;
2179 struct hns_roce_qp *hr_qp;
2180 struct hns_roce_wq *wq;
2181 struct hns_roce_wqe_ctrl_seg *sq_wqe;
2182 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2183 struct device *dev = &hr_dev->pdev->dev;
2184
2185 /* Find cqe according consumer index */
2186 cqe = next_cqe_sw(hr_cq);
2187 if (!cqe)
2188 return -EAGAIN;
2189
2190 ++hr_cq->cons_index;
2191 /* Memory barrier */
2192 rmb();
2193 /* 0->SQ, 1->RQ */
2194 is_send = !(roce_get_bit(cqe->cqe_byte_4, CQE_BYTE_4_SQ_RQ_FLAG_S));
2195
2196 /* Local_qpn in UD cqe is always 1, so it needs to compute new qpn */
2197 if (roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2198 CQE_BYTE_16_LOCAL_QPN_S) <= 1) {
2199 qpn = roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_PORT_NUM_M,
2200 CQE_BYTE_20_PORT_NUM_S) +
2201 roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2202 CQE_BYTE_16_LOCAL_QPN_S) *
2203 HNS_ROCE_MAX_PORTS;
2204 } else {
2205 qpn = roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2206 CQE_BYTE_16_LOCAL_QPN_S);
2207 }
2208
2209 if (!*cur_qp || (qpn & HNS_ROCE_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2210 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2211 if (unlikely(!hr_qp)) {
2212 dev_err(dev, "CQ %06lx with entry for unknown QPN %06x\n",
2213 hr_cq->cqn, (qpn & HNS_ROCE_CQE_QPN_MASK));
2214 return -EINVAL;
2215 }
2216
2217 *cur_qp = hr_qp;
2218 }
2219
2220 wc->qp = &(*cur_qp)->ibqp;
2221 wc->vendor_err = 0;
2222
2223 status = roce_get_field(cqe->cqe_byte_4,
2224 CQE_BYTE_4_STATUS_OF_THE_OPERATION_M,
2225 CQE_BYTE_4_STATUS_OF_THE_OPERATION_S) &
2226 HNS_ROCE_CQE_STATUS_MASK;
2227 switch (status) {
2228 case HNS_ROCE_CQE_SUCCESS:
2229 wc->status = IB_WC_SUCCESS;
2230 break;
2231 case HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR:
2232 wc->status = IB_WC_LOC_LEN_ERR;
2233 break;
2234 case HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR:
2235 wc->status = IB_WC_LOC_QP_OP_ERR;
2236 break;
2237 case HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR:
2238 wc->status = IB_WC_LOC_PROT_ERR;
2239 break;
2240 case HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR:
2241 wc->status = IB_WC_WR_FLUSH_ERR;
2242 break;
2243 case HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR:
2244 wc->status = IB_WC_MW_BIND_ERR;
2245 break;
2246 case HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR:
2247 wc->status = IB_WC_BAD_RESP_ERR;
2248 break;
2249 case HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR:
2250 wc->status = IB_WC_LOC_ACCESS_ERR;
2251 break;
2252 case HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
2253 wc->status = IB_WC_REM_INV_REQ_ERR;
2254 break;
2255 case HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR:
2256 wc->status = IB_WC_REM_ACCESS_ERR;
2257 break;
2258 case HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR:
2259 wc->status = IB_WC_REM_OP_ERR;
2260 break;
2261 case HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
2262 wc->status = IB_WC_RETRY_EXC_ERR;
2263 break;
2264 case HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
2265 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2266 break;
2267 default:
2268 wc->status = IB_WC_GENERAL_ERR;
2269 break;
2270 }
2271
2272 /* CQE status error, directly return */
2273 if (wc->status != IB_WC_SUCCESS)
2274 return 0;
2275
2276 if (is_send) {
2277 /* SQ conrespond to CQE */
2278 sq_wqe = hns_roce_get_send_wqe(*cur_qp,
2279 roce_get_field(cqe->cqe_byte_4,
2280 CQE_BYTE_4_WQE_INDEX_M,
2281 CQE_BYTE_4_WQE_INDEX_S) &
2282 ((*cur_qp)->sq.wqe_cnt-1));
2283 switch (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_OPCODE_MASK) {
2284 case HNS_ROCE_WQE_OPCODE_SEND:
2285 wc->opcode = IB_WC_SEND;
2286 break;
2287 case HNS_ROCE_WQE_OPCODE_RDMA_READ:
2288 wc->opcode = IB_WC_RDMA_READ;
2289 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2290 break;
2291 case HNS_ROCE_WQE_OPCODE_RDMA_WRITE:
2292 wc->opcode = IB_WC_RDMA_WRITE;
2293 break;
2294 case HNS_ROCE_WQE_OPCODE_LOCAL_INV:
2295 wc->opcode = IB_WC_LOCAL_INV;
2296 break;
2297 case HNS_ROCE_WQE_OPCODE_UD_SEND:
2298 wc->opcode = IB_WC_SEND;
2299 break;
2300 default:
2301 wc->status = IB_WC_GENERAL_ERR;
2302 break;
2303 }
2304 wc->wc_flags = (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_IMM ?
2305 IB_WC_WITH_IMM : 0);
2306
2307 wq = &(*cur_qp)->sq;
2308 if ((*cur_qp)->sq_signal_bits) {
2309 /*
2310 * If sg_signal_bit is 1,
2311 * firstly tail pointer updated to wqe
2312 * which current cqe correspond to
2313 */
2314 wqe_ctr = (u16)roce_get_field(cqe->cqe_byte_4,
2315 CQE_BYTE_4_WQE_INDEX_M,
2316 CQE_BYTE_4_WQE_INDEX_S);
2317 wq->tail += (wqe_ctr - (u16)wq->tail) &
2318 (wq->wqe_cnt - 1);
2319 }
2320 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2321 ++wq->tail;
2322 } else {
2323 /* RQ conrespond to CQE */
2324 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2325 opcode = roce_get_field(cqe->cqe_byte_4,
2326 CQE_BYTE_4_OPERATION_TYPE_M,
2327 CQE_BYTE_4_OPERATION_TYPE_S) &
2328 HNS_ROCE_CQE_OPCODE_MASK;
2329 switch (opcode) {
2330 case HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE:
2331 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2332 wc->wc_flags = IB_WC_WITH_IMM;
2333 wc->ex.imm_data =
2334 cpu_to_be32(le32_to_cpu(cqe->immediate_data));
2335 break;
2336 case HNS_ROCE_OPCODE_SEND_DATA_RECEIVE:
2337 if (roce_get_bit(cqe->cqe_byte_4,
2338 CQE_BYTE_4_IMM_INDICATOR_S)) {
2339 wc->opcode = IB_WC_RECV;
2340 wc->wc_flags = IB_WC_WITH_IMM;
2341 wc->ex.imm_data = cpu_to_be32(
2342 le32_to_cpu(cqe->immediate_data));
2343 } else {
2344 wc->opcode = IB_WC_RECV;
2345 wc->wc_flags = 0;
2346 }
2347 break;
2348 default:
2349 wc->status = IB_WC_GENERAL_ERR;
2350 break;
2351 }
2352
2353 /* Update tail pointer, record wr_id */
2354 wq = &(*cur_qp)->rq;
2355 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2356 ++wq->tail;
2357 wc->sl = (u8)roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_SL_M,
2358 CQE_BYTE_20_SL_S);
2359 wc->src_qp = (u8)roce_get_field(cqe->cqe_byte_20,
2360 CQE_BYTE_20_REMOTE_QPN_M,
2361 CQE_BYTE_20_REMOTE_QPN_S);
2362 wc->wc_flags |= (roce_get_bit(cqe->cqe_byte_20,
2363 CQE_BYTE_20_GRH_PRESENT_S) ?
2364 IB_WC_GRH : 0);
2365 wc->pkey_index = (u16)roce_get_field(cqe->cqe_byte_28,
2366 CQE_BYTE_28_P_KEY_IDX_M,
2367 CQE_BYTE_28_P_KEY_IDX_S);
2368 }
2369
2370 return 0;
2371 }
2372
hns_roce_v1_poll_cq(struct ib_cq * ibcq,int num_entries,struct ib_wc * wc)2373 int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
2374 {
2375 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2376 struct hns_roce_qp *cur_qp = NULL;
2377 unsigned long flags;
2378 int npolled;
2379 int ret = 0;
2380
2381 spin_lock_irqsave(&hr_cq->lock, flags);
2382
2383 for (npolled = 0; npolled < num_entries; ++npolled) {
2384 ret = hns_roce_v1_poll_one(hr_cq, &cur_qp, wc + npolled);
2385 if (ret)
2386 break;
2387 }
2388
2389 if (npolled) {
2390 *hr_cq->tptr_addr = hr_cq->cons_index &
2391 ((hr_cq->cq_depth << 1) - 1);
2392
2393 /* Memroy barrier */
2394 wmb();
2395 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2396 }
2397
2398 spin_unlock_irqrestore(&hr_cq->lock, flags);
2399
2400 if (ret == 0 || ret == -EAGAIN)
2401 return npolled;
2402 else
2403 return ret;
2404 }
2405
hns_roce_v1_clear_hem(struct hns_roce_dev * hr_dev,struct hns_roce_hem_table * table,int obj,int step_idx)2406 static int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
2407 struct hns_roce_hem_table *table, int obj,
2408 int step_idx)
2409 {
2410 struct hns_roce_v1_priv *priv = hr_dev->priv;
2411 struct device *dev = &hr_dev->pdev->dev;
2412 long end = HW_SYNC_TIMEOUT_MSECS;
2413 __le32 bt_cmd_val[2] = {0};
2414 unsigned long flags = 0;
2415 void __iomem *bt_cmd;
2416 u64 bt_ba = 0;
2417
2418 switch (table->type) {
2419 case HEM_TYPE_QPC:
2420 bt_ba = priv->bt_table.qpc_buf.map >> 12;
2421 break;
2422 case HEM_TYPE_MTPT:
2423 bt_ba = priv->bt_table.mtpt_buf.map >> 12;
2424 break;
2425 case HEM_TYPE_CQC:
2426 bt_ba = priv->bt_table.cqc_buf.map >> 12;
2427 break;
2428 case HEM_TYPE_SRQC:
2429 dev_dbg(dev, "HEM_TYPE_SRQC not support.\n");
2430 return -EINVAL;
2431 default:
2432 return 0;
2433 }
2434 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2435 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, table->type);
2436 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
2437 ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
2438 roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
2439 roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
2440
2441 spin_lock_irqsave(&hr_dev->bt_cmd_lock, flags);
2442
2443 bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
2444
2445 while (1) {
2446 if (readl(bt_cmd) >> BT_CMD_SYNC_SHIFT) {
2447 if (!end) {
2448 dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
2449 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock,
2450 flags);
2451 return -EBUSY;
2452 }
2453 } else {
2454 break;
2455 }
2456 mdelay(HW_SYNC_SLEEP_TIME_INTERVAL);
2457 end -= HW_SYNC_SLEEP_TIME_INTERVAL;
2458 }
2459
2460 bt_cmd_val[0] = cpu_to_le32(bt_ba);
2461 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
2462 ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S, bt_ba >> 32);
2463 hns_roce_write64_k(bt_cmd_val, hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
2464
2465 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock, flags);
2466
2467 return 0;
2468 }
2469
hns_roce_v1_qp_modify(struct hns_roce_dev * hr_dev,enum hns_roce_qp_state cur_state,enum hns_roce_qp_state new_state,struct hns_roce_qp_context * context,struct hns_roce_qp * hr_qp)2470 static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev,
2471 enum hns_roce_qp_state cur_state,
2472 enum hns_roce_qp_state new_state,
2473 struct hns_roce_qp_context *context,
2474 struct hns_roce_qp *hr_qp)
2475 {
2476 static const u16
2477 op[HNS_ROCE_QP_NUM_STATE][HNS_ROCE_QP_NUM_STATE] = {
2478 [HNS_ROCE_QP_STATE_RST] = {
2479 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2480 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2481 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2482 },
2483 [HNS_ROCE_QP_STATE_INIT] = {
2484 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2485 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2486 /* Note: In v1 engine, HW doesn't support RST2INIT.
2487 * We use RST2INIT cmd instead of INIT2INIT.
2488 */
2489 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2490 [HNS_ROCE_QP_STATE_RTR] = HNS_ROCE_CMD_INIT2RTR_QP,
2491 },
2492 [HNS_ROCE_QP_STATE_RTR] = {
2493 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2494 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2495 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTR2RTS_QP,
2496 },
2497 [HNS_ROCE_QP_STATE_RTS] = {
2498 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2499 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2500 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTS2RTS_QP,
2501 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_RTS2SQD_QP,
2502 },
2503 [HNS_ROCE_QP_STATE_SQD] = {
2504 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2505 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2506 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_SQD2RTS_QP,
2507 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_SQD2SQD_QP,
2508 },
2509 [HNS_ROCE_QP_STATE_ERR] = {
2510 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2511 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2512 }
2513 };
2514
2515 struct hns_roce_cmd_mailbox *mailbox;
2516 struct device *dev = &hr_dev->pdev->dev;
2517 int ret;
2518
2519 if (cur_state >= HNS_ROCE_QP_NUM_STATE ||
2520 new_state >= HNS_ROCE_QP_NUM_STATE ||
2521 !op[cur_state][new_state]) {
2522 dev_err(dev, "[modify_qp]not support state %d to %d\n",
2523 cur_state, new_state);
2524 return -EINVAL;
2525 }
2526
2527 if (op[cur_state][new_state] == HNS_ROCE_CMD_2RST_QP)
2528 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2529 HNS_ROCE_CMD_2RST_QP,
2530 HNS_ROCE_CMD_TIMEOUT_MSECS);
2531
2532 if (op[cur_state][new_state] == HNS_ROCE_CMD_2ERR_QP)
2533 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2534 HNS_ROCE_CMD_2ERR_QP,
2535 HNS_ROCE_CMD_TIMEOUT_MSECS);
2536
2537 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2538 if (IS_ERR(mailbox))
2539 return PTR_ERR(mailbox);
2540
2541 memcpy(mailbox->buf, context, sizeof(*context));
2542
2543 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
2544 op[cur_state][new_state],
2545 HNS_ROCE_CMD_TIMEOUT_MSECS);
2546
2547 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2548 return ret;
2549 }
2550
find_wqe_mtt(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,u64 * sq_ba,u64 * rq_ba,dma_addr_t * bt_ba)2551 static int find_wqe_mtt(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
2552 u64 *sq_ba, u64 *rq_ba, dma_addr_t *bt_ba)
2553 {
2554 struct ib_device *ibdev = &hr_dev->ib_dev;
2555 int count;
2556
2557 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, sq_ba, 1, bt_ba);
2558 if (count < 1) {
2559 ibdev_err(ibdev, "Failed to find SQ ba\n");
2560 return -ENOBUFS;
2561 }
2562
2563 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, rq_ba,
2564 1, NULL);
2565 if (!count) {
2566 ibdev_err(ibdev, "Failed to find RQ ba\n");
2567 return -ENOBUFS;
2568 }
2569
2570 return 0;
2571 }
2572
hns_roce_v1_m_sqp(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state)2573 static int hns_roce_v1_m_sqp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2574 int attr_mask, enum ib_qp_state cur_state,
2575 enum ib_qp_state new_state)
2576 {
2577 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2578 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2579 struct hns_roce_sqp_context *context;
2580 dma_addr_t dma_handle = 0;
2581 u32 __iomem *addr;
2582 u64 sq_ba = 0;
2583 u64 rq_ba = 0;
2584 __le32 tmp;
2585 u32 reg_val;
2586
2587 context = kzalloc(sizeof(*context), GFP_KERNEL);
2588 if (!context)
2589 return -ENOMEM;
2590
2591 /* Search QP buf's MTTs */
2592 if (find_wqe_mtt(hr_dev, hr_qp, &sq_ba, &rq_ba, &dma_handle))
2593 goto out;
2594
2595 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2596 roce_set_field(context->qp1c_bytes_4,
2597 QP1C_BYTES_4_SQ_WQE_SHIFT_M,
2598 QP1C_BYTES_4_SQ_WQE_SHIFT_S,
2599 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2600 roce_set_field(context->qp1c_bytes_4,
2601 QP1C_BYTES_4_RQ_WQE_SHIFT_M,
2602 QP1C_BYTES_4_RQ_WQE_SHIFT_S,
2603 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2604 roce_set_field(context->qp1c_bytes_4, QP1C_BYTES_4_PD_M,
2605 QP1C_BYTES_4_PD_S, to_hr_pd(ibqp->pd)->pdn);
2606
2607 context->sq_rq_bt_l = cpu_to_le32(dma_handle);
2608 roce_set_field(context->qp1c_bytes_12,
2609 QP1C_BYTES_12_SQ_RQ_BT_H_M,
2610 QP1C_BYTES_12_SQ_RQ_BT_H_S,
2611 upper_32_bits(dma_handle));
2612
2613 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_HEAD_M,
2614 QP1C_BYTES_16_RQ_HEAD_S, hr_qp->rq.head);
2615 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_PORT_NUM_M,
2616 QP1C_BYTES_16_PORT_NUM_S, hr_qp->phy_port);
2617 roce_set_bit(context->qp1c_bytes_16,
2618 QP1C_BYTES_16_SIGNALING_TYPE_S,
2619 hr_qp->sq_signal_bits);
2620 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_BA_FLG_S,
2621 1);
2622 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_SQ_BA_FLG_S,
2623 1);
2624 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_QP1_ERR_S,
2625 0);
2626
2627 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_SQ_HEAD_M,
2628 QP1C_BYTES_20_SQ_HEAD_S, hr_qp->sq.head);
2629 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_PKEY_IDX_M,
2630 QP1C_BYTES_20_PKEY_IDX_S, attr->pkey_index);
2631
2632 context->cur_rq_wqe_ba_l = cpu_to_le32(rq_ba);
2633
2634 roce_set_field(context->qp1c_bytes_28,
2635 QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M,
2636 QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S,
2637 upper_32_bits(rq_ba));
2638 roce_set_field(context->qp1c_bytes_28,
2639 QP1C_BYTES_28_RQ_CUR_IDX_M,
2640 QP1C_BYTES_28_RQ_CUR_IDX_S, 0);
2641
2642 roce_set_field(context->qp1c_bytes_32,
2643 QP1C_BYTES_32_RX_CQ_NUM_M,
2644 QP1C_BYTES_32_RX_CQ_NUM_S,
2645 to_hr_cq(ibqp->recv_cq)->cqn);
2646 roce_set_field(context->qp1c_bytes_32,
2647 QP1C_BYTES_32_TX_CQ_NUM_M,
2648 QP1C_BYTES_32_TX_CQ_NUM_S,
2649 to_hr_cq(ibqp->send_cq)->cqn);
2650
2651 context->cur_sq_wqe_ba_l = cpu_to_le32(sq_ba);
2652
2653 roce_set_field(context->qp1c_bytes_40,
2654 QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M,
2655 QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S,
2656 upper_32_bits(sq_ba));
2657 roce_set_field(context->qp1c_bytes_40,
2658 QP1C_BYTES_40_SQ_CUR_IDX_M,
2659 QP1C_BYTES_40_SQ_CUR_IDX_S, 0);
2660
2661 /* Copy context to QP1C register */
2662 addr = (u32 __iomem *)(hr_dev->reg_base +
2663 ROCEE_QP1C_CFG0_0_REG +
2664 hr_qp->phy_port * sizeof(*context));
2665
2666 writel(le32_to_cpu(context->qp1c_bytes_4), addr);
2667 writel(le32_to_cpu(context->sq_rq_bt_l), addr + 1);
2668 writel(le32_to_cpu(context->qp1c_bytes_12), addr + 2);
2669 writel(le32_to_cpu(context->qp1c_bytes_16), addr + 3);
2670 writel(le32_to_cpu(context->qp1c_bytes_20), addr + 4);
2671 writel(le32_to_cpu(context->cur_rq_wqe_ba_l), addr + 5);
2672 writel(le32_to_cpu(context->qp1c_bytes_28), addr + 6);
2673 writel(le32_to_cpu(context->qp1c_bytes_32), addr + 7);
2674 writel(le32_to_cpu(context->cur_sq_wqe_ba_l), addr + 8);
2675 writel(le32_to_cpu(context->qp1c_bytes_40), addr + 9);
2676 }
2677
2678 /* Modify QP1C status */
2679 reg_val = roce_read(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2680 hr_qp->phy_port * sizeof(*context));
2681 tmp = cpu_to_le32(reg_val);
2682 roce_set_field(tmp, ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M,
2683 ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S, new_state);
2684 reg_val = le32_to_cpu(tmp);
2685 roce_write(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2686 hr_qp->phy_port * sizeof(*context), reg_val);
2687
2688 hr_qp->state = new_state;
2689 if (new_state == IB_QPS_RESET) {
2690 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
2691 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
2692 if (ibqp->send_cq != ibqp->recv_cq)
2693 hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
2694 hr_qp->qpn, NULL);
2695
2696 hr_qp->rq.head = 0;
2697 hr_qp->rq.tail = 0;
2698 hr_qp->sq.head = 0;
2699 hr_qp->sq.tail = 0;
2700 }
2701
2702 kfree(context);
2703 return 0;
2704
2705 out:
2706 kfree(context);
2707 return -EINVAL;
2708 }
2709
check_qp_state(enum ib_qp_state cur_state,enum ib_qp_state new_state)2710 static bool check_qp_state(enum ib_qp_state cur_state,
2711 enum ib_qp_state new_state)
2712 {
2713 static const bool sm[][IB_QPS_ERR + 1] = {
2714 [IB_QPS_RESET] = { [IB_QPS_RESET] = true,
2715 [IB_QPS_INIT] = true },
2716 [IB_QPS_INIT] = { [IB_QPS_RESET] = true,
2717 [IB_QPS_INIT] = true,
2718 [IB_QPS_RTR] = true,
2719 [IB_QPS_ERR] = true },
2720 [IB_QPS_RTR] = { [IB_QPS_RESET] = true,
2721 [IB_QPS_RTS] = true,
2722 [IB_QPS_ERR] = true },
2723 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true },
2724 [IB_QPS_SQD] = {},
2725 [IB_QPS_SQE] = {},
2726 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true }
2727 };
2728
2729 return sm[cur_state][new_state];
2730 }
2731
hns_roce_v1_m_qp(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state)2732 static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2733 int attr_mask, enum ib_qp_state cur_state,
2734 enum ib_qp_state new_state)
2735 {
2736 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2737 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2738 struct device *dev = &hr_dev->pdev->dev;
2739 struct hns_roce_qp_context *context;
2740 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
2741 dma_addr_t dma_handle_2 = 0;
2742 dma_addr_t dma_handle = 0;
2743 __le32 doorbell[2] = {0};
2744 u64 *mtts_2 = NULL;
2745 int ret = -EINVAL;
2746 u64 sq_ba = 0;
2747 u64 rq_ba = 0;
2748 int port;
2749 u8 port_num;
2750 u8 *dmac;
2751 u8 *smac;
2752
2753 if (!check_qp_state(cur_state, new_state)) {
2754 ibdev_err(ibqp->device,
2755 "not support QP(%u) status from %d to %d\n",
2756 ibqp->qp_num, cur_state, new_state);
2757 return -EINVAL;
2758 }
2759
2760 context = kzalloc(sizeof(*context), GFP_KERNEL);
2761 if (!context)
2762 return -ENOMEM;
2763
2764 /* Search qp buf's mtts */
2765 if (find_wqe_mtt(hr_dev, hr_qp, &sq_ba, &rq_ba, &dma_handle))
2766 goto out;
2767
2768 /* Search IRRL's mtts */
2769 mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
2770 hr_qp->qpn, &dma_handle_2);
2771 if (mtts_2 == NULL) {
2772 dev_err(dev, "qp irrl_table find failed\n");
2773 goto out;
2774 }
2775
2776 /*
2777 * Reset to init
2778 * Mandatory param:
2779 * IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS
2780 * Optional param: NA
2781 */
2782 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2783 roce_set_field(context->qpc_bytes_4,
2784 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2785 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2786 to_hr_qp_type(hr_qp->ibqp.qp_type));
2787
2788 roce_set_bit(context->qpc_bytes_4,
2789 QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2790 roce_set_bit(context->qpc_bytes_4,
2791 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2792 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
2793 roce_set_bit(context->qpc_bytes_4,
2794 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2795 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
2796 );
2797 roce_set_bit(context->qpc_bytes_4,
2798 QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S,
2799 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC)
2800 );
2801 roce_set_bit(context->qpc_bytes_4,
2802 QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2803 roce_set_field(context->qpc_bytes_4,
2804 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2805 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2806 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2807 roce_set_field(context->qpc_bytes_4,
2808 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2809 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2810 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2811 roce_set_field(context->qpc_bytes_4,
2812 QP_CONTEXT_QPC_BYTES_4_PD_M,
2813 QP_CONTEXT_QPC_BYTES_4_PD_S,
2814 to_hr_pd(ibqp->pd)->pdn);
2815 hr_qp->access_flags = attr->qp_access_flags;
2816 roce_set_field(context->qpc_bytes_8,
2817 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2818 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2819 to_hr_cq(ibqp->send_cq)->cqn);
2820 roce_set_field(context->qpc_bytes_8,
2821 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2822 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2823 to_hr_cq(ibqp->recv_cq)->cqn);
2824
2825 if (ibqp->srq)
2826 roce_set_field(context->qpc_bytes_12,
2827 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2828 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2829 to_hr_srq(ibqp->srq)->srqn);
2830
2831 roce_set_field(context->qpc_bytes_12,
2832 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2833 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2834 attr->pkey_index);
2835 hr_qp->pkey_index = attr->pkey_index;
2836 roce_set_field(context->qpc_bytes_16,
2837 QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2838 QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2839 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
2840 roce_set_field(context->qpc_bytes_4,
2841 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2842 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2843 to_hr_qp_type(hr_qp->ibqp.qp_type));
2844 roce_set_bit(context->qpc_bytes_4,
2845 QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2846 if (attr_mask & IB_QP_ACCESS_FLAGS) {
2847 roce_set_bit(context->qpc_bytes_4,
2848 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2849 !!(attr->qp_access_flags &
2850 IB_ACCESS_REMOTE_READ));
2851 roce_set_bit(context->qpc_bytes_4,
2852 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2853 !!(attr->qp_access_flags &
2854 IB_ACCESS_REMOTE_WRITE));
2855 } else {
2856 roce_set_bit(context->qpc_bytes_4,
2857 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2858 !!(hr_qp->access_flags &
2859 IB_ACCESS_REMOTE_READ));
2860 roce_set_bit(context->qpc_bytes_4,
2861 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2862 !!(hr_qp->access_flags &
2863 IB_ACCESS_REMOTE_WRITE));
2864 }
2865
2866 roce_set_bit(context->qpc_bytes_4,
2867 QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2868 roce_set_field(context->qpc_bytes_4,
2869 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2870 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2871 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2872 roce_set_field(context->qpc_bytes_4,
2873 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2874 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2875 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2876 roce_set_field(context->qpc_bytes_4,
2877 QP_CONTEXT_QPC_BYTES_4_PD_M,
2878 QP_CONTEXT_QPC_BYTES_4_PD_S,
2879 to_hr_pd(ibqp->pd)->pdn);
2880
2881 roce_set_field(context->qpc_bytes_8,
2882 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2883 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2884 to_hr_cq(ibqp->send_cq)->cqn);
2885 roce_set_field(context->qpc_bytes_8,
2886 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2887 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2888 to_hr_cq(ibqp->recv_cq)->cqn);
2889
2890 if (ibqp->srq)
2891 roce_set_field(context->qpc_bytes_12,
2892 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2893 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2894 to_hr_srq(ibqp->srq)->srqn);
2895 if (attr_mask & IB_QP_PKEY_INDEX)
2896 roce_set_field(context->qpc_bytes_12,
2897 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2898 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2899 attr->pkey_index);
2900 else
2901 roce_set_field(context->qpc_bytes_12,
2902 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2903 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2904 hr_qp->pkey_index);
2905
2906 roce_set_field(context->qpc_bytes_16,
2907 QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2908 QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2909 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2910 if ((attr_mask & IB_QP_ALT_PATH) ||
2911 (attr_mask & IB_QP_ACCESS_FLAGS) ||
2912 (attr_mask & IB_QP_PKEY_INDEX) ||
2913 (attr_mask & IB_QP_QKEY)) {
2914 dev_err(dev, "INIT2RTR attr_mask error\n");
2915 goto out;
2916 }
2917
2918 dmac = (u8 *)attr->ah_attr.roce.dmac;
2919
2920 context->sq_rq_bt_l = cpu_to_le32(dma_handle);
2921 roce_set_field(context->qpc_bytes_24,
2922 QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M,
2923 QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S,
2924 upper_32_bits(dma_handle));
2925 roce_set_bit(context->qpc_bytes_24,
2926 QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S,
2927 1);
2928 roce_set_field(context->qpc_bytes_24,
2929 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
2930 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S,
2931 attr->min_rnr_timer);
2932 context->irrl_ba_l = cpu_to_le32((u32)(dma_handle_2));
2933 roce_set_field(context->qpc_bytes_32,
2934 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M,
2935 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S,
2936 ((u32)(dma_handle_2 >> 32)) &
2937 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M);
2938 roce_set_field(context->qpc_bytes_32,
2939 QP_CONTEXT_QPC_BYTES_32_MIG_STATE_M,
2940 QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S, 0);
2941 roce_set_bit(context->qpc_bytes_32,
2942 QP_CONTEXT_QPC_BYTE_32_LOCAL_ENABLE_E2E_CREDITS_S,
2943 1);
2944 roce_set_bit(context->qpc_bytes_32,
2945 QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S,
2946 hr_qp->sq_signal_bits);
2947
2948 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) :
2949 hr_qp->port;
2950 smac = (u8 *)hr_dev->dev_addr[port];
2951 /* when dmac equals smac or loop_idc is 1, it should loopback */
2952 if (ether_addr_equal_unaligned(dmac, smac) ||
2953 hr_dev->loop_idc == 0x1)
2954 roce_set_bit(context->qpc_bytes_32,
2955 QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S, 1);
2956
2957 roce_set_bit(context->qpc_bytes_32,
2958 QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S,
2959 rdma_ah_get_ah_flags(&attr->ah_attr));
2960 roce_set_field(context->qpc_bytes_32,
2961 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
2962 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S,
2963 ilog2((unsigned int)attr->max_dest_rd_atomic));
2964
2965 if (attr_mask & IB_QP_DEST_QPN)
2966 roce_set_field(context->qpc_bytes_36,
2967 QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
2968 QP_CONTEXT_QPC_BYTES_36_DEST_QP_S,
2969 attr->dest_qp_num);
2970
2971 /* Configure GID index */
2972 port_num = rdma_ah_get_port_num(&attr->ah_attr);
2973 roce_set_field(context->qpc_bytes_36,
2974 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
2975 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S,
2976 hns_get_gid_index(hr_dev,
2977 port_num - 1,
2978 grh->sgid_index));
2979
2980 memcpy(&(context->dmac_l), dmac, 4);
2981
2982 roce_set_field(context->qpc_bytes_44,
2983 QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2984 QP_CONTEXT_QPC_BYTES_44_DMAC_H_S,
2985 *((u16 *)(&dmac[4])));
2986 roce_set_field(context->qpc_bytes_44,
2987 QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_M,
2988 QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S,
2989 rdma_ah_get_static_rate(&attr->ah_attr));
2990 roce_set_field(context->qpc_bytes_44,
2991 QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
2992 QP_CONTEXT_QPC_BYTES_44_HOPLMT_S,
2993 grh->hop_limit);
2994
2995 roce_set_field(context->qpc_bytes_48,
2996 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
2997 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S,
2998 grh->flow_label);
2999 roce_set_field(context->qpc_bytes_48,
3000 QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3001 QP_CONTEXT_QPC_BYTES_48_TCLASS_S,
3002 grh->traffic_class);
3003 roce_set_field(context->qpc_bytes_48,
3004 QP_CONTEXT_QPC_BYTES_48_MTU_M,
3005 QP_CONTEXT_QPC_BYTES_48_MTU_S, attr->path_mtu);
3006
3007 memcpy(context->dgid, grh->dgid.raw,
3008 sizeof(grh->dgid.raw));
3009
3010 dev_dbg(dev, "dmac:%x :%lx\n", context->dmac_l,
3011 roce_get_field(context->qpc_bytes_44,
3012 QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
3013 QP_CONTEXT_QPC_BYTES_44_DMAC_H_S));
3014
3015 roce_set_field(context->qpc_bytes_68,
3016 QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_M,
3017 QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S,
3018 hr_qp->rq.head);
3019 roce_set_field(context->qpc_bytes_68,
3020 QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M,
3021 QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S, 0);
3022
3023 context->cur_rq_wqe_ba_l = cpu_to_le32(rq_ba);
3024
3025 roce_set_field(context->qpc_bytes_76,
3026 QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M,
3027 QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S,
3028 upper_32_bits(rq_ba));
3029 roce_set_field(context->qpc_bytes_76,
3030 QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M,
3031 QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S, 0);
3032
3033 context->rx_rnr_time = 0;
3034
3035 roce_set_field(context->qpc_bytes_84,
3036 QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_M,
3037 QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S,
3038 attr->rq_psn - 1);
3039 roce_set_field(context->qpc_bytes_84,
3040 QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_M,
3041 QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S, 0);
3042
3043 roce_set_field(context->qpc_bytes_88,
3044 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3045 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S,
3046 attr->rq_psn);
3047 roce_set_bit(context->qpc_bytes_88,
3048 QP_CONTEXT_QPC_BYTES_88_RX_REQ_PSN_ERR_FLAG_S, 0);
3049 roce_set_bit(context->qpc_bytes_88,
3050 QP_CONTEXT_QPC_BYTES_88_RX_LAST_OPCODE_FLG_S, 0);
3051 roce_set_field(context->qpc_bytes_88,
3052 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_M,
3053 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S,
3054 0);
3055 roce_set_field(context->qpc_bytes_88,
3056 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_M,
3057 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S,
3058 0);
3059
3060 context->dma_length = 0;
3061 context->r_key = 0;
3062 context->va_l = 0;
3063 context->va_h = 0;
3064
3065 roce_set_field(context->qpc_bytes_108,
3066 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_M,
3067 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S, 0);
3068 roce_set_bit(context->qpc_bytes_108,
3069 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_FLG_S, 0);
3070 roce_set_bit(context->qpc_bytes_108,
3071 QP_CONTEXT_QPC_BYTES_108_TRRL_TDB_PSN_FLG_S, 0);
3072
3073 roce_set_field(context->qpc_bytes_112,
3074 QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_M,
3075 QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S, 0);
3076 roce_set_field(context->qpc_bytes_112,
3077 QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_M,
3078 QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S, 0);
3079
3080 /* For chip resp ack */
3081 roce_set_field(context->qpc_bytes_156,
3082 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3083 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3084 hr_qp->phy_port);
3085 roce_set_field(context->qpc_bytes_156,
3086 QP_CONTEXT_QPC_BYTES_156_SL_M,
3087 QP_CONTEXT_QPC_BYTES_156_SL_S,
3088 rdma_ah_get_sl(&attr->ah_attr));
3089 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3090 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3091 /* If exist optional param, return error */
3092 if ((attr_mask & IB_QP_ALT_PATH) ||
3093 (attr_mask & IB_QP_ACCESS_FLAGS) ||
3094 (attr_mask & IB_QP_QKEY) ||
3095 (attr_mask & IB_QP_PATH_MIG_STATE) ||
3096 (attr_mask & IB_QP_CUR_STATE) ||
3097 (attr_mask & IB_QP_MIN_RNR_TIMER)) {
3098 dev_err(dev, "RTR2RTS attr_mask error\n");
3099 goto out;
3100 }
3101
3102 context->rx_cur_sq_wqe_ba_l = cpu_to_le32(sq_ba);
3103
3104 roce_set_field(context->qpc_bytes_120,
3105 QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M,
3106 QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S,
3107 upper_32_bits(sq_ba));
3108
3109 roce_set_field(context->qpc_bytes_124,
3110 QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M,
3111 QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S, 0);
3112 roce_set_field(context->qpc_bytes_124,
3113 QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_M,
3114 QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S, 0);
3115
3116 roce_set_field(context->qpc_bytes_128,
3117 QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_M,
3118 QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S,
3119 attr->sq_psn);
3120 roce_set_bit(context->qpc_bytes_128,
3121 QP_CONTEXT_QPC_BYTES_128_RX_ACK_PSN_ERR_FLG_S, 0);
3122 roce_set_field(context->qpc_bytes_128,
3123 QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_M,
3124 QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S,
3125 0);
3126 roce_set_bit(context->qpc_bytes_128,
3127 QP_CONTEXT_QPC_BYTES_128_IRRL_PSN_VLD_FLG_S, 0);
3128
3129 roce_set_field(context->qpc_bytes_132,
3130 QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_M,
3131 QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S, 0);
3132 roce_set_field(context->qpc_bytes_132,
3133 QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_M,
3134 QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S, 0);
3135
3136 roce_set_field(context->qpc_bytes_136,
3137 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_M,
3138 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S,
3139 attr->sq_psn);
3140 roce_set_field(context->qpc_bytes_136,
3141 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_M,
3142 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S,
3143 attr->sq_psn);
3144
3145 roce_set_field(context->qpc_bytes_140,
3146 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_M,
3147 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S,
3148 (attr->sq_psn >> SQ_PSN_SHIFT));
3149 roce_set_field(context->qpc_bytes_140,
3150 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_M,
3151 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S, 0);
3152 roce_set_bit(context->qpc_bytes_140,
3153 QP_CONTEXT_QPC_BYTES_140_RNR_RETRY_FLG_S, 0);
3154
3155 roce_set_field(context->qpc_bytes_148,
3156 QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_M,
3157 QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S, 0);
3158 roce_set_field(context->qpc_bytes_148,
3159 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3160 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S,
3161 attr->retry_cnt);
3162 roce_set_field(context->qpc_bytes_148,
3163 QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_M,
3164 QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S,
3165 attr->rnr_retry);
3166 roce_set_field(context->qpc_bytes_148,
3167 QP_CONTEXT_QPC_BYTES_148_LSN_M,
3168 QP_CONTEXT_QPC_BYTES_148_LSN_S, 0x100);
3169
3170 context->rnr_retry = 0;
3171
3172 roce_set_field(context->qpc_bytes_156,
3173 QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_M,
3174 QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S,
3175 attr->retry_cnt);
3176 if (attr->timeout < 0x12) {
3177 dev_info(dev, "ack timeout value(0x%x) must bigger than 0x12.\n",
3178 attr->timeout);
3179 roce_set_field(context->qpc_bytes_156,
3180 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3181 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3182 0x12);
3183 } else {
3184 roce_set_field(context->qpc_bytes_156,
3185 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3186 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3187 attr->timeout);
3188 }
3189 roce_set_field(context->qpc_bytes_156,
3190 QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_M,
3191 QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S,
3192 attr->rnr_retry);
3193 roce_set_field(context->qpc_bytes_156,
3194 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3195 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3196 hr_qp->phy_port);
3197 roce_set_field(context->qpc_bytes_156,
3198 QP_CONTEXT_QPC_BYTES_156_SL_M,
3199 QP_CONTEXT_QPC_BYTES_156_SL_S,
3200 rdma_ah_get_sl(&attr->ah_attr));
3201 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3202 roce_set_field(context->qpc_bytes_156,
3203 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3204 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S,
3205 ilog2((unsigned int)attr->max_rd_atomic));
3206 roce_set_field(context->qpc_bytes_156,
3207 QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_M,
3208 QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S, 0);
3209 context->pkt_use_len = 0;
3210
3211 roce_set_field(context->qpc_bytes_164,
3212 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3213 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S, attr->sq_psn);
3214 roce_set_field(context->qpc_bytes_164,
3215 QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_M,
3216 QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S, 0);
3217
3218 roce_set_field(context->qpc_bytes_168,
3219 QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_M,
3220 QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S,
3221 attr->sq_psn);
3222 roce_set_field(context->qpc_bytes_168,
3223 QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_M,
3224 QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S, 0);
3225 roce_set_field(context->qpc_bytes_168,
3226 QP_CONTEXT_QPC_BYTES_168_DB_TYPE_M,
3227 QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S, 0);
3228 roce_set_bit(context->qpc_bytes_168,
3229 QP_CONTEXT_QPC_BYTES_168_MSG_LP_IND_S, 0);
3230 roce_set_bit(context->qpc_bytes_168,
3231 QP_CONTEXT_QPC_BYTES_168_CSDB_LP_IND_S, 0);
3232 roce_set_bit(context->qpc_bytes_168,
3233 QP_CONTEXT_QPC_BYTES_168_QP_ERR_FLG_S, 0);
3234 context->sge_use_len = 0;
3235
3236 roce_set_field(context->qpc_bytes_176,
3237 QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_M,
3238 QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S, 0);
3239 roce_set_field(context->qpc_bytes_176,
3240 QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_M,
3241 QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S,
3242 0);
3243 roce_set_field(context->qpc_bytes_180,
3244 QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_M,
3245 QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S, 0);
3246 roce_set_field(context->qpc_bytes_180,
3247 QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M,
3248 QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S, 0);
3249
3250 context->tx_cur_sq_wqe_ba_l = cpu_to_le32(sq_ba);
3251
3252 roce_set_field(context->qpc_bytes_188,
3253 QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M,
3254 QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S,
3255 upper_32_bits(sq_ba));
3256 roce_set_bit(context->qpc_bytes_188,
3257 QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S, 0);
3258 roce_set_field(context->qpc_bytes_188,
3259 QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M,
3260 QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S,
3261 0);
3262 }
3263
3264 /* Every status migrate must change state */
3265 roce_set_field(context->qpc_bytes_144,
3266 QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3267 QP_CONTEXT_QPC_BYTES_144_QP_STATE_S, new_state);
3268
3269 /* SW pass context to HW */
3270 ret = hns_roce_v1_qp_modify(hr_dev, to_hns_roce_state(cur_state),
3271 to_hns_roce_state(new_state), context,
3272 hr_qp);
3273 if (ret) {
3274 dev_err(dev, "hns_roce_qp_modify failed\n");
3275 goto out;
3276 }
3277
3278 /*
3279 * Use rst2init to instead of init2init with drv,
3280 * need to hw to flash RQ HEAD by DB again
3281 */
3282 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3283 /* Memory barrier */
3284 wmb();
3285
3286 roce_set_field(doorbell[0], RQ_DOORBELL_U32_4_RQ_HEAD_M,
3287 RQ_DOORBELL_U32_4_RQ_HEAD_S, hr_qp->rq.head);
3288 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_QPN_M,
3289 RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
3290 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_CMD_M,
3291 RQ_DOORBELL_U32_8_CMD_S, 1);
3292 roce_set_bit(doorbell[1], RQ_DOORBELL_U32_8_HW_SYNC_S, 1);
3293
3294 if (ibqp->uobject) {
3295 hr_qp->rq.db_reg_l = hr_dev->reg_base +
3296 hr_dev->odb_offset +
3297 DB_REG_OFFSET * hr_dev->priv_uar.index;
3298 }
3299
3300 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
3301 }
3302
3303 hr_qp->state = new_state;
3304
3305 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3306 hr_qp->resp_depth = attr->max_dest_rd_atomic;
3307 if (attr_mask & IB_QP_PORT) {
3308 hr_qp->port = attr->port_num - 1;
3309 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
3310 }
3311
3312 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
3313 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
3314 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
3315 if (ibqp->send_cq != ibqp->recv_cq)
3316 hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
3317 hr_qp->qpn, NULL);
3318
3319 hr_qp->rq.head = 0;
3320 hr_qp->rq.tail = 0;
3321 hr_qp->sq.head = 0;
3322 hr_qp->sq.tail = 0;
3323 }
3324 out:
3325 kfree(context);
3326 return ret;
3327 }
3328
hns_roce_v1_modify_qp(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state)3329 static int hns_roce_v1_modify_qp(struct ib_qp *ibqp,
3330 const struct ib_qp_attr *attr, int attr_mask,
3331 enum ib_qp_state cur_state,
3332 enum ib_qp_state new_state)
3333 {
3334
3335 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
3336 return hns_roce_v1_m_sqp(ibqp, attr, attr_mask, cur_state,
3337 new_state);
3338 else
3339 return hns_roce_v1_m_qp(ibqp, attr, attr_mask, cur_state,
3340 new_state);
3341 }
3342
to_ib_qp_state(enum hns_roce_qp_state state)3343 static enum ib_qp_state to_ib_qp_state(enum hns_roce_qp_state state)
3344 {
3345 switch (state) {
3346 case HNS_ROCE_QP_STATE_RST:
3347 return IB_QPS_RESET;
3348 case HNS_ROCE_QP_STATE_INIT:
3349 return IB_QPS_INIT;
3350 case HNS_ROCE_QP_STATE_RTR:
3351 return IB_QPS_RTR;
3352 case HNS_ROCE_QP_STATE_RTS:
3353 return IB_QPS_RTS;
3354 case HNS_ROCE_QP_STATE_SQD:
3355 return IB_QPS_SQD;
3356 case HNS_ROCE_QP_STATE_ERR:
3357 return IB_QPS_ERR;
3358 default:
3359 return IB_QPS_ERR;
3360 }
3361 }
3362
hns_roce_v1_query_qpc(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,struct hns_roce_qp_context * hr_context)3363 static int hns_roce_v1_query_qpc(struct hns_roce_dev *hr_dev,
3364 struct hns_roce_qp *hr_qp,
3365 struct hns_roce_qp_context *hr_context)
3366 {
3367 struct hns_roce_cmd_mailbox *mailbox;
3368 int ret;
3369
3370 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3371 if (IS_ERR(mailbox))
3372 return PTR_ERR(mailbox);
3373
3374 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
3375 HNS_ROCE_CMD_QUERY_QP,
3376 HNS_ROCE_CMD_TIMEOUT_MSECS);
3377 if (!ret)
3378 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
3379 else
3380 dev_err(&hr_dev->pdev->dev, "QUERY QP cmd process error\n");
3381
3382 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3383
3384 return ret;
3385 }
3386
hns_roce_v1_q_sqp(struct ib_qp * ibqp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)3387 static int hns_roce_v1_q_sqp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3388 int qp_attr_mask,
3389 struct ib_qp_init_attr *qp_init_attr)
3390 {
3391 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3392 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3393 struct hns_roce_sqp_context context;
3394 u32 addr;
3395
3396 mutex_lock(&hr_qp->mutex);
3397
3398 if (hr_qp->state == IB_QPS_RESET) {
3399 qp_attr->qp_state = IB_QPS_RESET;
3400 goto done;
3401 }
3402
3403 addr = ROCEE_QP1C_CFG0_0_REG +
3404 hr_qp->port * sizeof(struct hns_roce_sqp_context);
3405 context.qp1c_bytes_4 = cpu_to_le32(roce_read(hr_dev, addr));
3406 context.sq_rq_bt_l = cpu_to_le32(roce_read(hr_dev, addr + 1));
3407 context.qp1c_bytes_12 = cpu_to_le32(roce_read(hr_dev, addr + 2));
3408 context.qp1c_bytes_16 = cpu_to_le32(roce_read(hr_dev, addr + 3));
3409 context.qp1c_bytes_20 = cpu_to_le32(roce_read(hr_dev, addr + 4));
3410 context.cur_rq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 5));
3411 context.qp1c_bytes_28 = cpu_to_le32(roce_read(hr_dev, addr + 6));
3412 context.qp1c_bytes_32 = cpu_to_le32(roce_read(hr_dev, addr + 7));
3413 context.cur_sq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 8));
3414 context.qp1c_bytes_40 = cpu_to_le32(roce_read(hr_dev, addr + 9));
3415
3416 hr_qp->state = roce_get_field(context.qp1c_bytes_4,
3417 QP1C_BYTES_4_QP_STATE_M,
3418 QP1C_BYTES_4_QP_STATE_S);
3419 qp_attr->qp_state = hr_qp->state;
3420 qp_attr->path_mtu = IB_MTU_256;
3421 qp_attr->path_mig_state = IB_MIG_ARMED;
3422 qp_attr->qkey = QKEY_VAL;
3423 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
3424 qp_attr->rq_psn = 0;
3425 qp_attr->sq_psn = 0;
3426 qp_attr->dest_qp_num = 1;
3427 qp_attr->qp_access_flags = 6;
3428
3429 qp_attr->pkey_index = roce_get_field(context.qp1c_bytes_20,
3430 QP1C_BYTES_20_PKEY_IDX_M,
3431 QP1C_BYTES_20_PKEY_IDX_S);
3432 qp_attr->port_num = hr_qp->port + 1;
3433 qp_attr->sq_draining = 0;
3434 qp_attr->max_rd_atomic = 0;
3435 qp_attr->max_dest_rd_atomic = 0;
3436 qp_attr->min_rnr_timer = 0;
3437 qp_attr->timeout = 0;
3438 qp_attr->retry_cnt = 0;
3439 qp_attr->rnr_retry = 0;
3440 qp_attr->alt_timeout = 0;
3441
3442 done:
3443 qp_attr->cur_qp_state = qp_attr->qp_state;
3444 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3445 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3446 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3447 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3448 qp_attr->cap.max_inline_data = 0;
3449 qp_init_attr->cap = qp_attr->cap;
3450 qp_init_attr->create_flags = 0;
3451
3452 mutex_unlock(&hr_qp->mutex);
3453
3454 return 0;
3455 }
3456
hns_roce_v1_q_qp(struct ib_qp * ibqp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)3457 static int hns_roce_v1_q_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3458 int qp_attr_mask,
3459 struct ib_qp_init_attr *qp_init_attr)
3460 {
3461 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3462 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3463 struct device *dev = &hr_dev->pdev->dev;
3464 struct hns_roce_qp_context *context;
3465 int tmp_qp_state;
3466 int ret = 0;
3467 int state;
3468
3469 context = kzalloc(sizeof(*context), GFP_KERNEL);
3470 if (!context)
3471 return -ENOMEM;
3472
3473 memset(qp_attr, 0, sizeof(*qp_attr));
3474 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
3475
3476 mutex_lock(&hr_qp->mutex);
3477
3478 if (hr_qp->state == IB_QPS_RESET) {
3479 qp_attr->qp_state = IB_QPS_RESET;
3480 goto done;
3481 }
3482
3483 ret = hns_roce_v1_query_qpc(hr_dev, hr_qp, context);
3484 if (ret) {
3485 dev_err(dev, "query qpc error\n");
3486 ret = -EINVAL;
3487 goto out;
3488 }
3489
3490 state = roce_get_field(context->qpc_bytes_144,
3491 QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3492 QP_CONTEXT_QPC_BYTES_144_QP_STATE_S);
3493 tmp_qp_state = (int)to_ib_qp_state((enum hns_roce_qp_state)state);
3494 if (tmp_qp_state == -1) {
3495 dev_err(dev, "to_ib_qp_state error\n");
3496 ret = -EINVAL;
3497 goto out;
3498 }
3499 hr_qp->state = (u8)tmp_qp_state;
3500 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
3501 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->qpc_bytes_48,
3502 QP_CONTEXT_QPC_BYTES_48_MTU_M,
3503 QP_CONTEXT_QPC_BYTES_48_MTU_S);
3504 qp_attr->path_mig_state = IB_MIG_ARMED;
3505 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
3506 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
3507 qp_attr->qkey = QKEY_VAL;
3508
3509 qp_attr->rq_psn = roce_get_field(context->qpc_bytes_88,
3510 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3511 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S);
3512 qp_attr->sq_psn = (u32)roce_get_field(context->qpc_bytes_164,
3513 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3514 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S);
3515 qp_attr->dest_qp_num = (u8)roce_get_field(context->qpc_bytes_36,
3516 QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
3517 QP_CONTEXT_QPC_BYTES_36_DEST_QP_S);
3518 qp_attr->qp_access_flags = ((roce_get_bit(context->qpc_bytes_4,
3519 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S)) << 2) |
3520 ((roce_get_bit(context->qpc_bytes_4,
3521 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S)) << 1) |
3522 ((roce_get_bit(context->qpc_bytes_4,
3523 QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S)) << 3);
3524
3525 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
3526 hr_qp->ibqp.qp_type == IB_QPT_UC) {
3527 struct ib_global_route *grh =
3528 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
3529
3530 rdma_ah_set_sl(&qp_attr->ah_attr,
3531 roce_get_field(context->qpc_bytes_156,
3532 QP_CONTEXT_QPC_BYTES_156_SL_M,
3533 QP_CONTEXT_QPC_BYTES_156_SL_S));
3534 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH);
3535 grh->flow_label =
3536 roce_get_field(context->qpc_bytes_48,
3537 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
3538 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S);
3539 grh->sgid_index =
3540 roce_get_field(context->qpc_bytes_36,
3541 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
3542 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S);
3543 grh->hop_limit =
3544 roce_get_field(context->qpc_bytes_44,
3545 QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
3546 QP_CONTEXT_QPC_BYTES_44_HOPLMT_S);
3547 grh->traffic_class =
3548 roce_get_field(context->qpc_bytes_48,
3549 QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3550 QP_CONTEXT_QPC_BYTES_48_TCLASS_S);
3551
3552 memcpy(grh->dgid.raw, context->dgid,
3553 sizeof(grh->dgid.raw));
3554 }
3555
3556 qp_attr->pkey_index = roce_get_field(context->qpc_bytes_12,
3557 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
3558 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S);
3559 qp_attr->port_num = hr_qp->port + 1;
3560 qp_attr->sq_draining = 0;
3561 qp_attr->max_rd_atomic = 1 << roce_get_field(context->qpc_bytes_156,
3562 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3563 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S);
3564 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->qpc_bytes_32,
3565 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
3566 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S);
3567 qp_attr->min_rnr_timer = (u8)(roce_get_field(context->qpc_bytes_24,
3568 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
3569 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S));
3570 qp_attr->timeout = (u8)(roce_get_field(context->qpc_bytes_156,
3571 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3572 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S));
3573 qp_attr->retry_cnt = roce_get_field(context->qpc_bytes_148,
3574 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3575 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S);
3576 qp_attr->rnr_retry = (u8)le32_to_cpu(context->rnr_retry);
3577
3578 done:
3579 qp_attr->cur_qp_state = qp_attr->qp_state;
3580 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3581 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3582
3583 if (!ibqp->uobject) {
3584 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3585 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3586 } else {
3587 qp_attr->cap.max_send_wr = 0;
3588 qp_attr->cap.max_send_sge = 0;
3589 }
3590
3591 qp_init_attr->cap = qp_attr->cap;
3592
3593 out:
3594 mutex_unlock(&hr_qp->mutex);
3595 kfree(context);
3596 return ret;
3597 }
3598
hns_roce_v1_query_qp(struct ib_qp * ibqp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)3599 static int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3600 int qp_attr_mask,
3601 struct ib_qp_init_attr *qp_init_attr)
3602 {
3603 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3604
3605 return hr_qp->doorbell_qpn <= 1 ?
3606 hns_roce_v1_q_sqp(ibqp, qp_attr, qp_attr_mask, qp_init_attr) :
3607 hns_roce_v1_q_qp(ibqp, qp_attr, qp_attr_mask, qp_init_attr);
3608 }
3609
hns_roce_v1_destroy_qp(struct ib_qp * ibqp,struct ib_udata * udata)3610 int hns_roce_v1_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
3611 {
3612 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3613 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3614 struct hns_roce_cq *send_cq, *recv_cq;
3615 int ret;
3616
3617 ret = hns_roce_v1_modify_qp(ibqp, NULL, 0, hr_qp->state, IB_QPS_RESET);
3618 if (ret)
3619 return ret;
3620
3621 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL;
3622 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL;
3623
3624 hns_roce_lock_cqs(send_cq, recv_cq);
3625 if (!udata) {
3626 if (recv_cq)
3627 __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn,
3628 (hr_qp->ibqp.srq ?
3629 to_hr_srq(hr_qp->ibqp.srq) :
3630 NULL));
3631
3632 if (send_cq && send_cq != recv_cq)
3633 __hns_roce_v1_cq_clean(send_cq, hr_qp->qpn, NULL);
3634 }
3635 hns_roce_qp_remove(hr_dev, hr_qp);
3636 hns_roce_unlock_cqs(send_cq, recv_cq);
3637
3638 hns_roce_qp_destroy(hr_dev, hr_qp, udata);
3639
3640 return 0;
3641 }
3642
hns_roce_v1_destroy_cq(struct ib_cq * ibcq,struct ib_udata * udata)3643 static int hns_roce_v1_destroy_cq(struct ib_cq *ibcq, struct ib_udata *udata)
3644 {
3645 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3646 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3647 struct device *dev = &hr_dev->pdev->dev;
3648 u32 cqe_cnt_ori;
3649 u32 cqe_cnt_cur;
3650 int wait_time = 0;
3651
3652 /*
3653 * Before freeing cq buffer, we need to ensure that the outstanding CQE
3654 * have been written by checking the CQE counter.
3655 */
3656 cqe_cnt_ori = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3657 while (1) {
3658 if (roce_read(hr_dev, ROCEE_CAEP_CQE_WCMD_EMPTY) &
3659 HNS_ROCE_CQE_WCMD_EMPTY_BIT)
3660 break;
3661
3662 cqe_cnt_cur = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3663 if ((cqe_cnt_cur - cqe_cnt_ori) >= HNS_ROCE_MIN_CQE_CNT)
3664 break;
3665
3666 msleep(HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS);
3667 if (wait_time > HNS_ROCE_MAX_FREE_CQ_WAIT_CNT) {
3668 dev_warn(dev, "Destroy cq 0x%lx timeout!\n",
3669 hr_cq->cqn);
3670 break;
3671 }
3672 wait_time++;
3673 }
3674 return 0;
3675 }
3676
set_eq_cons_index_v1(struct hns_roce_eq * eq,int req_not)3677 static void set_eq_cons_index_v1(struct hns_roce_eq *eq, int req_not)
3678 {
3679 roce_raw_write((eq->cons_index & HNS_ROCE_V1_CONS_IDX_M) |
3680 (req_not << eq->log_entries), eq->doorbell);
3681 }
3682
hns_roce_v1_wq_catas_err_handle(struct hns_roce_dev * hr_dev,struct hns_roce_aeqe * aeqe,int qpn)3683 static void hns_roce_v1_wq_catas_err_handle(struct hns_roce_dev *hr_dev,
3684 struct hns_roce_aeqe *aeqe, int qpn)
3685 {
3686 struct device *dev = &hr_dev->pdev->dev;
3687
3688 dev_warn(dev, "Local Work Queue Catastrophic Error.\n");
3689 switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3690 HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3691 case HNS_ROCE_LWQCE_QPC_ERROR:
3692 dev_warn(dev, "QP %d, QPC error.\n", qpn);
3693 break;
3694 case HNS_ROCE_LWQCE_MTU_ERROR:
3695 dev_warn(dev, "QP %d, MTU error.\n", qpn);
3696 break;
3697 case HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR:
3698 dev_warn(dev, "QP %d, WQE BA addr error.\n", qpn);
3699 break;
3700 case HNS_ROCE_LWQCE_WQE_ADDR_ERROR:
3701 dev_warn(dev, "QP %d, WQE addr error.\n", qpn);
3702 break;
3703 case HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR:
3704 dev_warn(dev, "QP %d, WQE shift error\n", qpn);
3705 break;
3706 case HNS_ROCE_LWQCE_SL_ERROR:
3707 dev_warn(dev, "QP %d, SL error.\n", qpn);
3708 break;
3709 case HNS_ROCE_LWQCE_PORT_ERROR:
3710 dev_warn(dev, "QP %d, port error.\n", qpn);
3711 break;
3712 default:
3713 break;
3714 }
3715 }
3716
hns_roce_v1_local_wq_access_err_handle(struct hns_roce_dev * hr_dev,struct hns_roce_aeqe * aeqe,int qpn)3717 static void hns_roce_v1_local_wq_access_err_handle(struct hns_roce_dev *hr_dev,
3718 struct hns_roce_aeqe *aeqe,
3719 int qpn)
3720 {
3721 struct device *dev = &hr_dev->pdev->dev;
3722
3723 dev_warn(dev, "Local Access Violation Work Queue Error.\n");
3724 switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3725 HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3726 case HNS_ROCE_LAVWQE_R_KEY_VIOLATION:
3727 dev_warn(dev, "QP %d, R_key violation.\n", qpn);
3728 break;
3729 case HNS_ROCE_LAVWQE_LENGTH_ERROR:
3730 dev_warn(dev, "QP %d, length error.\n", qpn);
3731 break;
3732 case HNS_ROCE_LAVWQE_VA_ERROR:
3733 dev_warn(dev, "QP %d, VA error.\n", qpn);
3734 break;
3735 case HNS_ROCE_LAVWQE_PD_ERROR:
3736 dev_err(dev, "QP %d, PD error.\n", qpn);
3737 break;
3738 case HNS_ROCE_LAVWQE_RW_ACC_ERROR:
3739 dev_warn(dev, "QP %d, rw acc error.\n", qpn);
3740 break;
3741 case HNS_ROCE_LAVWQE_KEY_STATE_ERROR:
3742 dev_warn(dev, "QP %d, key state error.\n", qpn);
3743 break;
3744 case HNS_ROCE_LAVWQE_MR_OPERATION_ERROR:
3745 dev_warn(dev, "QP %d, MR operation error.\n", qpn);
3746 break;
3747 default:
3748 break;
3749 }
3750 }
3751
hns_roce_v1_qp_err_handle(struct hns_roce_dev * hr_dev,struct hns_roce_aeqe * aeqe,int event_type)3752 static void hns_roce_v1_qp_err_handle(struct hns_roce_dev *hr_dev,
3753 struct hns_roce_aeqe *aeqe,
3754 int event_type)
3755 {
3756 struct device *dev = &hr_dev->pdev->dev;
3757 int phy_port;
3758 int qpn;
3759
3760 qpn = roce_get_field(aeqe->event.qp_event.qp,
3761 HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_M,
3762 HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S);
3763 phy_port = roce_get_field(aeqe->event.qp_event.qp,
3764 HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_M,
3765 HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S);
3766 if (qpn <= 1)
3767 qpn = HNS_ROCE_MAX_PORTS * qpn + phy_port;
3768
3769 switch (event_type) {
3770 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
3771 dev_warn(dev, "Invalid Req Local Work Queue Error.\n"
3772 "QP %d, phy_port %d.\n", qpn, phy_port);
3773 break;
3774 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
3775 hns_roce_v1_wq_catas_err_handle(hr_dev, aeqe, qpn);
3776 break;
3777 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
3778 hns_roce_v1_local_wq_access_err_handle(hr_dev, aeqe, qpn);
3779 break;
3780 default:
3781 break;
3782 }
3783
3784 hns_roce_qp_event(hr_dev, qpn, event_type);
3785 }
3786
hns_roce_v1_cq_err_handle(struct hns_roce_dev * hr_dev,struct hns_roce_aeqe * aeqe,int event_type)3787 static void hns_roce_v1_cq_err_handle(struct hns_roce_dev *hr_dev,
3788 struct hns_roce_aeqe *aeqe,
3789 int event_type)
3790 {
3791 struct device *dev = &hr_dev->pdev->dev;
3792 u32 cqn;
3793
3794 cqn = roce_get_field(aeqe->event.cq_event.cq,
3795 HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_M,
3796 HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S);
3797
3798 switch (event_type) {
3799 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
3800 dev_warn(dev, "CQ 0x%x access err.\n", cqn);
3801 break;
3802 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
3803 dev_warn(dev, "CQ 0x%x overflow\n", cqn);
3804 break;
3805 case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
3806 dev_warn(dev, "CQ 0x%x ID invalid.\n", cqn);
3807 break;
3808 default:
3809 break;
3810 }
3811
3812 hns_roce_cq_event(hr_dev, cqn, event_type);
3813 }
3814
hns_roce_v1_db_overflow_handle(struct hns_roce_dev * hr_dev,struct hns_roce_aeqe * aeqe)3815 static void hns_roce_v1_db_overflow_handle(struct hns_roce_dev *hr_dev,
3816 struct hns_roce_aeqe *aeqe)
3817 {
3818 struct device *dev = &hr_dev->pdev->dev;
3819
3820 switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3821 HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3822 case HNS_ROCE_DB_SUBTYPE_SDB_OVF:
3823 dev_warn(dev, "SDB overflow.\n");
3824 break;
3825 case HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF:
3826 dev_warn(dev, "SDB almost overflow.\n");
3827 break;
3828 case HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP:
3829 dev_warn(dev, "SDB almost empty.\n");
3830 break;
3831 case HNS_ROCE_DB_SUBTYPE_ODB_OVF:
3832 dev_warn(dev, "ODB overflow.\n");
3833 break;
3834 case HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF:
3835 dev_warn(dev, "ODB almost overflow.\n");
3836 break;
3837 case HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP:
3838 dev_warn(dev, "SDB almost empty.\n");
3839 break;
3840 default:
3841 break;
3842 }
3843 }
3844
get_aeqe_v1(struct hns_roce_eq * eq,u32 entry)3845 static struct hns_roce_aeqe *get_aeqe_v1(struct hns_roce_eq *eq, u32 entry)
3846 {
3847 unsigned long off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQE_SIZE;
3848
3849 return (struct hns_roce_aeqe *)((u8 *)
3850 (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
3851 off % HNS_ROCE_BA_SIZE);
3852 }
3853
next_aeqe_sw_v1(struct hns_roce_eq * eq)3854 static struct hns_roce_aeqe *next_aeqe_sw_v1(struct hns_roce_eq *eq)
3855 {
3856 struct hns_roce_aeqe *aeqe = get_aeqe_v1(eq, eq->cons_index);
3857
3858 return (roce_get_bit(aeqe->asyn, HNS_ROCE_AEQE_U32_4_OWNER_S) ^
3859 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
3860 }
3861
hns_roce_v1_aeq_int(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)3862 static int hns_roce_v1_aeq_int(struct hns_roce_dev *hr_dev,
3863 struct hns_roce_eq *eq)
3864 {
3865 struct device *dev = &hr_dev->pdev->dev;
3866 struct hns_roce_aeqe *aeqe;
3867 int aeqes_found = 0;
3868 int event_type;
3869
3870 while ((aeqe = next_aeqe_sw_v1(eq))) {
3871 /* Make sure we read the AEQ entry after we have checked the
3872 * ownership bit
3873 */
3874 dma_rmb();
3875
3876 dev_dbg(dev, "aeqe = %pK, aeqe->asyn.event_type = 0x%lx\n",
3877 aeqe,
3878 roce_get_field(aeqe->asyn,
3879 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
3880 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S));
3881 event_type = roce_get_field(aeqe->asyn,
3882 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
3883 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S);
3884 switch (event_type) {
3885 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
3886 dev_warn(dev, "PATH MIG not supported\n");
3887 break;
3888 case HNS_ROCE_EVENT_TYPE_COMM_EST:
3889 dev_warn(dev, "COMMUNICATION established\n");
3890 break;
3891 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
3892 dev_warn(dev, "SQ DRAINED not supported\n");
3893 break;
3894 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
3895 dev_warn(dev, "PATH MIG failed\n");
3896 break;
3897 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
3898 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
3899 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
3900 hns_roce_v1_qp_err_handle(hr_dev, aeqe, event_type);
3901 break;
3902 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
3903 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
3904 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
3905 dev_warn(dev, "SRQ not support!\n");
3906 break;
3907 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
3908 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
3909 case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
3910 hns_roce_v1_cq_err_handle(hr_dev, aeqe, event_type);
3911 break;
3912 case HNS_ROCE_EVENT_TYPE_PORT_CHANGE:
3913 dev_warn(dev, "port change.\n");
3914 break;
3915 case HNS_ROCE_EVENT_TYPE_MB:
3916 hns_roce_cmd_event(hr_dev,
3917 le16_to_cpu(aeqe->event.cmd.token),
3918 aeqe->event.cmd.status,
3919 le64_to_cpu(aeqe->event.cmd.out_param
3920 ));
3921 break;
3922 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
3923 hns_roce_v1_db_overflow_handle(hr_dev, aeqe);
3924 break;
3925 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW:
3926 dev_warn(dev, "CEQ 0x%lx overflow.\n",
3927 roce_get_field(aeqe->event.ce_event.ceqe,
3928 HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_M,
3929 HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_S));
3930 break;
3931 default:
3932 dev_warn(dev, "Unhandled event %d on EQ %d at idx %u.\n",
3933 event_type, eq->eqn, eq->cons_index);
3934 break;
3935 }
3936
3937 eq->cons_index++;
3938 aeqes_found = 1;
3939
3940 if (eq->cons_index > 2 * hr_dev->caps.aeqe_depth - 1)
3941 eq->cons_index = 0;
3942 }
3943
3944 set_eq_cons_index_v1(eq, 0);
3945
3946 return aeqes_found;
3947 }
3948
get_ceqe_v1(struct hns_roce_eq * eq,u32 entry)3949 static struct hns_roce_ceqe *get_ceqe_v1(struct hns_roce_eq *eq, u32 entry)
3950 {
3951 unsigned long off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQE_SIZE;
3952
3953 return (struct hns_roce_ceqe *)((u8 *)
3954 (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
3955 off % HNS_ROCE_BA_SIZE);
3956 }
3957
next_ceqe_sw_v1(struct hns_roce_eq * eq)3958 static struct hns_roce_ceqe *next_ceqe_sw_v1(struct hns_roce_eq *eq)
3959 {
3960 struct hns_roce_ceqe *ceqe = get_ceqe_v1(eq, eq->cons_index);
3961
3962 return (!!(roce_get_bit(ceqe->comp,
3963 HNS_ROCE_CEQE_CEQE_COMP_OWNER_S))) ^
3964 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
3965 }
3966
hns_roce_v1_ceq_int(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)3967 static int hns_roce_v1_ceq_int(struct hns_roce_dev *hr_dev,
3968 struct hns_roce_eq *eq)
3969 {
3970 struct hns_roce_ceqe *ceqe;
3971 int ceqes_found = 0;
3972 u32 cqn;
3973
3974 while ((ceqe = next_ceqe_sw_v1(eq))) {
3975 /* Make sure we read CEQ entry after we have checked the
3976 * ownership bit
3977 */
3978 dma_rmb();
3979
3980 cqn = roce_get_field(ceqe->comp,
3981 HNS_ROCE_CEQE_CEQE_COMP_CQN_M,
3982 HNS_ROCE_CEQE_CEQE_COMP_CQN_S);
3983 hns_roce_cq_completion(hr_dev, cqn);
3984
3985 ++eq->cons_index;
3986 ceqes_found = 1;
3987
3988 if (eq->cons_index >
3989 EQ_DEPTH_COEFF * hr_dev->caps.ceqe_depth - 1)
3990 eq->cons_index = 0;
3991 }
3992
3993 set_eq_cons_index_v1(eq, 0);
3994
3995 return ceqes_found;
3996 }
3997
hns_roce_v1_msix_interrupt_eq(int irq,void * eq_ptr)3998 static irqreturn_t hns_roce_v1_msix_interrupt_eq(int irq, void *eq_ptr)
3999 {
4000 struct hns_roce_eq *eq = eq_ptr;
4001 struct hns_roce_dev *hr_dev = eq->hr_dev;
4002 int int_work;
4003
4004 if (eq->type_flag == HNS_ROCE_CEQ)
4005 /* CEQ irq routine, CEQ is pulse irq, not clear */
4006 int_work = hns_roce_v1_ceq_int(hr_dev, eq);
4007 else
4008 /* AEQ irq routine, AEQ is pulse irq, not clear */
4009 int_work = hns_roce_v1_aeq_int(hr_dev, eq);
4010
4011 return IRQ_RETVAL(int_work);
4012 }
4013
hns_roce_v1_msix_interrupt_abn(int irq,void * dev_id)4014 static irqreturn_t hns_roce_v1_msix_interrupt_abn(int irq, void *dev_id)
4015 {
4016 struct hns_roce_dev *hr_dev = dev_id;
4017 struct device *dev = &hr_dev->pdev->dev;
4018 int int_work = 0;
4019 u32 caepaemask_val;
4020 u32 cealmovf_val;
4021 u32 caepaest_val;
4022 u32 aeshift_val;
4023 u32 ceshift_val;
4024 u32 cemask_val;
4025 __le32 tmp;
4026 int i;
4027
4028 /*
4029 * Abnormal interrupt:
4030 * AEQ overflow, ECC multi-bit err, CEQ overflow must clear
4031 * interrupt, mask irq, clear irq, cancel mask operation
4032 */
4033 aeshift_val = roce_read(hr_dev, ROCEE_CAEP_AEQC_AEQE_SHIFT_REG);
4034 tmp = cpu_to_le32(aeshift_val);
4035
4036 /* AEQE overflow */
4037 if (roce_get_bit(tmp,
4038 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQ_ALM_OVF_INT_ST_S) == 1) {
4039 dev_warn(dev, "AEQ overflow!\n");
4040
4041 /* Set mask */
4042 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4043 tmp = cpu_to_le32(caepaemask_val);
4044 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4045 HNS_ROCE_INT_MASK_ENABLE);
4046 caepaemask_val = le32_to_cpu(tmp);
4047 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
4048
4049 /* Clear int state(INT_WC : write 1 clear) */
4050 caepaest_val = roce_read(hr_dev, ROCEE_CAEP_AE_ST_REG);
4051 tmp = cpu_to_le32(caepaest_val);
4052 roce_set_bit(tmp, ROCEE_CAEP_AE_ST_CAEP_AEQ_ALM_OVF_S, 1);
4053 caepaest_val = le32_to_cpu(tmp);
4054 roce_write(hr_dev, ROCEE_CAEP_AE_ST_REG, caepaest_val);
4055
4056 /* Clear mask */
4057 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4058 tmp = cpu_to_le32(caepaemask_val);
4059 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4060 HNS_ROCE_INT_MASK_DISABLE);
4061 caepaemask_val = le32_to_cpu(tmp);
4062 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
4063 }
4064
4065 /* CEQ almost overflow */
4066 for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
4067 ceshift_val = roce_read(hr_dev, ROCEE_CAEP_CEQC_SHIFT_0_REG +
4068 i * CEQ_REG_OFFSET);
4069 tmp = cpu_to_le32(ceshift_val);
4070
4071 if (roce_get_bit(tmp,
4072 ROCEE_CAEP_CEQC_SHIFT_CAEP_CEQ_ALM_OVF_INT_ST_S) == 1) {
4073 dev_warn(dev, "CEQ[%d] almost overflow!\n", i);
4074 int_work++;
4075
4076 /* Set mask */
4077 cemask_val = roce_read(hr_dev,
4078 ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4079 i * CEQ_REG_OFFSET);
4080 tmp = cpu_to_le32(cemask_val);
4081 roce_set_bit(tmp,
4082 ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4083 HNS_ROCE_INT_MASK_ENABLE);
4084 cemask_val = le32_to_cpu(tmp);
4085 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4086 i * CEQ_REG_OFFSET, cemask_val);
4087
4088 /* Clear int state(INT_WC : write 1 clear) */
4089 cealmovf_val = roce_read(hr_dev,
4090 ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4091 i * CEQ_REG_OFFSET);
4092 tmp = cpu_to_le32(cealmovf_val);
4093 roce_set_bit(tmp,
4094 ROCEE_CAEP_CEQ_ALM_OVF_CAEP_CEQ_ALM_OVF_S,
4095 1);
4096 cealmovf_val = le32_to_cpu(tmp);
4097 roce_write(hr_dev, ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4098 i * CEQ_REG_OFFSET, cealmovf_val);
4099
4100 /* Clear mask */
4101 cemask_val = roce_read(hr_dev,
4102 ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4103 i * CEQ_REG_OFFSET);
4104 tmp = cpu_to_le32(cemask_val);
4105 roce_set_bit(tmp,
4106 ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4107 HNS_ROCE_INT_MASK_DISABLE);
4108 cemask_val = le32_to_cpu(tmp);
4109 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4110 i * CEQ_REG_OFFSET, cemask_val);
4111 }
4112 }
4113
4114 /* ECC multi-bit error alarm */
4115 dev_warn(dev, "ECC UCERR ALARM: 0x%x, 0x%x, 0x%x\n",
4116 roce_read(hr_dev, ROCEE_ECC_UCERR_ALM0_REG),
4117 roce_read(hr_dev, ROCEE_ECC_UCERR_ALM1_REG),
4118 roce_read(hr_dev, ROCEE_ECC_UCERR_ALM2_REG));
4119
4120 dev_warn(dev, "ECC CERR ALARM: 0x%x, 0x%x, 0x%x\n",
4121 roce_read(hr_dev, ROCEE_ECC_CERR_ALM0_REG),
4122 roce_read(hr_dev, ROCEE_ECC_CERR_ALM1_REG),
4123 roce_read(hr_dev, ROCEE_ECC_CERR_ALM2_REG));
4124
4125 return IRQ_RETVAL(int_work);
4126 }
4127
hns_roce_v1_int_mask_enable(struct hns_roce_dev * hr_dev)4128 static void hns_roce_v1_int_mask_enable(struct hns_roce_dev *hr_dev)
4129 {
4130 u32 aemask_val;
4131 int masken = 0;
4132 __le32 tmp;
4133 int i;
4134
4135 /* AEQ INT */
4136 aemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4137 tmp = cpu_to_le32(aemask_val);
4138 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4139 masken);
4140 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AE_IRQ_MASK_S, masken);
4141 aemask_val = le32_to_cpu(tmp);
4142 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, aemask_val);
4143
4144 /* CEQ INT */
4145 for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
4146 /* IRQ mask */
4147 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4148 i * CEQ_REG_OFFSET, masken);
4149 }
4150 }
4151
hns_roce_v1_free_eq(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)4152 static void hns_roce_v1_free_eq(struct hns_roce_dev *hr_dev,
4153 struct hns_roce_eq *eq)
4154 {
4155 int npages = (PAGE_ALIGN(eq->eqe_size * eq->entries) +
4156 HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4157 int i;
4158
4159 if (!eq->buf_list)
4160 return;
4161
4162 for (i = 0; i < npages; ++i)
4163 dma_free_coherent(&hr_dev->pdev->dev, HNS_ROCE_BA_SIZE,
4164 eq->buf_list[i].buf, eq->buf_list[i].map);
4165
4166 kfree(eq->buf_list);
4167 }
4168
hns_roce_v1_enable_eq(struct hns_roce_dev * hr_dev,int eq_num,int enable_flag)4169 static void hns_roce_v1_enable_eq(struct hns_roce_dev *hr_dev, int eq_num,
4170 int enable_flag)
4171 {
4172 void __iomem *eqc = hr_dev->eq_table.eqc_base[eq_num];
4173 __le32 tmp;
4174 u32 val;
4175
4176 val = readl(eqc);
4177 tmp = cpu_to_le32(val);
4178
4179 if (enable_flag)
4180 roce_set_field(tmp,
4181 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4182 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4183 HNS_ROCE_EQ_STAT_VALID);
4184 else
4185 roce_set_field(tmp,
4186 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4187 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4188 HNS_ROCE_EQ_STAT_INVALID);
4189
4190 val = le32_to_cpu(tmp);
4191 writel(val, eqc);
4192 }
4193
hns_roce_v1_create_eq(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)4194 static int hns_roce_v1_create_eq(struct hns_roce_dev *hr_dev,
4195 struct hns_roce_eq *eq)
4196 {
4197 void __iomem *eqc = hr_dev->eq_table.eqc_base[eq->eqn];
4198 struct device *dev = &hr_dev->pdev->dev;
4199 dma_addr_t tmp_dma_addr;
4200 u32 eqcuridx_val = 0;
4201 u32 eqconsindx_val;
4202 u32 eqshift_val;
4203 __le32 tmp2 = 0;
4204 __le32 tmp1 = 0;
4205 __le32 tmp = 0;
4206 int num_bas;
4207 int ret;
4208 int i;
4209
4210 num_bas = (PAGE_ALIGN(eq->entries * eq->eqe_size) +
4211 HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4212
4213 if ((eq->entries * eq->eqe_size) > HNS_ROCE_BA_SIZE) {
4214 dev_err(dev, "[error]eq buf %d gt ba size(%d) need bas=%d\n",
4215 (eq->entries * eq->eqe_size), HNS_ROCE_BA_SIZE,
4216 num_bas);
4217 return -EINVAL;
4218 }
4219
4220 eq->buf_list = kcalloc(num_bas, sizeof(*eq->buf_list), GFP_KERNEL);
4221 if (!eq->buf_list)
4222 return -ENOMEM;
4223
4224 for (i = 0; i < num_bas; ++i) {
4225 eq->buf_list[i].buf = dma_alloc_coherent(dev, HNS_ROCE_BA_SIZE,
4226 &tmp_dma_addr,
4227 GFP_KERNEL);
4228 if (!eq->buf_list[i].buf) {
4229 ret = -ENOMEM;
4230 goto err_out_free_pages;
4231 }
4232
4233 eq->buf_list[i].map = tmp_dma_addr;
4234 }
4235 eq->cons_index = 0;
4236 roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4237 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4238 HNS_ROCE_EQ_STAT_INVALID);
4239 roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_M,
4240 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S,
4241 eq->log_entries);
4242 eqshift_val = le32_to_cpu(tmp);
4243 writel(eqshift_val, eqc);
4244
4245 /* Configure eq extended address 12~44bit */
4246 writel((u32)(eq->buf_list[0].map >> 12), eqc + 4);
4247
4248 /*
4249 * Configure eq extended address 45~49 bit.
4250 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
4251 * using 4K page, and shift more 32 because of
4252 * caculating the high 32 bit value evaluated to hardware.
4253 */
4254 roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_M,
4255 ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S,
4256 eq->buf_list[0].map >> 44);
4257 roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_M,
4258 ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S, 0);
4259 eqcuridx_val = le32_to_cpu(tmp1);
4260 writel(eqcuridx_val, eqc + 8);
4261
4262 /* Configure eq consumer index */
4263 roce_set_field(tmp2, ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_M,
4264 ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S, 0);
4265 eqconsindx_val = le32_to_cpu(tmp2);
4266 writel(eqconsindx_val, eqc + 0xc);
4267
4268 return 0;
4269
4270 err_out_free_pages:
4271 for (i -= 1; i >= 0; i--)
4272 dma_free_coherent(dev, HNS_ROCE_BA_SIZE, eq->buf_list[i].buf,
4273 eq->buf_list[i].map);
4274
4275 kfree(eq->buf_list);
4276 return ret;
4277 }
4278
hns_roce_v1_init_eq_table(struct hns_roce_dev * hr_dev)4279 static int hns_roce_v1_init_eq_table(struct hns_roce_dev *hr_dev)
4280 {
4281 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4282 struct device *dev = &hr_dev->pdev->dev;
4283 struct hns_roce_eq *eq;
4284 int irq_num;
4285 int eq_num;
4286 int ret;
4287 int i, j;
4288
4289 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4290 irq_num = eq_num + hr_dev->caps.num_other_vectors;
4291
4292 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
4293 if (!eq_table->eq)
4294 return -ENOMEM;
4295
4296 eq_table->eqc_base = kcalloc(eq_num, sizeof(*eq_table->eqc_base),
4297 GFP_KERNEL);
4298 if (!eq_table->eqc_base) {
4299 ret = -ENOMEM;
4300 goto err_eqc_base_alloc_fail;
4301 }
4302
4303 for (i = 0; i < eq_num; i++) {
4304 eq = &eq_table->eq[i];
4305 eq->hr_dev = hr_dev;
4306 eq->eqn = i;
4307 eq->irq = hr_dev->irq[i];
4308 eq->log_page_size = PAGE_SHIFT;
4309
4310 if (i < hr_dev->caps.num_comp_vectors) {
4311 /* CEQ */
4312 eq_table->eqc_base[i] = hr_dev->reg_base +
4313 ROCEE_CAEP_CEQC_SHIFT_0_REG +
4314 CEQ_REG_OFFSET * i;
4315 eq->type_flag = HNS_ROCE_CEQ;
4316 eq->doorbell = hr_dev->reg_base +
4317 ROCEE_CAEP_CEQC_CONS_IDX_0_REG +
4318 CEQ_REG_OFFSET * i;
4319 eq->entries = hr_dev->caps.ceqe_depth;
4320 eq->log_entries = ilog2(eq->entries);
4321 eq->eqe_size = HNS_ROCE_CEQE_SIZE;
4322 } else {
4323 /* AEQ */
4324 eq_table->eqc_base[i] = hr_dev->reg_base +
4325 ROCEE_CAEP_AEQC_AEQE_SHIFT_REG;
4326 eq->type_flag = HNS_ROCE_AEQ;
4327 eq->doorbell = hr_dev->reg_base +
4328 ROCEE_CAEP_AEQE_CONS_IDX_REG;
4329 eq->entries = hr_dev->caps.aeqe_depth;
4330 eq->log_entries = ilog2(eq->entries);
4331 eq->eqe_size = HNS_ROCE_AEQE_SIZE;
4332 }
4333 }
4334
4335 /* Disable irq */
4336 hns_roce_v1_int_mask_enable(hr_dev);
4337
4338 /* Configure ce int interval */
4339 roce_write(hr_dev, ROCEE_CAEP_CE_INTERVAL_CFG_REG,
4340 HNS_ROCE_CEQ_DEFAULT_INTERVAL);
4341
4342 /* Configure ce int burst num */
4343 roce_write(hr_dev, ROCEE_CAEP_CE_BURST_NUM_CFG_REG,
4344 HNS_ROCE_CEQ_DEFAULT_BURST_NUM);
4345
4346 for (i = 0; i < eq_num; i++) {
4347 ret = hns_roce_v1_create_eq(hr_dev, &eq_table->eq[i]);
4348 if (ret) {
4349 dev_err(dev, "eq create failed\n");
4350 goto err_create_eq_fail;
4351 }
4352 }
4353
4354 for (j = 0; j < irq_num; j++) {
4355 if (j < eq_num)
4356 ret = request_irq(hr_dev->irq[j],
4357 hns_roce_v1_msix_interrupt_eq, 0,
4358 hr_dev->irq_names[j],
4359 &eq_table->eq[j]);
4360 else
4361 ret = request_irq(hr_dev->irq[j],
4362 hns_roce_v1_msix_interrupt_abn, 0,
4363 hr_dev->irq_names[j], hr_dev);
4364
4365 if (ret) {
4366 dev_err(dev, "request irq error!\n");
4367 goto err_request_irq_fail;
4368 }
4369 }
4370
4371 for (i = 0; i < eq_num; i++)
4372 hns_roce_v1_enable_eq(hr_dev, i, EQ_ENABLE);
4373
4374 return 0;
4375
4376 err_request_irq_fail:
4377 for (j -= 1; j >= 0; j--)
4378 free_irq(hr_dev->irq[j], &eq_table->eq[j]);
4379
4380 err_create_eq_fail:
4381 for (i -= 1; i >= 0; i--)
4382 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4383
4384 kfree(eq_table->eqc_base);
4385
4386 err_eqc_base_alloc_fail:
4387 kfree(eq_table->eq);
4388
4389 return ret;
4390 }
4391
hns_roce_v1_cleanup_eq_table(struct hns_roce_dev * hr_dev)4392 static void hns_roce_v1_cleanup_eq_table(struct hns_roce_dev *hr_dev)
4393 {
4394 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4395 int irq_num;
4396 int eq_num;
4397 int i;
4398
4399 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4400 irq_num = eq_num + hr_dev->caps.num_other_vectors;
4401 for (i = 0; i < eq_num; i++) {
4402 /* Disable EQ */
4403 hns_roce_v1_enable_eq(hr_dev, i, EQ_DISABLE);
4404
4405 free_irq(hr_dev->irq[i], &eq_table->eq[i]);
4406
4407 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4408 }
4409 for (i = eq_num; i < irq_num; i++)
4410 free_irq(hr_dev->irq[i], hr_dev);
4411
4412 kfree(eq_table->eqc_base);
4413 kfree(eq_table->eq);
4414 }
4415
4416 static const struct ib_device_ops hns_roce_v1_dev_ops = {
4417 .destroy_qp = hns_roce_v1_destroy_qp,
4418 .poll_cq = hns_roce_v1_poll_cq,
4419 .post_recv = hns_roce_v1_post_recv,
4420 .post_send = hns_roce_v1_post_send,
4421 .query_qp = hns_roce_v1_query_qp,
4422 .req_notify_cq = hns_roce_v1_req_notify_cq,
4423 };
4424
4425 static const struct hns_roce_hw hns_roce_hw_v1 = {
4426 .reset = hns_roce_v1_reset,
4427 .hw_profile = hns_roce_v1_profile,
4428 .hw_init = hns_roce_v1_init,
4429 .hw_exit = hns_roce_v1_exit,
4430 .post_mbox = hns_roce_v1_post_mbox,
4431 .chk_mbox = hns_roce_v1_chk_mbox,
4432 .set_gid = hns_roce_v1_set_gid,
4433 .set_mac = hns_roce_v1_set_mac,
4434 .set_mtu = hns_roce_v1_set_mtu,
4435 .write_mtpt = hns_roce_v1_write_mtpt,
4436 .write_cqc = hns_roce_v1_write_cqc,
4437 .set_hem = hns_roce_v1_set_hem,
4438 .clear_hem = hns_roce_v1_clear_hem,
4439 .modify_qp = hns_roce_v1_modify_qp,
4440 .query_qp = hns_roce_v1_query_qp,
4441 .destroy_qp = hns_roce_v1_destroy_qp,
4442 .post_send = hns_roce_v1_post_send,
4443 .post_recv = hns_roce_v1_post_recv,
4444 .req_notify_cq = hns_roce_v1_req_notify_cq,
4445 .poll_cq = hns_roce_v1_poll_cq,
4446 .dereg_mr = hns_roce_v1_dereg_mr,
4447 .destroy_cq = hns_roce_v1_destroy_cq,
4448 .init_eq = hns_roce_v1_init_eq_table,
4449 .cleanup_eq = hns_roce_v1_cleanup_eq_table,
4450 .hns_roce_dev_ops = &hns_roce_v1_dev_ops,
4451 };
4452
4453 static const struct of_device_id hns_roce_of_match[] = {
4454 { .compatible = "hisilicon,hns-roce-v1", .data = &hns_roce_hw_v1, },
4455 {},
4456 };
4457 MODULE_DEVICE_TABLE(of, hns_roce_of_match);
4458
4459 static const struct acpi_device_id hns_roce_acpi_match[] = {
4460 { "HISI00D1", (kernel_ulong_t)&hns_roce_hw_v1 },
4461 {},
4462 };
4463 MODULE_DEVICE_TABLE(acpi, hns_roce_acpi_match);
4464
4465 static struct
hns_roce_find_pdev(struct fwnode_handle * fwnode)4466 platform_device *hns_roce_find_pdev(struct fwnode_handle *fwnode)
4467 {
4468 struct device *dev;
4469
4470 /* get the 'device' corresponding to the matching 'fwnode' */
4471 dev = bus_find_device_by_fwnode(&platform_bus_type, fwnode);
4472 /* get the platform device */
4473 return dev ? to_platform_device(dev) : NULL;
4474 }
4475
hns_roce_get_cfg(struct hns_roce_dev * hr_dev)4476 static int hns_roce_get_cfg(struct hns_roce_dev *hr_dev)
4477 {
4478 struct device *dev = &hr_dev->pdev->dev;
4479 struct platform_device *pdev = NULL;
4480 struct net_device *netdev = NULL;
4481 struct device_node *net_node;
4482 int port_cnt = 0;
4483 u8 phy_port;
4484 int ret;
4485 int i;
4486
4487 /* check if we are compatible with the underlying SoC */
4488 if (dev_of_node(dev)) {
4489 const struct of_device_id *of_id;
4490
4491 of_id = of_match_node(hns_roce_of_match, dev->of_node);
4492 if (!of_id) {
4493 dev_err(dev, "device is not compatible!\n");
4494 return -ENXIO;
4495 }
4496 hr_dev->hw = (const struct hns_roce_hw *)of_id->data;
4497 if (!hr_dev->hw) {
4498 dev_err(dev, "couldn't get H/W specific DT data!\n");
4499 return -ENXIO;
4500 }
4501 } else if (is_acpi_device_node(dev->fwnode)) {
4502 const struct acpi_device_id *acpi_id;
4503
4504 acpi_id = acpi_match_device(hns_roce_acpi_match, dev);
4505 if (!acpi_id) {
4506 dev_err(dev, "device is not compatible!\n");
4507 return -ENXIO;
4508 }
4509 hr_dev->hw = (const struct hns_roce_hw *) acpi_id->driver_data;
4510 if (!hr_dev->hw) {
4511 dev_err(dev, "couldn't get H/W specific ACPI data!\n");
4512 return -ENXIO;
4513 }
4514 } else {
4515 dev_err(dev, "can't read compatibility data from DT or ACPI\n");
4516 return -ENXIO;
4517 }
4518
4519 /* get the mapped register base address */
4520 hr_dev->reg_base = devm_platform_ioremap_resource(hr_dev->pdev, 0);
4521 if (IS_ERR(hr_dev->reg_base))
4522 return PTR_ERR(hr_dev->reg_base);
4523
4524 /* read the node_guid of IB device from the DT or ACPI */
4525 ret = device_property_read_u8_array(dev, "node-guid",
4526 (u8 *)&hr_dev->ib_dev.node_guid,
4527 GUID_LEN);
4528 if (ret) {
4529 dev_err(dev, "couldn't get node_guid from DT or ACPI!\n");
4530 return ret;
4531 }
4532
4533 /* get the RoCE associated ethernet ports or netdevices */
4534 for (i = 0; i < HNS_ROCE_MAX_PORTS; i++) {
4535 if (dev_of_node(dev)) {
4536 net_node = of_parse_phandle(dev->of_node, "eth-handle",
4537 i);
4538 if (!net_node)
4539 continue;
4540 pdev = of_find_device_by_node(net_node);
4541 } else if (is_acpi_device_node(dev->fwnode)) {
4542 struct fwnode_reference_args args;
4543
4544 ret = acpi_node_get_property_reference(dev->fwnode,
4545 "eth-handle",
4546 i, &args);
4547 if (ret)
4548 continue;
4549 pdev = hns_roce_find_pdev(args.fwnode);
4550 } else {
4551 dev_err(dev, "cannot read data from DT or ACPI\n");
4552 return -ENXIO;
4553 }
4554
4555 if (pdev) {
4556 netdev = platform_get_drvdata(pdev);
4557 phy_port = (u8)i;
4558 if (netdev) {
4559 hr_dev->iboe.netdevs[port_cnt] = netdev;
4560 hr_dev->iboe.phy_port[port_cnt] = phy_port;
4561 } else {
4562 dev_err(dev, "no netdev found with pdev %s\n",
4563 pdev->name);
4564 return -ENODEV;
4565 }
4566 port_cnt++;
4567 }
4568 }
4569
4570 if (port_cnt == 0) {
4571 dev_err(dev, "unable to get eth-handle for available ports!\n");
4572 return -EINVAL;
4573 }
4574
4575 hr_dev->caps.num_ports = port_cnt;
4576
4577 /* cmd issue mode: 0 is poll, 1 is event */
4578 hr_dev->cmd_mod = 1;
4579 hr_dev->loop_idc = 0;
4580 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
4581 hr_dev->odb_offset = ROCEE_DB_OTHERS_L_0_REG;
4582
4583 /* read the interrupt names from the DT or ACPI */
4584 ret = device_property_read_string_array(dev, "interrupt-names",
4585 hr_dev->irq_names,
4586 HNS_ROCE_V1_MAX_IRQ_NUM);
4587 if (ret < 0) {
4588 dev_err(dev, "couldn't get interrupt names from DT or ACPI!\n");
4589 return ret;
4590 }
4591
4592 /* fetch the interrupt numbers */
4593 for (i = 0; i < HNS_ROCE_V1_MAX_IRQ_NUM; i++) {
4594 hr_dev->irq[i] = platform_get_irq(hr_dev->pdev, i);
4595 if (hr_dev->irq[i] <= 0)
4596 return -EINVAL;
4597 }
4598
4599 return 0;
4600 }
4601
4602 /**
4603 * hns_roce_probe - RoCE driver entrance
4604 * @pdev: pointer to platform device
4605 * Return : int
4606 *
4607 */
hns_roce_probe(struct platform_device * pdev)4608 static int hns_roce_probe(struct platform_device *pdev)
4609 {
4610 int ret;
4611 struct hns_roce_dev *hr_dev;
4612 struct device *dev = &pdev->dev;
4613
4614 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
4615 if (!hr_dev)
4616 return -ENOMEM;
4617
4618 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v1_priv), GFP_KERNEL);
4619 if (!hr_dev->priv) {
4620 ret = -ENOMEM;
4621 goto error_failed_kzalloc;
4622 }
4623
4624 hr_dev->pdev = pdev;
4625 hr_dev->dev = dev;
4626 platform_set_drvdata(pdev, hr_dev);
4627
4628 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64ULL)) &&
4629 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32ULL))) {
4630 dev_err(dev, "Not usable DMA addressing mode\n");
4631 ret = -EIO;
4632 goto error_failed_get_cfg;
4633 }
4634
4635 ret = hns_roce_get_cfg(hr_dev);
4636 if (ret) {
4637 dev_err(dev, "Get Configuration failed!\n");
4638 goto error_failed_get_cfg;
4639 }
4640
4641 ret = hns_roce_init(hr_dev);
4642 if (ret) {
4643 dev_err(dev, "RoCE engine init failed!\n");
4644 goto error_failed_get_cfg;
4645 }
4646
4647 return 0;
4648
4649 error_failed_get_cfg:
4650 kfree(hr_dev->priv);
4651
4652 error_failed_kzalloc:
4653 ib_dealloc_device(&hr_dev->ib_dev);
4654
4655 return ret;
4656 }
4657
4658 /**
4659 * hns_roce_remove - remove RoCE device
4660 * @pdev: pointer to platform device
4661 */
hns_roce_remove(struct platform_device * pdev)4662 static int hns_roce_remove(struct platform_device *pdev)
4663 {
4664 struct hns_roce_dev *hr_dev = platform_get_drvdata(pdev);
4665
4666 hns_roce_exit(hr_dev);
4667 kfree(hr_dev->priv);
4668 ib_dealloc_device(&hr_dev->ib_dev);
4669
4670 return 0;
4671 }
4672
4673 static struct platform_driver hns_roce_driver = {
4674 .probe = hns_roce_probe,
4675 .remove = hns_roce_remove,
4676 .driver = {
4677 .name = DRV_NAME,
4678 .of_match_table = hns_roce_of_match,
4679 .acpi_match_table = ACPI_PTR(hns_roce_acpi_match),
4680 },
4681 };
4682
4683 module_platform_driver(hns_roce_driver);
4684
4685 MODULE_LICENSE("Dual BSD/GPL");
4686 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
4687 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
4688 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
4689 MODULE_DESCRIPTION("Hisilicon Hip06 Family RoCE Driver");
4690