1 /*
2 * Copyright (c) 2016 Hisilicon Limited.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33 #include <linux/acpi.h>
34 #include <linux/of_platform.h>
35 #include <linux/module.h>
36 #include <rdma/ib_addr.h>
37 #include <rdma/ib_smi.h>
38 #include <rdma/ib_user_verbs.h>
39 #include <rdma/ib_cache.h>
40 #include "hns_roce_common.h"
41 #include "hns_roce_device.h"
42 #include <rdma/hns-abi.h>
43 #include "hns_roce_hem.h"
44
45 /**
46 * hns_get_gid_index - Get gid index.
47 * @hr_dev: pointer to structure hns_roce_dev.
48 * @port: port, value range: 0 ~ MAX
49 * @gid_index: gid_index, value range: 0 ~ MAX
50 * Description:
51 * N ports shared gids, allocation method as follow:
52 * GID[0][0], GID[1][0],.....GID[N - 1][0],
53 * GID[0][0], GID[1][0],.....GID[N - 1][0],
54 * And so on
55 */
hns_get_gid_index(struct hns_roce_dev * hr_dev,u8 port,int gid_index)56 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index)
57 {
58 return gid_index * hr_dev->caps.num_ports + port;
59 }
60
hns_roce_set_mac(struct hns_roce_dev * hr_dev,u8 port,u8 * addr)61 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr)
62 {
63 u8 phy_port;
64 u32 i = 0;
65
66 if (!memcmp(hr_dev->dev_addr[port], addr, ETH_ALEN))
67 return 0;
68
69 for (i = 0; i < ETH_ALEN; i++)
70 hr_dev->dev_addr[port][i] = addr[i];
71
72 phy_port = hr_dev->iboe.phy_port[port];
73 return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
74 }
75
hns_roce_add_gid(const struct ib_gid_attr * attr,void ** context)76 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context)
77 {
78 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
79 u8 port = attr->port_num - 1;
80 int ret;
81
82 if (port >= hr_dev->caps.num_ports)
83 return -EINVAL;
84
85 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &attr->gid, attr);
86
87 return ret;
88 }
89
hns_roce_del_gid(const struct ib_gid_attr * attr,void ** context)90 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context)
91 {
92 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
93 struct ib_gid_attr zattr = {};
94 u8 port = attr->port_num - 1;
95 int ret;
96
97 if (port >= hr_dev->caps.num_ports)
98 return -EINVAL;
99
100 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &zgid, &zattr);
101
102 return ret;
103 }
104
handle_en_event(struct hns_roce_dev * hr_dev,u8 port,unsigned long event)105 static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port,
106 unsigned long event)
107 {
108 struct device *dev = hr_dev->dev;
109 struct net_device *netdev;
110 int ret = 0;
111
112 netdev = hr_dev->iboe.netdevs[port];
113 if (!netdev) {
114 dev_err(dev, "Can't find netdev on port(%u)!\n", port);
115 return -ENODEV;
116 }
117
118 switch (event) {
119 case NETDEV_UP:
120 case NETDEV_CHANGE:
121 case NETDEV_REGISTER:
122 case NETDEV_CHANGEADDR:
123 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
124 break;
125 case NETDEV_DOWN:
126 /*
127 * In v1 engine, only support all ports closed together.
128 */
129 break;
130 default:
131 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
132 break;
133 }
134
135 return ret;
136 }
137
hns_roce_netdev_event(struct notifier_block * self,unsigned long event,void * ptr)138 static int hns_roce_netdev_event(struct notifier_block *self,
139 unsigned long event, void *ptr)
140 {
141 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
142 struct hns_roce_ib_iboe *iboe = NULL;
143 struct hns_roce_dev *hr_dev = NULL;
144 int ret;
145 u8 port;
146
147 hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
148 iboe = &hr_dev->iboe;
149
150 for (port = 0; port < hr_dev->caps.num_ports; port++) {
151 if (dev == iboe->netdevs[port]) {
152 ret = handle_en_event(hr_dev, port, event);
153 if (ret)
154 return NOTIFY_DONE;
155 break;
156 }
157 }
158
159 return NOTIFY_DONE;
160 }
161
hns_roce_setup_mtu_mac(struct hns_roce_dev * hr_dev)162 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
163 {
164 int ret;
165 u8 i;
166
167 for (i = 0; i < hr_dev->caps.num_ports; i++) {
168 if (hr_dev->hw->set_mtu)
169 hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i],
170 hr_dev->caps.max_mtu);
171 ret = hns_roce_set_mac(hr_dev, i,
172 hr_dev->iboe.netdevs[i]->dev_addr);
173 if (ret)
174 return ret;
175 }
176
177 return 0;
178 }
179
hns_roce_query_device(struct ib_device * ib_dev,struct ib_device_attr * props,struct ib_udata * uhw)180 static int hns_roce_query_device(struct ib_device *ib_dev,
181 struct ib_device_attr *props,
182 struct ib_udata *uhw)
183 {
184 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
185
186 memset(props, 0, sizeof(*props));
187
188 props->fw_ver = hr_dev->caps.fw_ver;
189 props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid);
190 props->max_mr_size = (u64)(~(0ULL));
191 props->page_size_cap = hr_dev->caps.page_size_cap;
192 props->vendor_id = hr_dev->vendor_id;
193 props->vendor_part_id = hr_dev->vendor_part_id;
194 props->hw_ver = hr_dev->hw_rev;
195 props->max_qp = hr_dev->caps.num_qps;
196 props->max_qp_wr = hr_dev->caps.max_wqes;
197 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
198 IB_DEVICE_RC_RNR_NAK_GEN;
199 props->max_send_sge = hr_dev->caps.max_sq_sg;
200 props->max_recv_sge = hr_dev->caps.max_rq_sg;
201 props->max_sge_rd = 1;
202 props->max_cq = hr_dev->caps.num_cqs;
203 props->max_cqe = hr_dev->caps.max_cqes;
204 props->max_mr = hr_dev->caps.num_mtpts;
205 props->max_pd = hr_dev->caps.num_pds;
206 props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
207 props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
208 props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ?
209 IB_ATOMIC_HCA : IB_ATOMIC_NONE;
210 props->max_pkeys = 1;
211 props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
212 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
213 props->max_srq = hr_dev->caps.num_srqs;
214 props->max_srq_wr = hr_dev->caps.max_srq_wrs;
215 props->max_srq_sge = hr_dev->caps.max_srq_sges;
216 }
217
218 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR) {
219 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
220 props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA;
221 }
222
223 return 0;
224 }
225
hns_roce_query_port(struct ib_device * ib_dev,u8 port_num,struct ib_port_attr * props)226 static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num,
227 struct ib_port_attr *props)
228 {
229 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
230 struct device *dev = hr_dev->dev;
231 struct net_device *net_dev;
232 unsigned long flags;
233 enum ib_mtu mtu;
234 u8 port;
235
236 port = port_num - 1;
237
238 /* props being zeroed by the caller, avoid zeroing it here */
239
240 props->max_mtu = hr_dev->caps.max_mtu;
241 props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
242 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
243 IB_PORT_VENDOR_CLASS_SUP |
244 IB_PORT_BOOT_MGMT_SUP;
245 props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
246 props->pkey_tbl_len = 1;
247 props->active_width = IB_WIDTH_4X;
248 props->active_speed = 1;
249
250 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
251
252 net_dev = hr_dev->iboe.netdevs[port];
253 if (!net_dev) {
254 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
255 dev_err(dev, "Find netdev %u failed!\n", port);
256 return -EINVAL;
257 }
258
259 mtu = iboe_get_mtu(net_dev->mtu);
260 props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
261 props->state = netif_running(net_dev) && netif_carrier_ok(net_dev) ?
262 IB_PORT_ACTIVE :
263 IB_PORT_DOWN;
264 props->phys_state = props->state == IB_PORT_ACTIVE ?
265 IB_PORT_PHYS_STATE_LINK_UP :
266 IB_PORT_PHYS_STATE_DISABLED;
267
268 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
269
270 return 0;
271 }
272
hns_roce_get_link_layer(struct ib_device * device,u8 port_num)273 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
274 u8 port_num)
275 {
276 return IB_LINK_LAYER_ETHERNET;
277 }
278
hns_roce_query_pkey(struct ib_device * ib_dev,u8 port,u16 index,u16 * pkey)279 static int hns_roce_query_pkey(struct ib_device *ib_dev, u8 port, u16 index,
280 u16 *pkey)
281 {
282 if (index > 0)
283 return -EINVAL;
284
285 *pkey = PKEY_ID;
286
287 return 0;
288 }
289
hns_roce_modify_device(struct ib_device * ib_dev,int mask,struct ib_device_modify * props)290 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
291 struct ib_device_modify *props)
292 {
293 unsigned long flags;
294
295 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
296 return -EOPNOTSUPP;
297
298 if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
299 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
300 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
301 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
302 }
303
304 return 0;
305 }
306
hns_roce_alloc_ucontext(struct ib_ucontext * uctx,struct ib_udata * udata)307 static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx,
308 struct ib_udata *udata)
309 {
310 int ret;
311 struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
312 struct hns_roce_ib_alloc_ucontext_resp resp = {};
313 struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device);
314
315 if (!hr_dev->active)
316 return -EAGAIN;
317
318 resp.qp_tab_size = hr_dev->caps.num_qps;
319
320 ret = hns_roce_uar_alloc(hr_dev, &context->uar);
321 if (ret)
322 goto error_fail_uar_alloc;
323
324 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) {
325 INIT_LIST_HEAD(&context->page_list);
326 mutex_init(&context->page_mutex);
327 }
328
329 resp.cqe_size = hr_dev->caps.cqe_sz;
330
331 ret = ib_copy_to_udata(udata, &resp,
332 min(udata->outlen, sizeof(resp)));
333 if (ret)
334 goto error_fail_copy_to_udata;
335
336 return 0;
337
338 error_fail_copy_to_udata:
339 hns_roce_uar_free(hr_dev, &context->uar);
340
341 error_fail_uar_alloc:
342 return ret;
343 }
344
hns_roce_dealloc_ucontext(struct ib_ucontext * ibcontext)345 static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
346 {
347 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
348
349 hns_roce_uar_free(to_hr_dev(ibcontext->device), &context->uar);
350 }
351
hns_roce_mmap(struct ib_ucontext * context,struct vm_area_struct * vma)352 static int hns_roce_mmap(struct ib_ucontext *context,
353 struct vm_area_struct *vma)
354 {
355 struct hns_roce_dev *hr_dev = to_hr_dev(context->device);
356
357 switch (vma->vm_pgoff) {
358 case 0:
359 return rdma_user_mmap_io(context, vma,
360 to_hr_ucontext(context)->uar.pfn,
361 PAGE_SIZE,
362 pgprot_device(vma->vm_page_prot),
363 NULL);
364
365 /* vm_pgoff: 1 -- TPTR */
366 case 1:
367 if (!hr_dev->tptr_dma_addr || !hr_dev->tptr_size)
368 return -EINVAL;
369 /*
370 * FIXME: using io_remap_pfn_range on the dma address returned
371 * by dma_alloc_coherent is totally wrong.
372 */
373 return rdma_user_mmap_io(context, vma,
374 hr_dev->tptr_dma_addr >> PAGE_SHIFT,
375 hr_dev->tptr_size,
376 vma->vm_page_prot,
377 NULL);
378
379 default:
380 return -EINVAL;
381 }
382 }
383
hns_roce_port_immutable(struct ib_device * ib_dev,u8 port_num,struct ib_port_immutable * immutable)384 static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num,
385 struct ib_port_immutable *immutable)
386 {
387 struct ib_port_attr attr;
388 int ret;
389
390 ret = ib_query_port(ib_dev, port_num, &attr);
391 if (ret)
392 return ret;
393
394 immutable->pkey_tbl_len = attr.pkey_tbl_len;
395 immutable->gid_tbl_len = attr.gid_tbl_len;
396
397 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
398 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
399 if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2)
400 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
401
402 return 0;
403 }
404
hns_roce_disassociate_ucontext(struct ib_ucontext * ibcontext)405 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext)
406 {
407 }
408
hns_roce_unregister_device(struct hns_roce_dev * hr_dev)409 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
410 {
411 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
412
413 hr_dev->active = false;
414 unregister_netdevice_notifier(&iboe->nb);
415 ib_unregister_device(&hr_dev->ib_dev);
416 }
417
418 static const struct ib_device_ops hns_roce_dev_ops = {
419 .owner = THIS_MODULE,
420 .driver_id = RDMA_DRIVER_HNS,
421 .uverbs_abi_ver = 1,
422 .uverbs_no_driver_id_binding = 1,
423
424 .add_gid = hns_roce_add_gid,
425 .alloc_pd = hns_roce_alloc_pd,
426 .alloc_ucontext = hns_roce_alloc_ucontext,
427 .create_ah = hns_roce_create_ah,
428 .create_cq = hns_roce_create_cq,
429 .create_qp = hns_roce_create_qp,
430 .dealloc_pd = hns_roce_dealloc_pd,
431 .dealloc_ucontext = hns_roce_dealloc_ucontext,
432 .del_gid = hns_roce_del_gid,
433 .dereg_mr = hns_roce_dereg_mr,
434 .destroy_ah = hns_roce_destroy_ah,
435 .destroy_cq = hns_roce_destroy_cq,
436 .disassociate_ucontext = hns_roce_disassociate_ucontext,
437 .fill_res_cq_entry = hns_roce_fill_res_cq_entry,
438 .get_dma_mr = hns_roce_get_dma_mr,
439 .get_link_layer = hns_roce_get_link_layer,
440 .get_port_immutable = hns_roce_port_immutable,
441 .mmap = hns_roce_mmap,
442 .modify_device = hns_roce_modify_device,
443 .modify_qp = hns_roce_modify_qp,
444 .query_ah = hns_roce_query_ah,
445 .query_device = hns_roce_query_device,
446 .query_pkey = hns_roce_query_pkey,
447 .query_port = hns_roce_query_port,
448 .reg_user_mr = hns_roce_reg_user_mr,
449
450 INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah),
451 INIT_RDMA_OBJ_SIZE(ib_cq, hns_roce_cq, ib_cq),
452 INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd),
453 INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext),
454 };
455
456 static const struct ib_device_ops hns_roce_dev_mr_ops = {
457 .rereg_user_mr = hns_roce_rereg_user_mr,
458 };
459
460 static const struct ib_device_ops hns_roce_dev_mw_ops = {
461 .alloc_mw = hns_roce_alloc_mw,
462 .dealloc_mw = hns_roce_dealloc_mw,
463
464 INIT_RDMA_OBJ_SIZE(ib_mw, hns_roce_mw, ibmw),
465 };
466
467 static const struct ib_device_ops hns_roce_dev_frmr_ops = {
468 .alloc_mr = hns_roce_alloc_mr,
469 .map_mr_sg = hns_roce_map_mr_sg,
470 };
471
472 static const struct ib_device_ops hns_roce_dev_srq_ops = {
473 .create_srq = hns_roce_create_srq,
474 .destroy_srq = hns_roce_destroy_srq,
475
476 INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq),
477 };
478
hns_roce_register_device(struct hns_roce_dev * hr_dev)479 static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
480 {
481 int ret;
482 struct hns_roce_ib_iboe *iboe = NULL;
483 struct ib_device *ib_dev = NULL;
484 struct device *dev = hr_dev->dev;
485 unsigned int i;
486
487 iboe = &hr_dev->iboe;
488 spin_lock_init(&iboe->lock);
489
490 ib_dev = &hr_dev->ib_dev;
491
492 ib_dev->node_type = RDMA_NODE_IB_CA;
493 ib_dev->dev.parent = dev;
494
495 ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
496 ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
497 ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
498 ib_dev->uverbs_cmd_mask =
499 (1ULL << IB_USER_VERBS_CMD_GET_CONTEXT) |
500 (1ULL << IB_USER_VERBS_CMD_QUERY_DEVICE) |
501 (1ULL << IB_USER_VERBS_CMD_QUERY_PORT) |
502 (1ULL << IB_USER_VERBS_CMD_ALLOC_PD) |
503 (1ULL << IB_USER_VERBS_CMD_DEALLOC_PD) |
504 (1ULL << IB_USER_VERBS_CMD_REG_MR) |
505 (1ULL << IB_USER_VERBS_CMD_DEREG_MR) |
506 (1ULL << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
507 (1ULL << IB_USER_VERBS_CMD_CREATE_CQ) |
508 (1ULL << IB_USER_VERBS_CMD_DESTROY_CQ) |
509 (1ULL << IB_USER_VERBS_CMD_CREATE_QP) |
510 (1ULL << IB_USER_VERBS_CMD_MODIFY_QP) |
511 (1ULL << IB_USER_VERBS_CMD_QUERY_QP) |
512 (1ULL << IB_USER_VERBS_CMD_DESTROY_QP);
513
514 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) {
515 ib_dev->uverbs_cmd_mask |= (1ULL << IB_USER_VERBS_CMD_REREG_MR);
516 ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops);
517 }
518
519 /* MW */
520 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW) {
521 ib_dev->uverbs_cmd_mask |=
522 (1ULL << IB_USER_VERBS_CMD_ALLOC_MW) |
523 (1ULL << IB_USER_VERBS_CMD_DEALLOC_MW);
524 ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops);
525 }
526
527 /* FRMR */
528 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR)
529 ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops);
530
531 /* SRQ */
532 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
533 ib_dev->uverbs_cmd_mask |=
534 (1ULL << IB_USER_VERBS_CMD_CREATE_SRQ) |
535 (1ULL << IB_USER_VERBS_CMD_MODIFY_SRQ) |
536 (1ULL << IB_USER_VERBS_CMD_QUERY_SRQ) |
537 (1ULL << IB_USER_VERBS_CMD_DESTROY_SRQ) |
538 (1ULL << IB_USER_VERBS_CMD_POST_SRQ_RECV);
539 ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops);
540 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops);
541 }
542
543 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops);
544 ib_set_device_ops(ib_dev, &hns_roce_dev_ops);
545 for (i = 0; i < hr_dev->caps.num_ports; i++) {
546 if (!hr_dev->iboe.netdevs[i])
547 continue;
548
549 ret = ib_device_set_netdev(ib_dev, hr_dev->iboe.netdevs[i],
550 i + 1);
551 if (ret)
552 return ret;
553 }
554 dma_set_max_seg_size(dev, UINT_MAX);
555 ret = ib_register_device(ib_dev, "hns_%d", dev);
556 if (ret) {
557 dev_err(dev, "ib_register_device failed!\n");
558 return ret;
559 }
560
561 ret = hns_roce_setup_mtu_mac(hr_dev);
562 if (ret) {
563 dev_err(dev, "setup_mtu_mac failed!\n");
564 goto error_failed_setup_mtu_mac;
565 }
566
567 iboe->nb.notifier_call = hns_roce_netdev_event;
568 ret = register_netdevice_notifier(&iboe->nb);
569 if (ret) {
570 dev_err(dev, "register_netdevice_notifier failed!\n");
571 goto error_failed_setup_mtu_mac;
572 }
573
574 hr_dev->active = true;
575 return 0;
576
577 error_failed_setup_mtu_mac:
578 ib_unregister_device(ib_dev);
579
580 return ret;
581 }
582
hns_roce_init_hem(struct hns_roce_dev * hr_dev)583 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
584 {
585 struct device *dev = hr_dev->dev;
586 int ret;
587
588 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
589 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
590 hr_dev->caps.num_mtpts, 1);
591 if (ret) {
592 dev_err(dev, "Failed to init MTPT context memory, aborting.\n");
593 return ret;
594 }
595
596 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
597 HEM_TYPE_QPC, hr_dev->caps.qpc_sz,
598 hr_dev->caps.num_qps, 1);
599 if (ret) {
600 dev_err(dev, "Failed to init QP context memory, aborting.\n");
601 goto err_unmap_dmpt;
602 }
603
604 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
605 HEM_TYPE_IRRL,
606 hr_dev->caps.irrl_entry_sz *
607 hr_dev->caps.max_qp_init_rdma,
608 hr_dev->caps.num_qps, 1);
609 if (ret) {
610 dev_err(dev, "Failed to init irrl_table memory, aborting.\n");
611 goto err_unmap_qp;
612 }
613
614 if (hr_dev->caps.trrl_entry_sz) {
615 ret = hns_roce_init_hem_table(hr_dev,
616 &hr_dev->qp_table.trrl_table,
617 HEM_TYPE_TRRL,
618 hr_dev->caps.trrl_entry_sz *
619 hr_dev->caps.max_qp_dest_rdma,
620 hr_dev->caps.num_qps, 1);
621 if (ret) {
622 dev_err(dev,
623 "Failed to init trrl_table memory, aborting.\n");
624 goto err_unmap_irrl;
625 }
626 }
627
628 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
629 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
630 hr_dev->caps.num_cqs, 1);
631 if (ret) {
632 dev_err(dev, "Failed to init CQ context memory, aborting.\n");
633 goto err_unmap_trrl;
634 }
635
636 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
637 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table,
638 HEM_TYPE_SRQC,
639 hr_dev->caps.srqc_entry_sz,
640 hr_dev->caps.num_srqs, 1);
641 if (ret) {
642 dev_err(dev,
643 "Failed to init SRQ context memory, aborting.\n");
644 goto err_unmap_cq;
645 }
646 }
647
648 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) {
649 ret = hns_roce_init_hem_table(hr_dev,
650 &hr_dev->qp_table.sccc_table,
651 HEM_TYPE_SCCC,
652 hr_dev->caps.sccc_sz,
653 hr_dev->caps.num_qps, 1);
654 if (ret) {
655 dev_err(dev,
656 "Failed to init SCC context memory, aborting.\n");
657 goto err_unmap_srq;
658 }
659 }
660
661 if (hr_dev->caps.qpc_timer_entry_sz) {
662 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qpc_timer_table,
663 HEM_TYPE_QPC_TIMER,
664 hr_dev->caps.qpc_timer_entry_sz,
665 hr_dev->caps.num_qpc_timer, 1);
666 if (ret) {
667 dev_err(dev,
668 "Failed to init QPC timer memory, aborting.\n");
669 goto err_unmap_ctx;
670 }
671 }
672
673 if (hr_dev->caps.cqc_timer_entry_sz) {
674 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cqc_timer_table,
675 HEM_TYPE_CQC_TIMER,
676 hr_dev->caps.cqc_timer_entry_sz,
677 hr_dev->caps.num_cqc_timer, 1);
678 if (ret) {
679 dev_err(dev,
680 "Failed to init CQC timer memory, aborting.\n");
681 goto err_unmap_qpc_timer;
682 }
683 }
684
685 return 0;
686
687 err_unmap_qpc_timer:
688 if (hr_dev->caps.qpc_timer_entry_sz)
689 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qpc_timer_table);
690
691 err_unmap_ctx:
692 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
693 hns_roce_cleanup_hem_table(hr_dev,
694 &hr_dev->qp_table.sccc_table);
695 err_unmap_srq:
696 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
697 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table);
698
699 err_unmap_cq:
700 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);
701
702 err_unmap_trrl:
703 if (hr_dev->caps.trrl_entry_sz)
704 hns_roce_cleanup_hem_table(hr_dev,
705 &hr_dev->qp_table.trrl_table);
706
707 err_unmap_irrl:
708 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
709
710 err_unmap_qp:
711 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
712
713 err_unmap_dmpt:
714 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
715
716 return ret;
717 }
718
719 /**
720 * hns_roce_setup_hca - setup host channel adapter
721 * @hr_dev: pointer to hns roce device
722 * Return : int
723 */
hns_roce_setup_hca(struct hns_roce_dev * hr_dev)724 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
725 {
726 struct device *dev = hr_dev->dev;
727 int ret;
728
729 spin_lock_init(&hr_dev->sm_lock);
730 spin_lock_init(&hr_dev->bt_cmd_lock);
731
732 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) {
733 INIT_LIST_HEAD(&hr_dev->pgdir_list);
734 mutex_init(&hr_dev->pgdir_mutex);
735 }
736
737 ret = hns_roce_init_uar_table(hr_dev);
738 if (ret) {
739 dev_err(dev, "Failed to initialize uar table. aborting\n");
740 return ret;
741 }
742
743 ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
744 if (ret) {
745 dev_err(dev, "Failed to allocate priv_uar.\n");
746 goto err_uar_table_free;
747 }
748
749 ret = hns_roce_init_pd_table(hr_dev);
750 if (ret) {
751 dev_err(dev, "Failed to init protected domain table.\n");
752 goto err_uar_alloc_free;
753 }
754
755 ret = hns_roce_init_mr_table(hr_dev);
756 if (ret) {
757 dev_err(dev, "Failed to init memory region table.\n");
758 goto err_pd_table_free;
759 }
760
761 ret = hns_roce_init_cq_table(hr_dev);
762 if (ret) {
763 dev_err(dev, "Failed to init completion queue table.\n");
764 goto err_mr_table_free;
765 }
766
767 ret = hns_roce_init_qp_table(hr_dev);
768 if (ret) {
769 dev_err(dev, "Failed to init queue pair table.\n");
770 goto err_cq_table_free;
771 }
772
773 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
774 ret = hns_roce_init_srq_table(hr_dev);
775 if (ret) {
776 dev_err(dev,
777 "Failed to init share receive queue table.\n");
778 goto err_qp_table_free;
779 }
780 }
781
782 return 0;
783
784 err_qp_table_free:
785 hns_roce_cleanup_qp_table(hr_dev);
786
787 err_cq_table_free:
788 hns_roce_cleanup_cq_table(hr_dev);
789
790 err_mr_table_free:
791 hns_roce_cleanup_mr_table(hr_dev);
792
793 err_pd_table_free:
794 hns_roce_cleanup_pd_table(hr_dev);
795
796 err_uar_alloc_free:
797 hns_roce_uar_free(hr_dev, &hr_dev->priv_uar);
798
799 err_uar_table_free:
800 hns_roce_cleanup_uar_table(hr_dev);
801 return ret;
802 }
803
check_and_get_armed_cq(struct list_head * cq_list,struct ib_cq * cq)804 static void check_and_get_armed_cq(struct list_head *cq_list, struct ib_cq *cq)
805 {
806 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
807 unsigned long flags;
808
809 spin_lock_irqsave(&hr_cq->lock, flags);
810 if (cq->comp_handler) {
811 if (!hr_cq->is_armed) {
812 hr_cq->is_armed = 1;
813 list_add_tail(&hr_cq->node, cq_list);
814 }
815 }
816 spin_unlock_irqrestore(&hr_cq->lock, flags);
817 }
818
hns_roce_handle_device_err(struct hns_roce_dev * hr_dev)819 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev)
820 {
821 struct hns_roce_qp *hr_qp;
822 struct hns_roce_cq *hr_cq;
823 struct list_head cq_list;
824 unsigned long flags_qp;
825 unsigned long flags;
826
827 INIT_LIST_HEAD(&cq_list);
828
829 spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
830 list_for_each_entry(hr_qp, &hr_dev->qp_list, node) {
831 spin_lock_irqsave(&hr_qp->sq.lock, flags_qp);
832 if (hr_qp->sq.tail != hr_qp->sq.head)
833 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.send_cq);
834 spin_unlock_irqrestore(&hr_qp->sq.lock, flags_qp);
835
836 spin_lock_irqsave(&hr_qp->rq.lock, flags_qp);
837 if ((!hr_qp->ibqp.srq) && (hr_qp->rq.tail != hr_qp->rq.head))
838 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.recv_cq);
839 spin_unlock_irqrestore(&hr_qp->rq.lock, flags_qp);
840 }
841
842 list_for_each_entry(hr_cq, &cq_list, node)
843 hns_roce_cq_completion(hr_dev, hr_cq->cqn);
844
845 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
846 }
847
hns_roce_init(struct hns_roce_dev * hr_dev)848 int hns_roce_init(struct hns_roce_dev *hr_dev)
849 {
850 struct device *dev = hr_dev->dev;
851 int ret;
852
853 if (hr_dev->hw->reset) {
854 ret = hr_dev->hw->reset(hr_dev, true);
855 if (ret) {
856 dev_err(dev, "Reset RoCE engine failed!\n");
857 return ret;
858 }
859 }
860 hr_dev->is_reset = false;
861
862 if (hr_dev->hw->cmq_init) {
863 ret = hr_dev->hw->cmq_init(hr_dev);
864 if (ret) {
865 dev_err(dev, "Init RoCE Command Queue failed!\n");
866 goto error_failed_cmq_init;
867 }
868 }
869
870 ret = hr_dev->hw->hw_profile(hr_dev);
871 if (ret) {
872 dev_err(dev, "Get RoCE engine profile failed!\n");
873 goto error_failed_cmd_init;
874 }
875
876 ret = hns_roce_cmd_init(hr_dev);
877 if (ret) {
878 dev_err(dev, "cmd init failed!\n");
879 goto error_failed_cmd_init;
880 }
881
882 /* EQ depends on poll mode, event mode depends on EQ */
883 ret = hr_dev->hw->init_eq(hr_dev);
884 if (ret) {
885 dev_err(dev, "eq init failed!\n");
886 goto error_failed_eq_table;
887 }
888
889 if (hr_dev->cmd_mod) {
890 ret = hns_roce_cmd_use_events(hr_dev);
891 if (ret) {
892 dev_warn(dev,
893 "Cmd event mode failed, set back to poll!\n");
894 hns_roce_cmd_use_polling(hr_dev);
895 }
896 }
897
898 ret = hns_roce_init_hem(hr_dev);
899 if (ret) {
900 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
901 goto error_failed_init_hem;
902 }
903
904 ret = hns_roce_setup_hca(hr_dev);
905 if (ret) {
906 dev_err(dev, "setup hca failed!\n");
907 goto error_failed_setup_hca;
908 }
909
910 if (hr_dev->hw->hw_init) {
911 ret = hr_dev->hw->hw_init(hr_dev);
912 if (ret) {
913 dev_err(dev, "hw_init failed!\n");
914 goto error_failed_engine_init;
915 }
916 }
917
918 INIT_LIST_HEAD(&hr_dev->qp_list);
919 spin_lock_init(&hr_dev->qp_list_lock);
920
921 ret = hns_roce_register_device(hr_dev);
922 if (ret)
923 goto error_failed_register_device;
924
925 return 0;
926
927 error_failed_register_device:
928 if (hr_dev->hw->hw_exit)
929 hr_dev->hw->hw_exit(hr_dev);
930
931 error_failed_engine_init:
932 hns_roce_cleanup_bitmap(hr_dev);
933
934 error_failed_setup_hca:
935 hns_roce_cleanup_hem(hr_dev);
936
937 error_failed_init_hem:
938 if (hr_dev->cmd_mod)
939 hns_roce_cmd_use_polling(hr_dev);
940 hr_dev->hw->cleanup_eq(hr_dev);
941
942 error_failed_eq_table:
943 hns_roce_cmd_cleanup(hr_dev);
944
945 error_failed_cmd_init:
946 if (hr_dev->hw->cmq_exit)
947 hr_dev->hw->cmq_exit(hr_dev);
948
949 error_failed_cmq_init:
950 if (hr_dev->hw->reset) {
951 if (hr_dev->hw->reset(hr_dev, false))
952 dev_err(dev, "Dereset RoCE engine failed!\n");
953 }
954
955 return ret;
956 }
957
hns_roce_exit(struct hns_roce_dev * hr_dev)958 void hns_roce_exit(struct hns_roce_dev *hr_dev)
959 {
960 hns_roce_unregister_device(hr_dev);
961
962 if (hr_dev->hw->hw_exit)
963 hr_dev->hw->hw_exit(hr_dev);
964 hns_roce_cleanup_bitmap(hr_dev);
965 hns_roce_cleanup_hem(hr_dev);
966
967 if (hr_dev->cmd_mod)
968 hns_roce_cmd_use_polling(hr_dev);
969
970 hr_dev->hw->cleanup_eq(hr_dev);
971 hns_roce_cmd_cleanup(hr_dev);
972 if (hr_dev->hw->cmq_exit)
973 hr_dev->hw->cmq_exit(hr_dev);
974 if (hr_dev->hw->reset)
975 hr_dev->hw->reset(hr_dev, false);
976 }
977
978 MODULE_LICENSE("Dual BSD/GPL");
979 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
980 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
981 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
982 MODULE_DESCRIPTION("HNS RoCE Driver");
983