1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2020 Intel Corporation.
3
4 #include <asm/unaligned.h>
5 #include <linux/acpi.h>
6 #include <linux/delay.h>
7 #include <linux/i2c.h>
8 #include <linux/module.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/nvmem-provider.h>
11 #include <linux/regmap.h>
12 #include <media/v4l2-ctrls.h>
13 #include <media/v4l2-device.h>
14 #include <media/v4l2-fwnode.h>
15
16 #define OV2740_LINK_FREQ_360MHZ 360000000ULL
17 #define OV2740_SCLK 72000000LL
18 #define OV2740_MCLK 19200000
19 #define OV2740_DATA_LANES 2
20 #define OV2740_RGB_DEPTH 10
21
22 #define OV2740_REG_CHIP_ID 0x300a
23 #define OV2740_CHIP_ID 0x2740
24
25 #define OV2740_REG_MODE_SELECT 0x0100
26 #define OV2740_MODE_STANDBY 0x00
27 #define OV2740_MODE_STREAMING 0x01
28
29 /* vertical-timings from sensor */
30 #define OV2740_REG_VTS 0x380e
31 #define OV2740_VTS_DEF 0x088a
32 #define OV2740_VTS_MIN 0x0460
33 #define OV2740_VTS_MAX 0x7fff
34
35 /* horizontal-timings from sensor */
36 #define OV2740_REG_HTS 0x380c
37
38 /* Exposure controls from sensor */
39 #define OV2740_REG_EXPOSURE 0x3500
40 #define OV2740_EXPOSURE_MIN 8
41 #define OV2740_EXPOSURE_MAX_MARGIN 8
42 #define OV2740_EXPOSURE_STEP 1
43
44 /* Analog gain controls from sensor */
45 #define OV2740_REG_ANALOG_GAIN 0x3508
46 #define OV2740_ANAL_GAIN_MIN 128
47 #define OV2740_ANAL_GAIN_MAX 1983
48 #define OV2740_ANAL_GAIN_STEP 1
49
50 /* Digital gain controls from sensor */
51 #define OV2740_REG_MWB_R_GAIN 0x500a
52 #define OV2740_REG_MWB_G_GAIN 0x500c
53 #define OV2740_REG_MWB_B_GAIN 0x500e
54 #define OV2740_DGTL_GAIN_MIN 0
55 #define OV2740_DGTL_GAIN_MAX 4095
56 #define OV2740_DGTL_GAIN_STEP 1
57 #define OV2740_DGTL_GAIN_DEFAULT 1024
58
59 /* Test Pattern Control */
60 #define OV2740_REG_TEST_PATTERN 0x5040
61 #define OV2740_TEST_PATTERN_ENABLE BIT(7)
62 #define OV2740_TEST_PATTERN_BAR_SHIFT 2
63
64 /* ISP CTRL00 */
65 #define OV2740_REG_ISP_CTRL00 0x5000
66 /* ISP CTRL01 */
67 #define OV2740_REG_ISP_CTRL01 0x5001
68 /* Customer Addresses: 0x7010 - 0x710F */
69 #define CUSTOMER_USE_OTP_SIZE 0x100
70 /* OTP registers from sensor */
71 #define OV2740_REG_OTP_CUSTOMER 0x7010
72
73 struct nvm_data {
74 char *nvm_buffer;
75 struct nvmem_device *nvmem;
76 struct regmap *regmap;
77 };
78
79 enum {
80 OV2740_LINK_FREQ_360MHZ_INDEX,
81 };
82
83 struct ov2740_reg {
84 u16 address;
85 u8 val;
86 };
87
88 struct ov2740_reg_list {
89 u32 num_of_regs;
90 const struct ov2740_reg *regs;
91 };
92
93 struct ov2740_link_freq_config {
94 const struct ov2740_reg_list reg_list;
95 };
96
97 struct ov2740_mode {
98 /* Frame width in pixels */
99 u32 width;
100
101 /* Frame height in pixels */
102 u32 height;
103
104 /* Horizontal timining size */
105 u32 hts;
106
107 /* Default vertical timining size */
108 u32 vts_def;
109
110 /* Min vertical timining size */
111 u32 vts_min;
112
113 /* Link frequency needed for this resolution */
114 u32 link_freq_index;
115
116 /* Sensor register settings for this resolution */
117 const struct ov2740_reg_list reg_list;
118 };
119
120 static const struct ov2740_reg mipi_data_rate_720mbps[] = {
121 {0x0103, 0x01},
122 {0x0302, 0x4b},
123 {0x030d, 0x4b},
124 {0x030e, 0x02},
125 {0x030a, 0x01},
126 {0x0312, 0x11},
127 };
128
129 static const struct ov2740_reg mode_1932x1092_regs[] = {
130 {0x3000, 0x00},
131 {0x3018, 0x32},
132 {0x3031, 0x0a},
133 {0x3080, 0x08},
134 {0x3083, 0xB4},
135 {0x3103, 0x00},
136 {0x3104, 0x01},
137 {0x3106, 0x01},
138 {0x3500, 0x00},
139 {0x3501, 0x44},
140 {0x3502, 0x40},
141 {0x3503, 0x88},
142 {0x3507, 0x00},
143 {0x3508, 0x00},
144 {0x3509, 0x80},
145 {0x350c, 0x00},
146 {0x350d, 0x80},
147 {0x3510, 0x00},
148 {0x3511, 0x00},
149 {0x3512, 0x20},
150 {0x3632, 0x00},
151 {0x3633, 0x10},
152 {0x3634, 0x10},
153 {0x3635, 0x10},
154 {0x3645, 0x13},
155 {0x3646, 0x81},
156 {0x3636, 0x10},
157 {0x3651, 0x0a},
158 {0x3656, 0x02},
159 {0x3659, 0x04},
160 {0x365a, 0xda},
161 {0x365b, 0xa2},
162 {0x365c, 0x04},
163 {0x365d, 0x1d},
164 {0x365e, 0x1a},
165 {0x3662, 0xd7},
166 {0x3667, 0x78},
167 {0x3669, 0x0a},
168 {0x366a, 0x92},
169 {0x3700, 0x54},
170 {0x3702, 0x10},
171 {0x3706, 0x42},
172 {0x3709, 0x30},
173 {0x370b, 0xc2},
174 {0x3714, 0x63},
175 {0x3715, 0x01},
176 {0x3716, 0x00},
177 {0x371a, 0x3e},
178 {0x3732, 0x0e},
179 {0x3733, 0x10},
180 {0x375f, 0x0e},
181 {0x3768, 0x30},
182 {0x3769, 0x44},
183 {0x376a, 0x22},
184 {0x377b, 0x20},
185 {0x377c, 0x00},
186 {0x377d, 0x0c},
187 {0x3798, 0x00},
188 {0x37a1, 0x55},
189 {0x37a8, 0x6d},
190 {0x37c2, 0x04},
191 {0x37c5, 0x00},
192 {0x37c8, 0x00},
193 {0x3800, 0x00},
194 {0x3801, 0x00},
195 {0x3802, 0x00},
196 {0x3803, 0x00},
197 {0x3804, 0x07},
198 {0x3805, 0x8f},
199 {0x3806, 0x04},
200 {0x3807, 0x47},
201 {0x3808, 0x07},
202 {0x3809, 0x88},
203 {0x380a, 0x04},
204 {0x380b, 0x40},
205 {0x380c, 0x04},
206 {0x380d, 0x38},
207 {0x380e, 0x04},
208 {0x380f, 0x60},
209 {0x3810, 0x00},
210 {0x3811, 0x04},
211 {0x3812, 0x00},
212 {0x3813, 0x04},
213 {0x3814, 0x01},
214 {0x3815, 0x01},
215 {0x3820, 0x80},
216 {0x3821, 0x46},
217 {0x3822, 0x84},
218 {0x3829, 0x00},
219 {0x382a, 0x01},
220 {0x382b, 0x01},
221 {0x3830, 0x04},
222 {0x3836, 0x01},
223 {0x3837, 0x08},
224 {0x3839, 0x01},
225 {0x383a, 0x00},
226 {0x383b, 0x08},
227 {0x383c, 0x00},
228 {0x3f0b, 0x00},
229 {0x4001, 0x20},
230 {0x4009, 0x07},
231 {0x4003, 0x10},
232 {0x4010, 0xe0},
233 {0x4016, 0x00},
234 {0x4017, 0x10},
235 {0x4044, 0x02},
236 {0x4304, 0x08},
237 {0x4307, 0x30},
238 {0x4320, 0x80},
239 {0x4322, 0x00},
240 {0x4323, 0x00},
241 {0x4324, 0x00},
242 {0x4325, 0x00},
243 {0x4326, 0x00},
244 {0x4327, 0x00},
245 {0x4328, 0x00},
246 {0x4329, 0x00},
247 {0x432c, 0x03},
248 {0x432d, 0x81},
249 {0x4501, 0x84},
250 {0x4502, 0x40},
251 {0x4503, 0x18},
252 {0x4504, 0x04},
253 {0x4508, 0x02},
254 {0x4601, 0x10},
255 {0x4800, 0x00},
256 {0x4816, 0x52},
257 {0x4837, 0x16},
258 {0x5000, 0x7f},
259 {0x5001, 0x00},
260 {0x5005, 0x38},
261 {0x501e, 0x0d},
262 {0x5040, 0x00},
263 {0x5901, 0x00},
264 {0x3800, 0x00},
265 {0x3801, 0x00},
266 {0x3802, 0x00},
267 {0x3803, 0x00},
268 {0x3804, 0x07},
269 {0x3805, 0x8f},
270 {0x3806, 0x04},
271 {0x3807, 0x47},
272 {0x3808, 0x07},
273 {0x3809, 0x8c},
274 {0x380a, 0x04},
275 {0x380b, 0x44},
276 {0x3810, 0x00},
277 {0x3811, 0x00},
278 {0x3812, 0x00},
279 {0x3813, 0x01},
280 };
281
282 static const char * const ov2740_test_pattern_menu[] = {
283 "Disabled",
284 "Color Bar",
285 "Top-Bottom Darker Color Bar",
286 "Right-Left Darker Color Bar",
287 "Bottom-Top Darker Color Bar",
288 };
289
290 static const s64 link_freq_menu_items[] = {
291 OV2740_LINK_FREQ_360MHZ,
292 };
293
294 static const struct ov2740_link_freq_config link_freq_configs[] = {
295 [OV2740_LINK_FREQ_360MHZ_INDEX] = {
296 .reg_list = {
297 .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps),
298 .regs = mipi_data_rate_720mbps,
299 }
300 },
301 };
302
303 static const struct ov2740_mode supported_modes[] = {
304 {
305 .width = 1932,
306 .height = 1092,
307 .hts = 1080,
308 .vts_def = OV2740_VTS_DEF,
309 .vts_min = OV2740_VTS_MIN,
310 .reg_list = {
311 .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs),
312 .regs = mode_1932x1092_regs,
313 },
314 .link_freq_index = OV2740_LINK_FREQ_360MHZ_INDEX,
315 },
316 };
317
318 struct ov2740 {
319 struct v4l2_subdev sd;
320 struct media_pad pad;
321 struct v4l2_ctrl_handler ctrl_handler;
322
323 /* V4L2 Controls */
324 struct v4l2_ctrl *link_freq;
325 struct v4l2_ctrl *pixel_rate;
326 struct v4l2_ctrl *vblank;
327 struct v4l2_ctrl *hblank;
328 struct v4l2_ctrl *exposure;
329
330 /* Current mode */
331 const struct ov2740_mode *cur_mode;
332
333 /* To serialize asynchronus callbacks */
334 struct mutex mutex;
335
336 /* Streaming on/off */
337 bool streaming;
338 };
339
to_ov2740(struct v4l2_subdev * subdev)340 static inline struct ov2740 *to_ov2740(struct v4l2_subdev *subdev)
341 {
342 return container_of(subdev, struct ov2740, sd);
343 }
344
to_pixel_rate(u32 f_index)345 static u64 to_pixel_rate(u32 f_index)
346 {
347 u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV2740_DATA_LANES;
348
349 do_div(pixel_rate, OV2740_RGB_DEPTH);
350
351 return pixel_rate;
352 }
353
to_pixels_per_line(u32 hts,u32 f_index)354 static u64 to_pixels_per_line(u32 hts, u32 f_index)
355 {
356 u64 ppl = hts * to_pixel_rate(f_index);
357
358 do_div(ppl, OV2740_SCLK);
359
360 return ppl;
361 }
362
ov2740_read_reg(struct ov2740 * ov2740,u16 reg,u16 len,u32 * val)363 static int ov2740_read_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 *val)
364 {
365 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
366 struct i2c_msg msgs[2];
367 u8 addr_buf[2];
368 u8 data_buf[4] = {0};
369 int ret = 0;
370
371 if (len > sizeof(data_buf))
372 return -EINVAL;
373
374 put_unaligned_be16(reg, addr_buf);
375 msgs[0].addr = client->addr;
376 msgs[0].flags = 0;
377 msgs[0].len = sizeof(addr_buf);
378 msgs[0].buf = addr_buf;
379 msgs[1].addr = client->addr;
380 msgs[1].flags = I2C_M_RD;
381 msgs[1].len = len;
382 msgs[1].buf = &data_buf[sizeof(data_buf) - len];
383
384 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
385 if (ret != ARRAY_SIZE(msgs))
386 return ret < 0 ? ret : -EIO;
387
388 *val = get_unaligned_be32(data_buf);
389
390 return 0;
391 }
392
ov2740_write_reg(struct ov2740 * ov2740,u16 reg,u16 len,u32 val)393 static int ov2740_write_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 val)
394 {
395 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
396 u8 buf[6];
397 int ret = 0;
398
399 if (len > 4)
400 return -EINVAL;
401
402 put_unaligned_be16(reg, buf);
403 put_unaligned_be32(val << 8 * (4 - len), buf + 2);
404
405 ret = i2c_master_send(client, buf, len + 2);
406 if (ret != len + 2)
407 return ret < 0 ? ret : -EIO;
408
409 return 0;
410 }
411
ov2740_write_reg_list(struct ov2740 * ov2740,const struct ov2740_reg_list * r_list)412 static int ov2740_write_reg_list(struct ov2740 *ov2740,
413 const struct ov2740_reg_list *r_list)
414 {
415 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
416 unsigned int i;
417 int ret = 0;
418
419 for (i = 0; i < r_list->num_of_regs; i++) {
420 ret = ov2740_write_reg(ov2740, r_list->regs[i].address, 1,
421 r_list->regs[i].val);
422 if (ret) {
423 dev_err_ratelimited(&client->dev,
424 "write reg 0x%4.4x return err = %d",
425 r_list->regs[i].address, ret);
426 return ret;
427 }
428 }
429
430 return 0;
431 }
432
ov2740_update_digital_gain(struct ov2740 * ov2740,u32 d_gain)433 static int ov2740_update_digital_gain(struct ov2740 *ov2740, u32 d_gain)
434 {
435 int ret = 0;
436
437 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_R_GAIN, 2, d_gain);
438 if (ret)
439 return ret;
440
441 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_G_GAIN, 2, d_gain);
442 if (ret)
443 return ret;
444
445 return ov2740_write_reg(ov2740, OV2740_REG_MWB_B_GAIN, 2, d_gain);
446 }
447
ov2740_test_pattern(struct ov2740 * ov2740,u32 pattern)448 static int ov2740_test_pattern(struct ov2740 *ov2740, u32 pattern)
449 {
450 if (pattern)
451 pattern = (pattern - 1) << OV2740_TEST_PATTERN_BAR_SHIFT |
452 OV2740_TEST_PATTERN_ENABLE;
453
454 return ov2740_write_reg(ov2740, OV2740_REG_TEST_PATTERN, 1, pattern);
455 }
456
ov2740_set_ctrl(struct v4l2_ctrl * ctrl)457 static int ov2740_set_ctrl(struct v4l2_ctrl *ctrl)
458 {
459 struct ov2740 *ov2740 = container_of(ctrl->handler,
460 struct ov2740, ctrl_handler);
461 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
462 s64 exposure_max;
463 int ret = 0;
464
465 /* Propagate change of current control to all related controls */
466 if (ctrl->id == V4L2_CID_VBLANK) {
467 /* Update max exposure while meeting expected vblanking */
468 exposure_max = ov2740->cur_mode->height + ctrl->val -
469 OV2740_EXPOSURE_MAX_MARGIN;
470 __v4l2_ctrl_modify_range(ov2740->exposure,
471 ov2740->exposure->minimum,
472 exposure_max, ov2740->exposure->step,
473 exposure_max);
474 }
475
476 /* V4L2 controls values will be applied only when power is already up */
477 if (!pm_runtime_get_if_in_use(&client->dev))
478 return 0;
479
480 switch (ctrl->id) {
481 case V4L2_CID_ANALOGUE_GAIN:
482 ret = ov2740_write_reg(ov2740, OV2740_REG_ANALOG_GAIN, 2,
483 ctrl->val);
484 break;
485
486 case V4L2_CID_DIGITAL_GAIN:
487 ret = ov2740_update_digital_gain(ov2740, ctrl->val);
488 break;
489
490 case V4L2_CID_EXPOSURE:
491 /* 4 least significant bits of expsoure are fractional part */
492 ret = ov2740_write_reg(ov2740, OV2740_REG_EXPOSURE, 3,
493 ctrl->val << 4);
494 break;
495
496 case V4L2_CID_VBLANK:
497 ret = ov2740_write_reg(ov2740, OV2740_REG_VTS, 2,
498 ov2740->cur_mode->height + ctrl->val);
499 break;
500
501 case V4L2_CID_TEST_PATTERN:
502 ret = ov2740_test_pattern(ov2740, ctrl->val);
503 break;
504
505 default:
506 ret = -EINVAL;
507 break;
508 }
509
510 pm_runtime_put(&client->dev);
511
512 return ret;
513 }
514
515 static const struct v4l2_ctrl_ops ov2740_ctrl_ops = {
516 .s_ctrl = ov2740_set_ctrl,
517 };
518
ov2740_init_controls(struct ov2740 * ov2740)519 static int ov2740_init_controls(struct ov2740 *ov2740)
520 {
521 struct v4l2_ctrl_handler *ctrl_hdlr;
522 const struct ov2740_mode *cur_mode;
523 s64 exposure_max, h_blank, pixel_rate;
524 u32 vblank_min, vblank_max, vblank_default;
525 int size;
526 int ret = 0;
527
528 ctrl_hdlr = &ov2740->ctrl_handler;
529 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
530 if (ret)
531 return ret;
532
533 ctrl_hdlr->lock = &ov2740->mutex;
534 cur_mode = ov2740->cur_mode;
535 size = ARRAY_SIZE(link_freq_menu_items);
536
537 ov2740->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov2740_ctrl_ops,
538 V4L2_CID_LINK_FREQ,
539 size - 1, 0,
540 link_freq_menu_items);
541 if (ov2740->link_freq)
542 ov2740->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
543
544 pixel_rate = to_pixel_rate(OV2740_LINK_FREQ_360MHZ_INDEX);
545 ov2740->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
546 V4L2_CID_PIXEL_RATE, 0,
547 pixel_rate, 1, pixel_rate);
548
549 vblank_min = cur_mode->vts_min - cur_mode->height;
550 vblank_max = OV2740_VTS_MAX - cur_mode->height;
551 vblank_default = cur_mode->vts_def - cur_mode->height;
552 ov2740->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
553 V4L2_CID_VBLANK, vblank_min,
554 vblank_max, 1, vblank_default);
555
556 h_blank = to_pixels_per_line(cur_mode->hts, cur_mode->link_freq_index);
557 h_blank -= cur_mode->width;
558 ov2740->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
559 V4L2_CID_HBLANK, h_blank, h_blank, 1,
560 h_blank);
561 if (ov2740->hblank)
562 ov2740->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
563
564 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
565 OV2740_ANAL_GAIN_MIN, OV2740_ANAL_GAIN_MAX,
566 OV2740_ANAL_GAIN_STEP, OV2740_ANAL_GAIN_MIN);
567 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
568 OV2740_DGTL_GAIN_MIN, OV2740_DGTL_GAIN_MAX,
569 OV2740_DGTL_GAIN_STEP, OV2740_DGTL_GAIN_DEFAULT);
570 exposure_max = cur_mode->vts_def - OV2740_EXPOSURE_MAX_MARGIN;
571 ov2740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
572 V4L2_CID_EXPOSURE,
573 OV2740_EXPOSURE_MIN, exposure_max,
574 OV2740_EXPOSURE_STEP,
575 exposure_max);
576 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov2740_ctrl_ops,
577 V4L2_CID_TEST_PATTERN,
578 ARRAY_SIZE(ov2740_test_pattern_menu) - 1,
579 0, 0, ov2740_test_pattern_menu);
580 if (ctrl_hdlr->error) {
581 v4l2_ctrl_handler_free(ctrl_hdlr);
582 return ctrl_hdlr->error;
583 }
584
585 ov2740->sd.ctrl_handler = ctrl_hdlr;
586
587 return 0;
588 }
589
ov2740_update_pad_format(const struct ov2740_mode * mode,struct v4l2_mbus_framefmt * fmt)590 static void ov2740_update_pad_format(const struct ov2740_mode *mode,
591 struct v4l2_mbus_framefmt *fmt)
592 {
593 fmt->width = mode->width;
594 fmt->height = mode->height;
595 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
596 fmt->field = V4L2_FIELD_NONE;
597 }
598
ov2740_start_streaming(struct ov2740 * ov2740)599 static int ov2740_start_streaming(struct ov2740 *ov2740)
600 {
601 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
602 const struct ov2740_reg_list *reg_list;
603 int link_freq_index;
604 int ret = 0;
605
606 link_freq_index = ov2740->cur_mode->link_freq_index;
607 reg_list = &link_freq_configs[link_freq_index].reg_list;
608 ret = ov2740_write_reg_list(ov2740, reg_list);
609 if (ret) {
610 dev_err(&client->dev, "failed to set plls");
611 return ret;
612 }
613
614 reg_list = &ov2740->cur_mode->reg_list;
615 ret = ov2740_write_reg_list(ov2740, reg_list);
616 if (ret) {
617 dev_err(&client->dev, "failed to set mode");
618 return ret;
619 }
620
621 ret = __v4l2_ctrl_handler_setup(ov2740->sd.ctrl_handler);
622 if (ret)
623 return ret;
624
625 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
626 OV2740_MODE_STREAMING);
627 if (ret)
628 dev_err(&client->dev, "failed to start streaming");
629
630 return ret;
631 }
632
ov2740_stop_streaming(struct ov2740 * ov2740)633 static void ov2740_stop_streaming(struct ov2740 *ov2740)
634 {
635 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
636
637 if (ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
638 OV2740_MODE_STANDBY))
639 dev_err(&client->dev, "failed to stop streaming");
640 }
641
ov2740_set_stream(struct v4l2_subdev * sd,int enable)642 static int ov2740_set_stream(struct v4l2_subdev *sd, int enable)
643 {
644 struct ov2740 *ov2740 = to_ov2740(sd);
645 struct i2c_client *client = v4l2_get_subdevdata(sd);
646 int ret = 0;
647
648 if (ov2740->streaming == enable)
649 return 0;
650
651 mutex_lock(&ov2740->mutex);
652 if (enable) {
653 ret = pm_runtime_get_sync(&client->dev);
654 if (ret < 0) {
655 pm_runtime_put_noidle(&client->dev);
656 mutex_unlock(&ov2740->mutex);
657 return ret;
658 }
659
660 ret = ov2740_start_streaming(ov2740);
661 if (ret) {
662 enable = 0;
663 ov2740_stop_streaming(ov2740);
664 pm_runtime_put(&client->dev);
665 }
666 } else {
667 ov2740_stop_streaming(ov2740);
668 pm_runtime_put(&client->dev);
669 }
670
671 ov2740->streaming = enable;
672 mutex_unlock(&ov2740->mutex);
673
674 return ret;
675 }
676
ov2740_suspend(struct device * dev)677 static int __maybe_unused ov2740_suspend(struct device *dev)
678 {
679 struct i2c_client *client = to_i2c_client(dev);
680 struct v4l2_subdev *sd = i2c_get_clientdata(client);
681 struct ov2740 *ov2740 = to_ov2740(sd);
682
683 mutex_lock(&ov2740->mutex);
684 if (ov2740->streaming)
685 ov2740_stop_streaming(ov2740);
686
687 mutex_unlock(&ov2740->mutex);
688
689 return 0;
690 }
691
ov2740_resume(struct device * dev)692 static int __maybe_unused ov2740_resume(struct device *dev)
693 {
694 struct i2c_client *client = to_i2c_client(dev);
695 struct v4l2_subdev *sd = i2c_get_clientdata(client);
696 struct ov2740 *ov2740 = to_ov2740(sd);
697 int ret = 0;
698
699 mutex_lock(&ov2740->mutex);
700 if (!ov2740->streaming)
701 goto exit;
702
703 ret = ov2740_start_streaming(ov2740);
704 if (ret) {
705 ov2740->streaming = false;
706 ov2740_stop_streaming(ov2740);
707 }
708
709 exit:
710 mutex_unlock(&ov2740->mutex);
711 return ret;
712 }
713
ov2740_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)714 static int ov2740_set_format(struct v4l2_subdev *sd,
715 struct v4l2_subdev_pad_config *cfg,
716 struct v4l2_subdev_format *fmt)
717 {
718 struct ov2740 *ov2740 = to_ov2740(sd);
719 const struct ov2740_mode *mode;
720 s32 vblank_def, h_blank;
721
722 mode = v4l2_find_nearest_size(supported_modes,
723 ARRAY_SIZE(supported_modes), width,
724 height, fmt->format.width,
725 fmt->format.height);
726
727 mutex_lock(&ov2740->mutex);
728 ov2740_update_pad_format(mode, &fmt->format);
729 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
730 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
731 } else {
732 ov2740->cur_mode = mode;
733 __v4l2_ctrl_s_ctrl(ov2740->link_freq, mode->link_freq_index);
734 __v4l2_ctrl_s_ctrl_int64(ov2740->pixel_rate,
735 to_pixel_rate(mode->link_freq_index));
736
737 /* Update limits and set FPS to default */
738 vblank_def = mode->vts_def - mode->height;
739 __v4l2_ctrl_modify_range(ov2740->vblank,
740 mode->vts_min - mode->height,
741 OV2740_VTS_MAX - mode->height, 1,
742 vblank_def);
743 __v4l2_ctrl_s_ctrl(ov2740->vblank, vblank_def);
744 h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) -
745 mode->width;
746 __v4l2_ctrl_modify_range(ov2740->hblank, h_blank, h_blank, 1,
747 h_blank);
748 }
749 mutex_unlock(&ov2740->mutex);
750
751 return 0;
752 }
753
ov2740_get_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)754 static int ov2740_get_format(struct v4l2_subdev *sd,
755 struct v4l2_subdev_pad_config *cfg,
756 struct v4l2_subdev_format *fmt)
757 {
758 struct ov2740 *ov2740 = to_ov2740(sd);
759
760 mutex_lock(&ov2740->mutex);
761 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
762 fmt->format = *v4l2_subdev_get_try_format(&ov2740->sd, cfg,
763 fmt->pad);
764 else
765 ov2740_update_pad_format(ov2740->cur_mode, &fmt->format);
766
767 mutex_unlock(&ov2740->mutex);
768
769 return 0;
770 }
771
ov2740_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)772 static int ov2740_enum_mbus_code(struct v4l2_subdev *sd,
773 struct v4l2_subdev_pad_config *cfg,
774 struct v4l2_subdev_mbus_code_enum *code)
775 {
776 if (code->index > 0)
777 return -EINVAL;
778
779 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
780
781 return 0;
782 }
783
ov2740_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)784 static int ov2740_enum_frame_size(struct v4l2_subdev *sd,
785 struct v4l2_subdev_pad_config *cfg,
786 struct v4l2_subdev_frame_size_enum *fse)
787 {
788 if (fse->index >= ARRAY_SIZE(supported_modes))
789 return -EINVAL;
790
791 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
792 return -EINVAL;
793
794 fse->min_width = supported_modes[fse->index].width;
795 fse->max_width = fse->min_width;
796 fse->min_height = supported_modes[fse->index].height;
797 fse->max_height = fse->min_height;
798
799 return 0;
800 }
801
ov2740_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)802 static int ov2740_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
803 {
804 struct ov2740 *ov2740 = to_ov2740(sd);
805
806 mutex_lock(&ov2740->mutex);
807 ov2740_update_pad_format(&supported_modes[0],
808 v4l2_subdev_get_try_format(sd, fh->pad, 0));
809 mutex_unlock(&ov2740->mutex);
810
811 return 0;
812 }
813
814 static const struct v4l2_subdev_video_ops ov2740_video_ops = {
815 .s_stream = ov2740_set_stream,
816 };
817
818 static const struct v4l2_subdev_pad_ops ov2740_pad_ops = {
819 .set_fmt = ov2740_set_format,
820 .get_fmt = ov2740_get_format,
821 .enum_mbus_code = ov2740_enum_mbus_code,
822 .enum_frame_size = ov2740_enum_frame_size,
823 };
824
825 static const struct v4l2_subdev_ops ov2740_subdev_ops = {
826 .video = &ov2740_video_ops,
827 .pad = &ov2740_pad_ops,
828 };
829
830 static const struct media_entity_operations ov2740_subdev_entity_ops = {
831 .link_validate = v4l2_subdev_link_validate,
832 };
833
834 static const struct v4l2_subdev_internal_ops ov2740_internal_ops = {
835 .open = ov2740_open,
836 };
837
ov2740_identify_module(struct ov2740 * ov2740)838 static int ov2740_identify_module(struct ov2740 *ov2740)
839 {
840 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
841 int ret;
842 u32 val;
843
844 ret = ov2740_read_reg(ov2740, OV2740_REG_CHIP_ID, 3, &val);
845 if (ret)
846 return ret;
847
848 if (val != OV2740_CHIP_ID) {
849 dev_err(&client->dev, "chip id mismatch: %x!=%x",
850 OV2740_CHIP_ID, val);
851 return -ENXIO;
852 }
853
854 return 0;
855 }
856
ov2740_check_hwcfg(struct device * dev)857 static int ov2740_check_hwcfg(struct device *dev)
858 {
859 struct fwnode_handle *ep;
860 struct fwnode_handle *fwnode = dev_fwnode(dev);
861 struct v4l2_fwnode_endpoint bus_cfg = {
862 .bus_type = V4L2_MBUS_CSI2_DPHY
863 };
864 u32 mclk;
865 int ret;
866 unsigned int i, j;
867
868 if (!fwnode)
869 return -ENXIO;
870
871 ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk);
872 if (ret)
873 return ret;
874
875 if (mclk != OV2740_MCLK) {
876 dev_err(dev, "external clock %d is not supported", mclk);
877 return -EINVAL;
878 }
879
880 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
881 if (!ep)
882 return -ENXIO;
883
884 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
885 fwnode_handle_put(ep);
886 if (ret)
887 return ret;
888
889 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV2740_DATA_LANES) {
890 dev_err(dev, "number of CSI2 data lanes %d is not supported",
891 bus_cfg.bus.mipi_csi2.num_data_lanes);
892 ret = -EINVAL;
893 goto check_hwcfg_error;
894 }
895
896 if (!bus_cfg.nr_of_link_frequencies) {
897 dev_err(dev, "no link frequencies defined");
898 ret = -EINVAL;
899 goto check_hwcfg_error;
900 }
901
902 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
903 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
904 if (link_freq_menu_items[i] ==
905 bus_cfg.link_frequencies[j])
906 break;
907 }
908
909 if (j == bus_cfg.nr_of_link_frequencies) {
910 dev_err(dev, "no link frequency %lld supported",
911 link_freq_menu_items[i]);
912 ret = -EINVAL;
913 goto check_hwcfg_error;
914 }
915 }
916
917 check_hwcfg_error:
918 v4l2_fwnode_endpoint_free(&bus_cfg);
919
920 return ret;
921 }
922
ov2740_remove(struct i2c_client * client)923 static int ov2740_remove(struct i2c_client *client)
924 {
925 struct v4l2_subdev *sd = i2c_get_clientdata(client);
926 struct ov2740 *ov2740 = to_ov2740(sd);
927
928 v4l2_async_unregister_subdev(sd);
929 media_entity_cleanup(&sd->entity);
930 v4l2_ctrl_handler_free(sd->ctrl_handler);
931 pm_runtime_disable(&client->dev);
932 mutex_destroy(&ov2740->mutex);
933
934 return 0;
935 }
936
ov2740_load_otp_data(struct i2c_client * client,struct nvm_data * nvm)937 static int ov2740_load_otp_data(struct i2c_client *client, struct nvm_data *nvm)
938 {
939 struct ov2740 *ov2740 = to_ov2740(i2c_get_clientdata(client));
940 u32 isp_ctrl00 = 0;
941 u32 isp_ctrl01 = 0;
942 int ret;
943
944 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, &isp_ctrl00);
945 if (ret) {
946 dev_err(&client->dev, "failed to read ISP CTRL00\n");
947 goto exit;
948 }
949 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, &isp_ctrl01);
950 if (ret) {
951 dev_err(&client->dev, "failed to read ISP CTRL01\n");
952 goto exit;
953 }
954
955 /* Clear bit 5 of ISP CTRL00 */
956 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1,
957 isp_ctrl00 & ~BIT(5));
958 if (ret) {
959 dev_err(&client->dev, "failed to write ISP CTRL00\n");
960 goto exit;
961 }
962
963 /* Clear bit 7 of ISP CTRL01 */
964 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1,
965 isp_ctrl01 & ~BIT(7));
966 if (ret) {
967 dev_err(&client->dev, "failed to write ISP CTRL01\n");
968 goto exit;
969 }
970
971 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
972 OV2740_MODE_STREAMING);
973 if (ret) {
974 dev_err(&client->dev, "failed to start streaming\n");
975 goto exit;
976 }
977
978 /*
979 * Users are not allowed to access OTP-related registers and memory
980 * during the 20 ms period after streaming starts (0x100 = 0x01).
981 */
982 msleep(20);
983
984 ret = regmap_bulk_read(nvm->regmap, OV2740_REG_OTP_CUSTOMER,
985 nvm->nvm_buffer, CUSTOMER_USE_OTP_SIZE);
986 if (ret) {
987 dev_err(&client->dev, "failed to read OTP data, ret %d\n", ret);
988 goto exit;
989 }
990
991 ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
992 OV2740_MODE_STANDBY);
993 ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01);
994 ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00);
995
996 exit:
997 return ret;
998 }
999
ov2740_nvmem_read(void * priv,unsigned int off,void * val,size_t count)1000 static int ov2740_nvmem_read(void *priv, unsigned int off, void *val,
1001 size_t count)
1002 {
1003 struct nvm_data *nvm = priv;
1004
1005 memcpy(val, nvm->nvm_buffer + off, count);
1006
1007 return 0;
1008 }
1009
ov2740_register_nvmem(struct i2c_client * client)1010 static int ov2740_register_nvmem(struct i2c_client *client)
1011 {
1012 struct nvm_data *nvm;
1013 struct regmap_config regmap_config = { };
1014 struct nvmem_config nvmem_config = { };
1015 struct regmap *regmap;
1016 struct device *dev = &client->dev;
1017 int ret = 0;
1018
1019 nvm = devm_kzalloc(dev, sizeof(*nvm), GFP_KERNEL);
1020 if (!nvm)
1021 return -ENOMEM;
1022
1023 nvm->nvm_buffer = devm_kzalloc(dev, CUSTOMER_USE_OTP_SIZE, GFP_KERNEL);
1024 if (!nvm->nvm_buffer)
1025 return -ENOMEM;
1026
1027 regmap_config.val_bits = 8;
1028 regmap_config.reg_bits = 16;
1029 regmap_config.disable_locking = true;
1030 regmap = devm_regmap_init_i2c(client, ®map_config);
1031 if (IS_ERR(regmap))
1032 return PTR_ERR(regmap);
1033
1034 nvm->regmap = regmap;
1035
1036 ret = ov2740_load_otp_data(client, nvm);
1037 if (ret) {
1038 dev_err(dev, "failed to load OTP data, ret %d\n", ret);
1039 return ret;
1040 }
1041
1042 nvmem_config.name = dev_name(dev);
1043 nvmem_config.dev = dev;
1044 nvmem_config.read_only = true;
1045 nvmem_config.root_only = true;
1046 nvmem_config.owner = THIS_MODULE;
1047 nvmem_config.compat = true;
1048 nvmem_config.base_dev = dev;
1049 nvmem_config.reg_read = ov2740_nvmem_read;
1050 nvmem_config.reg_write = NULL;
1051 nvmem_config.priv = nvm;
1052 nvmem_config.stride = 1;
1053 nvmem_config.word_size = 1;
1054 nvmem_config.size = CUSTOMER_USE_OTP_SIZE;
1055
1056 nvm->nvmem = devm_nvmem_register(dev, &nvmem_config);
1057
1058 return PTR_ERR_OR_ZERO(nvm->nvmem);
1059 }
1060
ov2740_probe(struct i2c_client * client)1061 static int ov2740_probe(struct i2c_client *client)
1062 {
1063 struct ov2740 *ov2740;
1064 int ret = 0;
1065
1066 ret = ov2740_check_hwcfg(&client->dev);
1067 if (ret) {
1068 dev_err(&client->dev, "failed to check HW configuration: %d",
1069 ret);
1070 return ret;
1071 }
1072
1073 ov2740 = devm_kzalloc(&client->dev, sizeof(*ov2740), GFP_KERNEL);
1074 if (!ov2740)
1075 return -ENOMEM;
1076
1077 v4l2_i2c_subdev_init(&ov2740->sd, client, &ov2740_subdev_ops);
1078 ret = ov2740_identify_module(ov2740);
1079 if (ret) {
1080 dev_err(&client->dev, "failed to find sensor: %d", ret);
1081 return ret;
1082 }
1083
1084 mutex_init(&ov2740->mutex);
1085 ov2740->cur_mode = &supported_modes[0];
1086 ret = ov2740_init_controls(ov2740);
1087 if (ret) {
1088 dev_err(&client->dev, "failed to init controls: %d", ret);
1089 goto probe_error_v4l2_ctrl_handler_free;
1090 }
1091
1092 ov2740->sd.internal_ops = &ov2740_internal_ops;
1093 ov2740->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1094 ov2740->sd.entity.ops = &ov2740_subdev_entity_ops;
1095 ov2740->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1096 ov2740->pad.flags = MEDIA_PAD_FL_SOURCE;
1097 ret = media_entity_pads_init(&ov2740->sd.entity, 1, &ov2740->pad);
1098 if (ret) {
1099 dev_err(&client->dev, "failed to init entity pads: %d", ret);
1100 goto probe_error_v4l2_ctrl_handler_free;
1101 }
1102
1103 ret = v4l2_async_register_subdev_sensor_common(&ov2740->sd);
1104 if (ret < 0) {
1105 dev_err(&client->dev, "failed to register V4L2 subdev: %d",
1106 ret);
1107 goto probe_error_media_entity_cleanup;
1108 }
1109
1110 ret = ov2740_register_nvmem(client);
1111 if (ret)
1112 dev_warn(&client->dev, "register nvmem failed, ret %d\n", ret);
1113
1114 /*
1115 * Device is already turned on by i2c-core with ACPI domain PM.
1116 * Enable runtime PM and turn off the device.
1117 */
1118 pm_runtime_set_active(&client->dev);
1119 pm_runtime_enable(&client->dev);
1120 pm_runtime_idle(&client->dev);
1121
1122 return 0;
1123
1124 probe_error_media_entity_cleanup:
1125 media_entity_cleanup(&ov2740->sd.entity);
1126
1127 probe_error_v4l2_ctrl_handler_free:
1128 v4l2_ctrl_handler_free(ov2740->sd.ctrl_handler);
1129 mutex_destroy(&ov2740->mutex);
1130
1131 return ret;
1132 }
1133
1134 static const struct dev_pm_ops ov2740_pm_ops = {
1135 SET_SYSTEM_SLEEP_PM_OPS(ov2740_suspend, ov2740_resume)
1136 };
1137
1138 static const struct acpi_device_id ov2740_acpi_ids[] = {
1139 {"INT3474"},
1140 {}
1141 };
1142
1143 MODULE_DEVICE_TABLE(acpi, ov2740_acpi_ids);
1144
1145 static struct i2c_driver ov2740_i2c_driver = {
1146 .driver = {
1147 .name = "ov2740",
1148 .pm = &ov2740_pm_ops,
1149 .acpi_match_table = ov2740_acpi_ids,
1150 },
1151 .probe_new = ov2740_probe,
1152 .remove = ov2740_remove,
1153 };
1154
1155 module_i2c_driver(ov2740_i2c_driver);
1156
1157 MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>");
1158 MODULE_AUTHOR("Shawn Tu <shawnx.tu@intel.com>");
1159 MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>");
1160 MODULE_DESCRIPTION("OmniVision OV2740 sensor driver");
1161 MODULE_LICENSE("GPL v2");
1162