1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Access SD/MMC cards through SPI master controllers
4 *
5 * (C) Copyright 2005, Intec Automation,
6 * Mike Lavender (mike@steroidmicros)
7 * (C) Copyright 2006-2007, David Brownell
8 * (C) Copyright 2007, Axis Communications,
9 * Hans-Peter Nilsson (hp@axis.com)
10 * (C) Copyright 2007, ATRON electronic GmbH,
11 * Jan Nikitenko <jan.nikitenko@gmail.com>
12 */
13 #include <linux/sched.h>
14 #include <linux/delay.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/bio.h>
18 #include <linux/dma-direction.h>
19 #include <linux/crc7.h>
20 #include <linux/crc-itu-t.h>
21 #include <linux/scatterlist.h>
22
23 #include <linux/mmc/host.h>
24 #include <linux/mmc/mmc.h> /* for R1_SPI_* bit values */
25 #include <linux/mmc/slot-gpio.h>
26
27 #include <linux/spi/spi.h>
28 #include <linux/spi/mmc_spi.h>
29
30 #include <asm/unaligned.h>
31
32
33 /* NOTES:
34 *
35 * - For now, we won't try to interoperate with a real mmc/sd/sdio
36 * controller, although some of them do have hardware support for
37 * SPI protocol. The main reason for such configs would be mmc-ish
38 * cards like DataFlash, which don't support that "native" protocol.
39 *
40 * We don't have a "DataFlash/MMC/SD/SDIO card slot" abstraction to
41 * switch between driver stacks, and in any case if "native" mode
42 * is available, it will be faster and hence preferable.
43 *
44 * - MMC depends on a different chipselect management policy than the
45 * SPI interface currently supports for shared bus segments: it needs
46 * to issue multiple spi_message requests with the chipselect active,
47 * using the results of one message to decide the next one to issue.
48 *
49 * Pending updates to the programming interface, this driver expects
50 * that it not share the bus with other drivers (precluding conflicts).
51 *
52 * - We tell the controller to keep the chipselect active from the
53 * beginning of an mmc_host_ops.request until the end. So beware
54 * of SPI controller drivers that mis-handle the cs_change flag!
55 *
56 * However, many cards seem OK with chipselect flapping up/down
57 * during that time ... at least on unshared bus segments.
58 */
59
60
61 /*
62 * Local protocol constants, internal to data block protocols.
63 */
64
65 /* Response tokens used to ack each block written: */
66 #define SPI_MMC_RESPONSE_CODE(x) ((x) & 0x1f)
67 #define SPI_RESPONSE_ACCEPTED ((2 << 1)|1)
68 #define SPI_RESPONSE_CRC_ERR ((5 << 1)|1)
69 #define SPI_RESPONSE_WRITE_ERR ((6 << 1)|1)
70
71 /* Read and write blocks start with these tokens and end with crc;
72 * on error, read tokens act like a subset of R2_SPI_* values.
73 */
74 #define SPI_TOKEN_SINGLE 0xfe /* single block r/w, multiblock read */
75 #define SPI_TOKEN_MULTI_WRITE 0xfc /* multiblock write */
76 #define SPI_TOKEN_STOP_TRAN 0xfd /* terminate multiblock write */
77
78 #define MMC_SPI_BLOCKSIZE 512
79
80 #define MMC_SPI_R1B_TIMEOUT_MS 3000
81 #define MMC_SPI_INIT_TIMEOUT_MS 3000
82
83 /* One of the critical speed parameters is the amount of data which may
84 * be transferred in one command. If this value is too low, the SD card
85 * controller has to do multiple partial block writes (argggh!). With
86 * today (2008) SD cards there is little speed gain if we transfer more
87 * than 64 KBytes at a time. So use this value until there is any indication
88 * that we should do more here.
89 */
90 #define MMC_SPI_BLOCKSATONCE 128
91
92 /****************************************************************************/
93
94 /*
95 * Local Data Structures
96 */
97
98 /* "scratch" is per-{command,block} data exchanged with the card */
99 struct scratch {
100 u8 status[29];
101 u8 data_token;
102 __be16 crc_val;
103 };
104
105 struct mmc_spi_host {
106 struct mmc_host *mmc;
107 struct spi_device *spi;
108
109 unsigned char power_mode;
110 u16 powerup_msecs;
111
112 struct mmc_spi_platform_data *pdata;
113
114 /* for bulk data transfers */
115 struct spi_transfer token, t, crc, early_status;
116 struct spi_message m;
117
118 /* for status readback */
119 struct spi_transfer status;
120 struct spi_message readback;
121
122 /* buffer used for commands and for message "overhead" */
123 struct scratch *data;
124
125 /* Specs say to write ones most of the time, even when the card
126 * has no need to read its input data; and many cards won't care.
127 * This is our source of those ones.
128 */
129 void *ones;
130 };
131
132
133 /****************************************************************************/
134
135 /*
136 * MMC-over-SPI protocol glue, used by the MMC stack interface
137 */
138
mmc_cs_off(struct mmc_spi_host * host)139 static inline int mmc_cs_off(struct mmc_spi_host *host)
140 {
141 /* chipselect will always be inactive after setup() */
142 return spi_setup(host->spi);
143 }
144
mmc_spi_readbytes(struct mmc_spi_host * host,unsigned int len)145 static int mmc_spi_readbytes(struct mmc_spi_host *host, unsigned int len)
146 {
147 if (len > sizeof(*host->data)) {
148 WARN_ON(1);
149 return -EIO;
150 }
151
152 host->status.len = len;
153
154 return spi_sync_locked(host->spi, &host->readback);
155 }
156
mmc_spi_skip(struct mmc_spi_host * host,unsigned long timeout,unsigned n,u8 byte)157 static int mmc_spi_skip(struct mmc_spi_host *host, unsigned long timeout,
158 unsigned n, u8 byte)
159 {
160 u8 *cp = host->data->status;
161 unsigned long start = jiffies;
162
163 while (1) {
164 int status;
165 unsigned i;
166
167 status = mmc_spi_readbytes(host, n);
168 if (status < 0)
169 return status;
170
171 for (i = 0; i < n; i++) {
172 if (cp[i] != byte)
173 return cp[i];
174 }
175
176 if (time_is_before_jiffies(start + timeout))
177 break;
178
179 /* If we need long timeouts, we may release the CPU.
180 * We use jiffies here because we want to have a relation
181 * between elapsed time and the blocking of the scheduler.
182 */
183 if (time_is_before_jiffies(start + 1))
184 schedule();
185 }
186 return -ETIMEDOUT;
187 }
188
189 static inline int
mmc_spi_wait_unbusy(struct mmc_spi_host * host,unsigned long timeout)190 mmc_spi_wait_unbusy(struct mmc_spi_host *host, unsigned long timeout)
191 {
192 return mmc_spi_skip(host, timeout, sizeof(host->data->status), 0);
193 }
194
mmc_spi_readtoken(struct mmc_spi_host * host,unsigned long timeout)195 static int mmc_spi_readtoken(struct mmc_spi_host *host, unsigned long timeout)
196 {
197 return mmc_spi_skip(host, timeout, 1, 0xff);
198 }
199
200
201 /*
202 * Note that for SPI, cmd->resp[0] is not the same data as "native" protocol
203 * hosts return! The low byte holds R1_SPI bits. The next byte may hold
204 * R2_SPI bits ... for SEND_STATUS, or after data read errors.
205 *
206 * cmd->resp[1] holds any four-byte response, for R3 (READ_OCR) and on
207 * newer cards R7 (IF_COND).
208 */
209
maptype(struct mmc_command * cmd)210 static char *maptype(struct mmc_command *cmd)
211 {
212 switch (mmc_spi_resp_type(cmd)) {
213 case MMC_RSP_SPI_R1: return "R1";
214 case MMC_RSP_SPI_R1B: return "R1B";
215 case MMC_RSP_SPI_R2: return "R2/R5";
216 case MMC_RSP_SPI_R3: return "R3/R4/R7";
217 default: return "?";
218 }
219 }
220
221 /* return zero, else negative errno after setting cmd->error */
mmc_spi_response_get(struct mmc_spi_host * host,struct mmc_command * cmd,int cs_on)222 static int mmc_spi_response_get(struct mmc_spi_host *host,
223 struct mmc_command *cmd, int cs_on)
224 {
225 unsigned long timeout_ms;
226 u8 *cp = host->data->status;
227 u8 *end = cp + host->t.len;
228 int value = 0;
229 int bitshift;
230 u8 leftover = 0;
231 unsigned short rotator;
232 int i;
233 char tag[32];
234
235 snprintf(tag, sizeof(tag), " ... CMD%d response SPI_%s",
236 cmd->opcode, maptype(cmd));
237
238 /* Except for data block reads, the whole response will already
239 * be stored in the scratch buffer. It's somewhere after the
240 * command and the first byte we read after it. We ignore that
241 * first byte. After STOP_TRANSMISSION command it may include
242 * two data bits, but otherwise it's all ones.
243 */
244 cp += 8;
245 while (cp < end && *cp == 0xff)
246 cp++;
247
248 /* Data block reads (R1 response types) may need more data... */
249 if (cp == end) {
250 cp = host->data->status;
251 end = cp+1;
252
253 /* Card sends N(CR) (== 1..8) bytes of all-ones then one
254 * status byte ... and we already scanned 2 bytes.
255 *
256 * REVISIT block read paths use nasty byte-at-a-time I/O
257 * so it can always DMA directly into the target buffer.
258 * It'd probably be better to memcpy() the first chunk and
259 * avoid extra i/o calls...
260 *
261 * Note we check for more than 8 bytes, because in practice,
262 * some SD cards are slow...
263 */
264 for (i = 2; i < 16; i++) {
265 value = mmc_spi_readbytes(host, 1);
266 if (value < 0)
267 goto done;
268 if (*cp != 0xff)
269 goto checkstatus;
270 }
271 value = -ETIMEDOUT;
272 goto done;
273 }
274
275 checkstatus:
276 bitshift = 0;
277 if (*cp & 0x80) {
278 /* Houston, we have an ugly card with a bit-shifted response */
279 rotator = *cp++ << 8;
280 /* read the next byte */
281 if (cp == end) {
282 value = mmc_spi_readbytes(host, 1);
283 if (value < 0)
284 goto done;
285 cp = host->data->status;
286 end = cp+1;
287 }
288 rotator |= *cp++;
289 while (rotator & 0x8000) {
290 bitshift++;
291 rotator <<= 1;
292 }
293 cmd->resp[0] = rotator >> 8;
294 leftover = rotator;
295 } else {
296 cmd->resp[0] = *cp++;
297 }
298 cmd->error = 0;
299
300 /* Status byte: the entire seven-bit R1 response. */
301 if (cmd->resp[0] != 0) {
302 if ((R1_SPI_PARAMETER | R1_SPI_ADDRESS)
303 & cmd->resp[0])
304 value = -EFAULT; /* Bad address */
305 else if (R1_SPI_ILLEGAL_COMMAND & cmd->resp[0])
306 value = -ENOSYS; /* Function not implemented */
307 else if (R1_SPI_COM_CRC & cmd->resp[0])
308 value = -EILSEQ; /* Illegal byte sequence */
309 else if ((R1_SPI_ERASE_SEQ | R1_SPI_ERASE_RESET)
310 & cmd->resp[0])
311 value = -EIO; /* I/O error */
312 /* else R1_SPI_IDLE, "it's resetting" */
313 }
314
315 switch (mmc_spi_resp_type(cmd)) {
316
317 /* SPI R1B == R1 + busy; STOP_TRANSMISSION (for multiblock reads)
318 * and less-common stuff like various erase operations.
319 */
320 case MMC_RSP_SPI_R1B:
321 /* maybe we read all the busy tokens already */
322 while (cp < end && *cp == 0)
323 cp++;
324 if (cp == end) {
325 timeout_ms = cmd->busy_timeout ? cmd->busy_timeout :
326 MMC_SPI_R1B_TIMEOUT_MS;
327 mmc_spi_wait_unbusy(host, msecs_to_jiffies(timeout_ms));
328 }
329 break;
330
331 /* SPI R2 == R1 + second status byte; SEND_STATUS
332 * SPI R5 == R1 + data byte; IO_RW_DIRECT
333 */
334 case MMC_RSP_SPI_R2:
335 /* read the next byte */
336 if (cp == end) {
337 value = mmc_spi_readbytes(host, 1);
338 if (value < 0)
339 goto done;
340 cp = host->data->status;
341 end = cp+1;
342 }
343 if (bitshift) {
344 rotator = leftover << 8;
345 rotator |= *cp << bitshift;
346 cmd->resp[0] |= (rotator & 0xFF00);
347 } else {
348 cmd->resp[0] |= *cp << 8;
349 }
350 break;
351
352 /* SPI R3, R4, or R7 == R1 + 4 bytes */
353 case MMC_RSP_SPI_R3:
354 rotator = leftover << 8;
355 cmd->resp[1] = 0;
356 for (i = 0; i < 4; i++) {
357 cmd->resp[1] <<= 8;
358 /* read the next byte */
359 if (cp == end) {
360 value = mmc_spi_readbytes(host, 1);
361 if (value < 0)
362 goto done;
363 cp = host->data->status;
364 end = cp+1;
365 }
366 if (bitshift) {
367 rotator |= *cp++ << bitshift;
368 cmd->resp[1] |= (rotator >> 8);
369 rotator <<= 8;
370 } else {
371 cmd->resp[1] |= *cp++;
372 }
373 }
374 break;
375
376 /* SPI R1 == just one status byte */
377 case MMC_RSP_SPI_R1:
378 break;
379
380 default:
381 dev_dbg(&host->spi->dev, "bad response type %04x\n",
382 mmc_spi_resp_type(cmd));
383 if (value >= 0)
384 value = -EINVAL;
385 goto done;
386 }
387
388 if (value < 0)
389 dev_dbg(&host->spi->dev, "%s: resp %04x %08x\n",
390 tag, cmd->resp[0], cmd->resp[1]);
391
392 /* disable chipselect on errors and some success cases */
393 if (value >= 0 && cs_on)
394 return value;
395 done:
396 if (value < 0)
397 cmd->error = value;
398 mmc_cs_off(host);
399 return value;
400 }
401
402 /* Issue command and read its response.
403 * Returns zero on success, negative for error.
404 *
405 * On error, caller must cope with mmc core retry mechanism. That
406 * means immediate low-level resubmit, which affects the bus lock...
407 */
408 static int
mmc_spi_command_send(struct mmc_spi_host * host,struct mmc_request * mrq,struct mmc_command * cmd,int cs_on)409 mmc_spi_command_send(struct mmc_spi_host *host,
410 struct mmc_request *mrq,
411 struct mmc_command *cmd, int cs_on)
412 {
413 struct scratch *data = host->data;
414 u8 *cp = data->status;
415 int status;
416 struct spi_transfer *t;
417
418 /* We can handle most commands (except block reads) in one full
419 * duplex I/O operation before either starting the next transfer
420 * (data block or command) or else deselecting the card.
421 *
422 * First, write 7 bytes:
423 * - an all-ones byte to ensure the card is ready
424 * - opcode byte (plus start and transmission bits)
425 * - four bytes of big-endian argument
426 * - crc7 (plus end bit) ... always computed, it's cheap
427 *
428 * We init the whole buffer to all-ones, which is what we need
429 * to write while we're reading (later) response data.
430 */
431 memset(cp, 0xff, sizeof(data->status));
432
433 cp[1] = 0x40 | cmd->opcode;
434 put_unaligned_be32(cmd->arg, cp + 2);
435 cp[6] = crc7_be(0, cp + 1, 5) | 0x01;
436 cp += 7;
437
438 /* Then, read up to 13 bytes (while writing all-ones):
439 * - N(CR) (== 1..8) bytes of all-ones
440 * - status byte (for all response types)
441 * - the rest of the response, either:
442 * + nothing, for R1 or R1B responses
443 * + second status byte, for R2 responses
444 * + four data bytes, for R3 and R7 responses
445 *
446 * Finally, read some more bytes ... in the nice cases we know in
447 * advance how many, and reading 1 more is always OK:
448 * - N(EC) (== 0..N) bytes of all-ones, before deselect/finish
449 * - N(RC) (== 1..N) bytes of all-ones, before next command
450 * - N(WR) (== 1..N) bytes of all-ones, before data write
451 *
452 * So in those cases one full duplex I/O of at most 21 bytes will
453 * handle the whole command, leaving the card ready to receive a
454 * data block or new command. We do that whenever we can, shaving
455 * CPU and IRQ costs (especially when using DMA or FIFOs).
456 *
457 * There are two other cases, where it's not generally practical
458 * to rely on a single I/O:
459 *
460 * - R1B responses need at least N(EC) bytes of all-zeroes.
461 *
462 * In this case we can *try* to fit it into one I/O, then
463 * maybe read more data later.
464 *
465 * - Data block reads are more troublesome, since a variable
466 * number of padding bytes precede the token and data.
467 * + N(CX) (== 0..8) bytes of all-ones, before CSD or CID
468 * + N(AC) (== 1..many) bytes of all-ones
469 *
470 * In this case we currently only have minimal speedups here:
471 * when N(CR) == 1 we can avoid I/O in response_get().
472 */
473 if (cs_on && (mrq->data->flags & MMC_DATA_READ)) {
474 cp += 2; /* min(N(CR)) + status */
475 /* R1 */
476 } else {
477 cp += 10; /* max(N(CR)) + status + min(N(RC),N(WR)) */
478 if (cmd->flags & MMC_RSP_SPI_S2) /* R2/R5 */
479 cp++;
480 else if (cmd->flags & MMC_RSP_SPI_B4) /* R3/R4/R7 */
481 cp += 4;
482 else if (cmd->flags & MMC_RSP_BUSY) /* R1B */
483 cp = data->status + sizeof(data->status);
484 /* else: R1 (most commands) */
485 }
486
487 dev_dbg(&host->spi->dev, " mmc_spi: CMD%d, resp %s\n",
488 cmd->opcode, maptype(cmd));
489
490 /* send command, leaving chipselect active */
491 spi_message_init(&host->m);
492
493 t = &host->t;
494 memset(t, 0, sizeof(*t));
495 t->tx_buf = t->rx_buf = data->status;
496 t->len = cp - data->status;
497 t->cs_change = 1;
498 spi_message_add_tail(t, &host->m);
499
500 status = spi_sync_locked(host->spi, &host->m);
501 if (status < 0) {
502 dev_dbg(&host->spi->dev, " ... write returned %d\n", status);
503 cmd->error = status;
504 return status;
505 }
506
507 /* after no-data commands and STOP_TRANSMISSION, chipselect off */
508 return mmc_spi_response_get(host, cmd, cs_on);
509 }
510
511 /* Build data message with up to four separate transfers. For TX, we
512 * start by writing the data token. And in most cases, we finish with
513 * a status transfer.
514 *
515 * We always provide TX data for data and CRC. The MMC/SD protocol
516 * requires us to write ones; but Linux defaults to writing zeroes;
517 * so we explicitly initialize it to all ones on RX paths.
518 */
519 static void
mmc_spi_setup_data_message(struct mmc_spi_host * host,int multiple,enum dma_data_direction direction)520 mmc_spi_setup_data_message(
521 struct mmc_spi_host *host,
522 int multiple,
523 enum dma_data_direction direction)
524 {
525 struct spi_transfer *t;
526 struct scratch *scratch = host->data;
527
528 spi_message_init(&host->m);
529
530 /* for reads, readblock() skips 0xff bytes before finding
531 * the token; for writes, this transfer issues that token.
532 */
533 if (direction == DMA_TO_DEVICE) {
534 t = &host->token;
535 memset(t, 0, sizeof(*t));
536 t->len = 1;
537 if (multiple)
538 scratch->data_token = SPI_TOKEN_MULTI_WRITE;
539 else
540 scratch->data_token = SPI_TOKEN_SINGLE;
541 t->tx_buf = &scratch->data_token;
542 spi_message_add_tail(t, &host->m);
543 }
544
545 /* Body of transfer is buffer, then CRC ...
546 * either TX-only, or RX with TX-ones.
547 */
548 t = &host->t;
549 memset(t, 0, sizeof(*t));
550 t->tx_buf = host->ones;
551 /* length and actual buffer info are written later */
552 spi_message_add_tail(t, &host->m);
553
554 t = &host->crc;
555 memset(t, 0, sizeof(*t));
556 t->len = 2;
557 if (direction == DMA_TO_DEVICE) {
558 /* the actual CRC may get written later */
559 t->tx_buf = &scratch->crc_val;
560 } else {
561 t->tx_buf = host->ones;
562 t->rx_buf = &scratch->crc_val;
563 }
564 spi_message_add_tail(t, &host->m);
565
566 /*
567 * A single block read is followed by N(EC) [0+] all-ones bytes
568 * before deselect ... don't bother.
569 *
570 * Multiblock reads are followed by N(AC) [1+] all-ones bytes before
571 * the next block is read, or a STOP_TRANSMISSION is issued. We'll
572 * collect that single byte, so readblock() doesn't need to.
573 *
574 * For a write, the one-byte data response follows immediately, then
575 * come zero or more busy bytes, then N(WR) [1+] all-ones bytes.
576 * Then single block reads may deselect, and multiblock ones issue
577 * the next token (next data block, or STOP_TRAN). We can try to
578 * minimize I/O ops by using a single read to collect end-of-busy.
579 */
580 if (multiple || direction == DMA_TO_DEVICE) {
581 t = &host->early_status;
582 memset(t, 0, sizeof(*t));
583 t->len = (direction == DMA_TO_DEVICE) ? sizeof(scratch->status) : 1;
584 t->tx_buf = host->ones;
585 t->rx_buf = scratch->status;
586 t->cs_change = 1;
587 spi_message_add_tail(t, &host->m);
588 }
589 }
590
591 /*
592 * Write one block:
593 * - caller handled preceding N(WR) [1+] all-ones bytes
594 * - data block
595 * + token
596 * + data bytes
597 * + crc16
598 * - an all-ones byte ... card writes a data-response byte
599 * - followed by N(EC) [0+] all-ones bytes, card writes zero/'busy'
600 *
601 * Return negative errno, else success.
602 */
603 static int
mmc_spi_writeblock(struct mmc_spi_host * host,struct spi_transfer * t,unsigned long timeout)604 mmc_spi_writeblock(struct mmc_spi_host *host, struct spi_transfer *t,
605 unsigned long timeout)
606 {
607 struct spi_device *spi = host->spi;
608 int status, i;
609 struct scratch *scratch = host->data;
610 u32 pattern;
611
612 if (host->mmc->use_spi_crc)
613 scratch->crc_val = cpu_to_be16(crc_itu_t(0, t->tx_buf, t->len));
614
615 status = spi_sync_locked(spi, &host->m);
616 if (status != 0) {
617 dev_dbg(&spi->dev, "write error (%d)\n", status);
618 return status;
619 }
620
621 /*
622 * Get the transmission data-response reply. It must follow
623 * immediately after the data block we transferred. This reply
624 * doesn't necessarily tell whether the write operation succeeded;
625 * it just says if the transmission was ok and whether *earlier*
626 * writes succeeded; see the standard.
627 *
628 * In practice, there are (even modern SDHC-)cards which are late
629 * in sending the response, and miss the time frame by a few bits,
630 * so we have to cope with this situation and check the response
631 * bit-by-bit. Arggh!!!
632 */
633 pattern = get_unaligned_be32(scratch->status);
634
635 /* First 3 bit of pattern are undefined */
636 pattern |= 0xE0000000;
637
638 /* left-adjust to leading 0 bit */
639 while (pattern & 0x80000000)
640 pattern <<= 1;
641 /* right-adjust for pattern matching. Code is in bit 4..0 now. */
642 pattern >>= 27;
643
644 switch (pattern) {
645 case SPI_RESPONSE_ACCEPTED:
646 status = 0;
647 break;
648 case SPI_RESPONSE_CRC_ERR:
649 /* host shall then issue MMC_STOP_TRANSMISSION */
650 status = -EILSEQ;
651 break;
652 case SPI_RESPONSE_WRITE_ERR:
653 /* host shall then issue MMC_STOP_TRANSMISSION,
654 * and should MMC_SEND_STATUS to sort it out
655 */
656 status = -EIO;
657 break;
658 default:
659 status = -EPROTO;
660 break;
661 }
662 if (status != 0) {
663 dev_dbg(&spi->dev, "write error %02x (%d)\n",
664 scratch->status[0], status);
665 return status;
666 }
667
668 t->tx_buf += t->len;
669
670 /* Return when not busy. If we didn't collect that status yet,
671 * we'll need some more I/O.
672 */
673 for (i = 4; i < sizeof(scratch->status); i++) {
674 /* card is non-busy if the most recent bit is 1 */
675 if (scratch->status[i] & 0x01)
676 return 0;
677 }
678 return mmc_spi_wait_unbusy(host, timeout);
679 }
680
681 /*
682 * Read one block:
683 * - skip leading all-ones bytes ... either
684 * + N(AC) [1..f(clock,CSD)] usually, else
685 * + N(CX) [0..8] when reading CSD or CID
686 * - data block
687 * + token ... if error token, no data or crc
688 * + data bytes
689 * + crc16
690 *
691 * After single block reads, we're done; N(EC) [0+] all-ones bytes follow
692 * before dropping chipselect.
693 *
694 * For multiblock reads, caller either reads the next block or issues a
695 * STOP_TRANSMISSION command.
696 */
697 static int
mmc_spi_readblock(struct mmc_spi_host * host,struct spi_transfer * t,unsigned long timeout)698 mmc_spi_readblock(struct mmc_spi_host *host, struct spi_transfer *t,
699 unsigned long timeout)
700 {
701 struct spi_device *spi = host->spi;
702 int status;
703 struct scratch *scratch = host->data;
704 unsigned int bitshift;
705 u8 leftover;
706
707 /* At least one SD card sends an all-zeroes byte when N(CX)
708 * applies, before the all-ones bytes ... just cope with that.
709 */
710 status = mmc_spi_readbytes(host, 1);
711 if (status < 0)
712 return status;
713 status = scratch->status[0];
714 if (status == 0xff || status == 0)
715 status = mmc_spi_readtoken(host, timeout);
716
717 if (status < 0) {
718 dev_dbg(&spi->dev, "read error %02x (%d)\n", status, status);
719 return status;
720 }
721
722 /* The token may be bit-shifted...
723 * the first 0-bit precedes the data stream.
724 */
725 bitshift = 7;
726 while (status & 0x80) {
727 status <<= 1;
728 bitshift--;
729 }
730 leftover = status << 1;
731
732 status = spi_sync_locked(spi, &host->m);
733 if (status < 0) {
734 dev_dbg(&spi->dev, "read error %d\n", status);
735 return status;
736 }
737
738 if (bitshift) {
739 /* Walk through the data and the crc and do
740 * all the magic to get byte-aligned data.
741 */
742 u8 *cp = t->rx_buf;
743 unsigned int len;
744 unsigned int bitright = 8 - bitshift;
745 u8 temp;
746 for (len = t->len; len; len--) {
747 temp = *cp;
748 *cp++ = leftover | (temp >> bitshift);
749 leftover = temp << bitright;
750 }
751 cp = (u8 *) &scratch->crc_val;
752 temp = *cp;
753 *cp++ = leftover | (temp >> bitshift);
754 leftover = temp << bitright;
755 temp = *cp;
756 *cp = leftover | (temp >> bitshift);
757 }
758
759 if (host->mmc->use_spi_crc) {
760 u16 crc = crc_itu_t(0, t->rx_buf, t->len);
761
762 be16_to_cpus(&scratch->crc_val);
763 if (scratch->crc_val != crc) {
764 dev_dbg(&spi->dev,
765 "read - crc error: crc_val=0x%04x, computed=0x%04x len=%d\n",
766 scratch->crc_val, crc, t->len);
767 return -EILSEQ;
768 }
769 }
770
771 t->rx_buf += t->len;
772
773 return 0;
774 }
775
776 /*
777 * An MMC/SD data stage includes one or more blocks, optional CRCs,
778 * and inline handshaking. That handhaking makes it unlike most
779 * other SPI protocol stacks.
780 */
781 static void
mmc_spi_data_do(struct mmc_spi_host * host,struct mmc_command * cmd,struct mmc_data * data,u32 blk_size)782 mmc_spi_data_do(struct mmc_spi_host *host, struct mmc_command *cmd,
783 struct mmc_data *data, u32 blk_size)
784 {
785 struct spi_device *spi = host->spi;
786 struct spi_transfer *t;
787 enum dma_data_direction direction;
788 struct scatterlist *sg;
789 unsigned n_sg;
790 int multiple = (data->blocks > 1);
791 u32 clock_rate;
792 unsigned long timeout;
793
794 direction = mmc_get_dma_dir(data);
795 mmc_spi_setup_data_message(host, multiple, direction);
796 t = &host->t;
797
798 if (t->speed_hz)
799 clock_rate = t->speed_hz;
800 else
801 clock_rate = spi->max_speed_hz;
802
803 timeout = data->timeout_ns / 1000 +
804 data->timeout_clks * 1000000 / clock_rate;
805 timeout = usecs_to_jiffies((unsigned int)timeout) + 1;
806
807 /* Handle scatterlist segments one at a time, with synch for
808 * each 512-byte block
809 */
810 for_each_sg(data->sg, sg, data->sg_len, n_sg) {
811 int status = 0;
812 void *kmap_addr;
813 unsigned length = sg->length;
814
815 /* allow pio too; we don't allow highmem */
816 kmap_addr = kmap(sg_page(sg));
817 if (direction == DMA_TO_DEVICE)
818 t->tx_buf = kmap_addr + sg->offset;
819 else
820 t->rx_buf = kmap_addr + sg->offset;
821
822 /* transfer each block, and update request status */
823 while (length) {
824 t->len = min(length, blk_size);
825
826 dev_dbg(&host->spi->dev,
827 " mmc_spi: %s block, %d bytes\n",
828 (direction == DMA_TO_DEVICE) ? "write" : "read",
829 t->len);
830
831 if (direction == DMA_TO_DEVICE)
832 status = mmc_spi_writeblock(host, t, timeout);
833 else
834 status = mmc_spi_readblock(host, t, timeout);
835 if (status < 0)
836 break;
837
838 data->bytes_xfered += t->len;
839 length -= t->len;
840
841 if (!multiple)
842 break;
843 }
844
845 /* discard mappings */
846 if (direction == DMA_FROM_DEVICE)
847 flush_kernel_dcache_page(sg_page(sg));
848 kunmap(sg_page(sg));
849
850 if (status < 0) {
851 data->error = status;
852 dev_dbg(&spi->dev, "%s status %d\n",
853 (direction == DMA_TO_DEVICE) ? "write" : "read",
854 status);
855 break;
856 }
857 }
858
859 /* NOTE some docs describe an MMC-only SET_BLOCK_COUNT (CMD23) that
860 * can be issued before multiblock writes. Unlike its more widely
861 * documented analogue for SD cards (SET_WR_BLK_ERASE_COUNT, ACMD23),
862 * that can affect the STOP_TRAN logic. Complete (and current)
863 * MMC specs should sort that out before Linux starts using CMD23.
864 */
865 if (direction == DMA_TO_DEVICE && multiple) {
866 struct scratch *scratch = host->data;
867 int tmp;
868 const unsigned statlen = sizeof(scratch->status);
869
870 dev_dbg(&spi->dev, " mmc_spi: STOP_TRAN\n");
871
872 /* Tweak the per-block message we set up earlier by morphing
873 * it to hold single buffer with the token followed by some
874 * all-ones bytes ... skip N(BR) (0..1), scan the rest for
875 * "not busy any longer" status, and leave chip selected.
876 */
877 INIT_LIST_HEAD(&host->m.transfers);
878 list_add(&host->early_status.transfer_list,
879 &host->m.transfers);
880
881 memset(scratch->status, 0xff, statlen);
882 scratch->status[0] = SPI_TOKEN_STOP_TRAN;
883
884 host->early_status.tx_buf = host->early_status.rx_buf;
885 host->early_status.len = statlen;
886
887 tmp = spi_sync_locked(spi, &host->m);
888 if (tmp < 0) {
889 if (!data->error)
890 data->error = tmp;
891 return;
892 }
893
894 /* Ideally we collected "not busy" status with one I/O,
895 * avoiding wasteful byte-at-a-time scanning... but more
896 * I/O is often needed.
897 */
898 for (tmp = 2; tmp < statlen; tmp++) {
899 if (scratch->status[tmp] != 0)
900 return;
901 }
902 tmp = mmc_spi_wait_unbusy(host, timeout);
903 if (tmp < 0 && !data->error)
904 data->error = tmp;
905 }
906 }
907
908 /****************************************************************************/
909
910 /*
911 * MMC driver implementation -- the interface to the MMC stack
912 */
913
mmc_spi_request(struct mmc_host * mmc,struct mmc_request * mrq)914 static void mmc_spi_request(struct mmc_host *mmc, struct mmc_request *mrq)
915 {
916 struct mmc_spi_host *host = mmc_priv(mmc);
917 int status = -EINVAL;
918 int crc_retry = 5;
919 struct mmc_command stop;
920
921 #ifdef DEBUG
922 /* MMC core and layered drivers *MUST* issue SPI-aware commands */
923 {
924 struct mmc_command *cmd;
925 int invalid = 0;
926
927 cmd = mrq->cmd;
928 if (!mmc_spi_resp_type(cmd)) {
929 dev_dbg(&host->spi->dev, "bogus command\n");
930 cmd->error = -EINVAL;
931 invalid = 1;
932 }
933
934 cmd = mrq->stop;
935 if (cmd && !mmc_spi_resp_type(cmd)) {
936 dev_dbg(&host->spi->dev, "bogus STOP command\n");
937 cmd->error = -EINVAL;
938 invalid = 1;
939 }
940
941 if (invalid) {
942 dump_stack();
943 mmc_request_done(host->mmc, mrq);
944 return;
945 }
946 }
947 #endif
948
949 /* request exclusive bus access */
950 spi_bus_lock(host->spi->master);
951
952 crc_recover:
953 /* issue command; then optionally data and stop */
954 status = mmc_spi_command_send(host, mrq, mrq->cmd, mrq->data != NULL);
955 if (status == 0 && mrq->data) {
956 mmc_spi_data_do(host, mrq->cmd, mrq->data, mrq->data->blksz);
957
958 /*
959 * The SPI bus is not always reliable for large data transfers.
960 * If an occasional crc error is reported by the SD device with
961 * data read/write over SPI, it may be recovered by repeating
962 * the last SD command again. The retry count is set to 5 to
963 * ensure the driver passes stress tests.
964 */
965 if (mrq->data->error == -EILSEQ && crc_retry) {
966 stop.opcode = MMC_STOP_TRANSMISSION;
967 stop.arg = 0;
968 stop.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC;
969 status = mmc_spi_command_send(host, mrq, &stop, 0);
970 crc_retry--;
971 mrq->data->error = 0;
972 goto crc_recover;
973 }
974
975 if (mrq->stop)
976 status = mmc_spi_command_send(host, mrq, mrq->stop, 0);
977 else
978 mmc_cs_off(host);
979 }
980
981 /* release the bus */
982 spi_bus_unlock(host->spi->master);
983
984 mmc_request_done(host->mmc, mrq);
985 }
986
987 /* See Section 6.4.1, in SD "Simplified Physical Layer Specification 2.0"
988 *
989 * NOTE that here we can't know that the card has just been powered up;
990 * not all MMC/SD sockets support power switching.
991 *
992 * FIXME when the card is still in SPI mode, e.g. from a previous kernel,
993 * this doesn't seem to do the right thing at all...
994 */
mmc_spi_initsequence(struct mmc_spi_host * host)995 static void mmc_spi_initsequence(struct mmc_spi_host *host)
996 {
997 /* Try to be very sure any previous command has completed;
998 * wait till not-busy, skip debris from any old commands.
999 */
1000 mmc_spi_wait_unbusy(host, msecs_to_jiffies(MMC_SPI_INIT_TIMEOUT_MS));
1001 mmc_spi_readbytes(host, 10);
1002
1003 /*
1004 * Do a burst with chipselect active-high. We need to do this to
1005 * meet the requirement of 74 clock cycles with both chipselect
1006 * and CMD (MOSI) high before CMD0 ... after the card has been
1007 * powered up to Vdd(min), and so is ready to take commands.
1008 *
1009 * Some cards are particularly needy of this (e.g. Viking "SD256")
1010 * while most others don't seem to care.
1011 *
1012 * Note that this is one of the places MMC/SD plays games with the
1013 * SPI protocol. Another is that when chipselect is released while
1014 * the card returns BUSY status, the clock must issue several cycles
1015 * with chipselect high before the card will stop driving its output.
1016 *
1017 * SPI_CS_HIGH means "asserted" here. In some cases like when using
1018 * GPIOs for chip select, SPI_CS_HIGH is set but this will be logically
1019 * inverted by gpiolib, so if we want to ascertain to drive it high
1020 * we should toggle the default with an XOR as we do here.
1021 */
1022 host->spi->mode ^= SPI_CS_HIGH;
1023 if (spi_setup(host->spi) != 0) {
1024 /* Just warn; most cards work without it. */
1025 dev_warn(&host->spi->dev,
1026 "can't change chip-select polarity\n");
1027 host->spi->mode ^= SPI_CS_HIGH;
1028 } else {
1029 mmc_spi_readbytes(host, 18);
1030
1031 host->spi->mode ^= SPI_CS_HIGH;
1032 if (spi_setup(host->spi) != 0) {
1033 /* Wot, we can't get the same setup we had before? */
1034 dev_err(&host->spi->dev,
1035 "can't restore chip-select polarity\n");
1036 }
1037 }
1038 }
1039
mmc_powerstring(u8 power_mode)1040 static char *mmc_powerstring(u8 power_mode)
1041 {
1042 switch (power_mode) {
1043 case MMC_POWER_OFF: return "off";
1044 case MMC_POWER_UP: return "up";
1045 case MMC_POWER_ON: return "on";
1046 }
1047 return "?";
1048 }
1049
mmc_spi_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)1050 static void mmc_spi_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1051 {
1052 struct mmc_spi_host *host = mmc_priv(mmc);
1053
1054 if (host->power_mode != ios->power_mode) {
1055 int canpower;
1056
1057 canpower = host->pdata && host->pdata->setpower;
1058
1059 dev_dbg(&host->spi->dev, "mmc_spi: power %s (%d)%s\n",
1060 mmc_powerstring(ios->power_mode),
1061 ios->vdd,
1062 canpower ? ", can switch" : "");
1063
1064 /* switch power on/off if possible, accounting for
1065 * max 250msec powerup time if needed.
1066 */
1067 if (canpower) {
1068 switch (ios->power_mode) {
1069 case MMC_POWER_OFF:
1070 case MMC_POWER_UP:
1071 host->pdata->setpower(&host->spi->dev,
1072 ios->vdd);
1073 if (ios->power_mode == MMC_POWER_UP)
1074 msleep(host->powerup_msecs);
1075 }
1076 }
1077
1078 /* See 6.4.1 in the simplified SD card physical spec 2.0 */
1079 if (ios->power_mode == MMC_POWER_ON)
1080 mmc_spi_initsequence(host);
1081
1082 /* If powering down, ground all card inputs to avoid power
1083 * delivery from data lines! On a shared SPI bus, this
1084 * will probably be temporary; 6.4.2 of the simplified SD
1085 * spec says this must last at least 1msec.
1086 *
1087 * - Clock low means CPOL 0, e.g. mode 0
1088 * - MOSI low comes from writing zero
1089 * - Chipselect is usually active low...
1090 */
1091 if (canpower && ios->power_mode == MMC_POWER_OFF) {
1092 int mres;
1093 u8 nullbyte = 0;
1094
1095 host->spi->mode &= ~(SPI_CPOL|SPI_CPHA);
1096 mres = spi_setup(host->spi);
1097 if (mres < 0)
1098 dev_dbg(&host->spi->dev,
1099 "switch to SPI mode 0 failed\n");
1100
1101 if (spi_write(host->spi, &nullbyte, 1) < 0)
1102 dev_dbg(&host->spi->dev,
1103 "put spi signals to low failed\n");
1104
1105 /*
1106 * Now clock should be low due to spi mode 0;
1107 * MOSI should be low because of written 0x00;
1108 * chipselect should be low (it is active low)
1109 * power supply is off, so now MMC is off too!
1110 *
1111 * FIXME no, chipselect can be high since the
1112 * device is inactive and SPI_CS_HIGH is clear...
1113 */
1114 msleep(10);
1115 if (mres == 0) {
1116 host->spi->mode |= (SPI_CPOL|SPI_CPHA);
1117 mres = spi_setup(host->spi);
1118 if (mres < 0)
1119 dev_dbg(&host->spi->dev,
1120 "switch back to SPI mode 3 failed\n");
1121 }
1122 }
1123
1124 host->power_mode = ios->power_mode;
1125 }
1126
1127 if (host->spi->max_speed_hz != ios->clock && ios->clock != 0) {
1128 int status;
1129
1130 host->spi->max_speed_hz = ios->clock;
1131 status = spi_setup(host->spi);
1132 dev_dbg(&host->spi->dev,
1133 "mmc_spi: clock to %d Hz, %d\n",
1134 host->spi->max_speed_hz, status);
1135 }
1136 }
1137
1138 static const struct mmc_host_ops mmc_spi_ops = {
1139 .request = mmc_spi_request,
1140 .set_ios = mmc_spi_set_ios,
1141 .get_ro = mmc_gpio_get_ro,
1142 .get_cd = mmc_gpio_get_cd,
1143 };
1144
1145
1146 /****************************************************************************/
1147
1148 /*
1149 * SPI driver implementation
1150 */
1151
1152 static irqreturn_t
mmc_spi_detect_irq(int irq,void * mmc)1153 mmc_spi_detect_irq(int irq, void *mmc)
1154 {
1155 struct mmc_spi_host *host = mmc_priv(mmc);
1156 u16 delay_msec = max(host->pdata->detect_delay, (u16)100);
1157
1158 mmc_detect_change(mmc, msecs_to_jiffies(delay_msec));
1159 return IRQ_HANDLED;
1160 }
1161
mmc_spi_probe(struct spi_device * spi)1162 static int mmc_spi_probe(struct spi_device *spi)
1163 {
1164 void *ones;
1165 struct mmc_host *mmc;
1166 struct mmc_spi_host *host;
1167 int status;
1168 bool has_ro = false;
1169
1170 /* We rely on full duplex transfers, mostly to reduce
1171 * per-transfer overheads (by making fewer transfers).
1172 */
1173 if (spi->master->flags & SPI_MASTER_HALF_DUPLEX)
1174 return -EINVAL;
1175
1176 /* MMC and SD specs only seem to care that sampling is on the
1177 * rising edge ... meaning SPI modes 0 or 3. So either SPI mode
1178 * should be legit. We'll use mode 0 since the steady state is 0,
1179 * which is appropriate for hotplugging, unless the platform data
1180 * specify mode 3 (if hardware is not compatible to mode 0).
1181 */
1182 if (spi->mode != SPI_MODE_3)
1183 spi->mode = SPI_MODE_0;
1184 spi->bits_per_word = 8;
1185
1186 status = spi_setup(spi);
1187 if (status < 0) {
1188 dev_dbg(&spi->dev, "needs SPI mode %02x, %d KHz; %d\n",
1189 spi->mode, spi->max_speed_hz / 1000,
1190 status);
1191 return status;
1192 }
1193
1194 /* We need a supply of ones to transmit. This is the only time
1195 * the CPU touches these, so cache coherency isn't a concern.
1196 *
1197 * NOTE if many systems use more than one MMC-over-SPI connector
1198 * it'd save some memory to share this. That's evidently rare.
1199 */
1200 status = -ENOMEM;
1201 ones = kmalloc(MMC_SPI_BLOCKSIZE, GFP_KERNEL);
1202 if (!ones)
1203 goto nomem;
1204 memset(ones, 0xff, MMC_SPI_BLOCKSIZE);
1205
1206 mmc = mmc_alloc_host(sizeof(*host), &spi->dev);
1207 if (!mmc)
1208 goto nomem;
1209
1210 mmc->ops = &mmc_spi_ops;
1211 mmc->max_blk_size = MMC_SPI_BLOCKSIZE;
1212 mmc->max_segs = MMC_SPI_BLOCKSATONCE;
1213 mmc->max_req_size = MMC_SPI_BLOCKSATONCE * MMC_SPI_BLOCKSIZE;
1214 mmc->max_blk_count = MMC_SPI_BLOCKSATONCE;
1215
1216 mmc->caps = MMC_CAP_SPI;
1217
1218 /* SPI doesn't need the lowspeed device identification thing for
1219 * MMC or SD cards, since it never comes up in open drain mode.
1220 * That's good; some SPI masters can't handle very low speeds!
1221 *
1222 * However, low speed SDIO cards need not handle over 400 KHz;
1223 * that's the only reason not to use a few MHz for f_min (until
1224 * the upper layer reads the target frequency from the CSD).
1225 */
1226 mmc->f_min = 400000;
1227 mmc->f_max = spi->max_speed_hz;
1228
1229 host = mmc_priv(mmc);
1230 host->mmc = mmc;
1231 host->spi = spi;
1232
1233 host->ones = ones;
1234
1235 /* Platform data is used to hook up things like card sensing
1236 * and power switching gpios.
1237 */
1238 host->pdata = mmc_spi_get_pdata(spi);
1239 if (host->pdata)
1240 mmc->ocr_avail = host->pdata->ocr_mask;
1241 if (!mmc->ocr_avail) {
1242 dev_warn(&spi->dev, "ASSUMING 3.2-3.4 V slot power\n");
1243 mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34;
1244 }
1245 if (host->pdata && host->pdata->setpower) {
1246 host->powerup_msecs = host->pdata->powerup_msecs;
1247 if (!host->powerup_msecs || host->powerup_msecs > 250)
1248 host->powerup_msecs = 250;
1249 }
1250
1251 dev_set_drvdata(&spi->dev, mmc);
1252
1253 /* Preallocate buffers */
1254 host->data = kmalloc(sizeof(*host->data), GFP_KERNEL);
1255 if (!host->data)
1256 goto fail_nobuf1;
1257
1258 /* setup message for status/busy readback */
1259 spi_message_init(&host->readback);
1260
1261 spi_message_add_tail(&host->status, &host->readback);
1262 host->status.tx_buf = host->ones;
1263 host->status.rx_buf = &host->data->status;
1264 host->status.cs_change = 1;
1265
1266 /* register card detect irq */
1267 if (host->pdata && host->pdata->init) {
1268 status = host->pdata->init(&spi->dev, mmc_spi_detect_irq, mmc);
1269 if (status != 0)
1270 goto fail_glue_init;
1271 }
1272
1273 /* pass platform capabilities, if any */
1274 if (host->pdata) {
1275 mmc->caps |= host->pdata->caps;
1276 mmc->caps2 |= host->pdata->caps2;
1277 }
1278
1279 status = mmc_add_host(mmc);
1280 if (status != 0)
1281 goto fail_glue_init;
1282
1283 /*
1284 * Index 0 is card detect
1285 * Old boardfiles were specifying 1 ms as debounce
1286 */
1287 status = mmc_gpiod_request_cd(mmc, NULL, 0, false, 1000);
1288 if (status == -EPROBE_DEFER)
1289 goto fail_gpiod_request;
1290 if (!status) {
1291 /*
1292 * The platform has a CD GPIO signal that may support
1293 * interrupts, so let mmc_gpiod_request_cd_irq() decide
1294 * if polling is needed or not.
1295 */
1296 mmc->caps &= ~MMC_CAP_NEEDS_POLL;
1297 mmc_gpiod_request_cd_irq(mmc);
1298 }
1299 mmc_detect_change(mmc, 0);
1300
1301 /* Index 1 is write protect/read only */
1302 status = mmc_gpiod_request_ro(mmc, NULL, 1, 0);
1303 if (status == -EPROBE_DEFER)
1304 goto fail_gpiod_request;
1305 if (!status)
1306 has_ro = true;
1307
1308 dev_info(&spi->dev, "SD/MMC host %s%s%s%s\n",
1309 dev_name(&mmc->class_dev),
1310 has_ro ? "" : ", no WP",
1311 (host->pdata && host->pdata->setpower)
1312 ? "" : ", no poweroff",
1313 (mmc->caps & MMC_CAP_NEEDS_POLL)
1314 ? ", cd polling" : "");
1315 return 0;
1316
1317 fail_gpiod_request:
1318 mmc_remove_host(mmc);
1319 fail_glue_init:
1320 kfree(host->data);
1321 fail_nobuf1:
1322 mmc_free_host(mmc);
1323 mmc_spi_put_pdata(spi);
1324 nomem:
1325 kfree(ones);
1326 return status;
1327 }
1328
1329
mmc_spi_remove(struct spi_device * spi)1330 static int mmc_spi_remove(struct spi_device *spi)
1331 {
1332 struct mmc_host *mmc = dev_get_drvdata(&spi->dev);
1333 struct mmc_spi_host *host = mmc_priv(mmc);
1334
1335 /* prevent new mmc_detect_change() calls */
1336 if (host->pdata && host->pdata->exit)
1337 host->pdata->exit(&spi->dev, mmc);
1338
1339 mmc_remove_host(mmc);
1340
1341 kfree(host->data);
1342 kfree(host->ones);
1343
1344 spi->max_speed_hz = mmc->f_max;
1345 mmc_free_host(mmc);
1346 mmc_spi_put_pdata(spi);
1347 return 0;
1348 }
1349
1350 static const struct of_device_id mmc_spi_of_match_table[] = {
1351 { .compatible = "mmc-spi-slot", },
1352 {},
1353 };
1354 MODULE_DEVICE_TABLE(of, mmc_spi_of_match_table);
1355
1356 static struct spi_driver mmc_spi_driver = {
1357 .driver = {
1358 .name = "mmc_spi",
1359 .of_match_table = mmc_spi_of_match_table,
1360 },
1361 .probe = mmc_spi_probe,
1362 .remove = mmc_spi_remove,
1363 };
1364
1365 module_spi_driver(mmc_spi_driver);
1366
1367 MODULE_AUTHOR("Mike Lavender, David Brownell, Hans-Peter Nilsson, Jan Nikitenko");
1368 MODULE_DESCRIPTION("SPI SD/MMC host driver");
1369 MODULE_LICENSE("GPL");
1370 MODULE_ALIAS("spi:mmc_spi");
1371