1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
3
4 #include <linux/clk.h>
5 #include <linux/console.h>
6 #include <linux/io.h>
7 #include <linux/iopoll.h>
8 #include <linux/irq.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_device.h>
12 #include <linux/pm_opp.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/pm_wakeirq.h>
16 #include <linux/qcom-geni-se.h>
17 #include <linux/serial.h>
18 #include <linux/serial_core.h>
19 #include <linux/slab.h>
20 #include <linux/tty.h>
21 #include <linux/tty_flip.h>
22
23 /* UART specific GENI registers */
24 #define SE_UART_LOOPBACK_CFG 0x22c
25 #define SE_UART_IO_MACRO_CTRL 0x240
26 #define SE_UART_TX_TRANS_CFG 0x25c
27 #define SE_UART_TX_WORD_LEN 0x268
28 #define SE_UART_TX_STOP_BIT_LEN 0x26c
29 #define SE_UART_TX_TRANS_LEN 0x270
30 #define SE_UART_RX_TRANS_CFG 0x280
31 #define SE_UART_RX_WORD_LEN 0x28c
32 #define SE_UART_RX_STALE_CNT 0x294
33 #define SE_UART_TX_PARITY_CFG 0x2a4
34 #define SE_UART_RX_PARITY_CFG 0x2a8
35 #define SE_UART_MANUAL_RFR 0x2ac
36
37 /* SE_UART_TRANS_CFG */
38 #define UART_TX_PAR_EN BIT(0)
39 #define UART_CTS_MASK BIT(1)
40
41 /* SE_UART_TX_WORD_LEN */
42 #define TX_WORD_LEN_MSK GENMASK(9, 0)
43
44 /* SE_UART_TX_STOP_BIT_LEN */
45 #define TX_STOP_BIT_LEN_MSK GENMASK(23, 0)
46 #define TX_STOP_BIT_LEN_1 0
47 #define TX_STOP_BIT_LEN_1_5 1
48 #define TX_STOP_BIT_LEN_2 2
49
50 /* SE_UART_TX_TRANS_LEN */
51 #define TX_TRANS_LEN_MSK GENMASK(23, 0)
52
53 /* SE_UART_RX_TRANS_CFG */
54 #define UART_RX_INS_STATUS_BIT BIT(2)
55 #define UART_RX_PAR_EN BIT(3)
56
57 /* SE_UART_RX_WORD_LEN */
58 #define RX_WORD_LEN_MASK GENMASK(9, 0)
59
60 /* SE_UART_RX_STALE_CNT */
61 #define RX_STALE_CNT GENMASK(23, 0)
62
63 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
64 #define PAR_CALC_EN BIT(0)
65 #define PAR_MODE_MSK GENMASK(2, 1)
66 #define PAR_MODE_SHFT 1
67 #define PAR_EVEN 0x00
68 #define PAR_ODD 0x01
69 #define PAR_SPACE 0x10
70 #define PAR_MARK 0x11
71
72 /* SE_UART_MANUAL_RFR register fields */
73 #define UART_MANUAL_RFR_EN BIT(31)
74 #define UART_RFR_NOT_READY BIT(1)
75 #define UART_RFR_READY BIT(0)
76
77 /* UART M_CMD OP codes */
78 #define UART_START_TX 0x1
79 #define UART_START_BREAK 0x4
80 #define UART_STOP_BREAK 0x5
81 /* UART S_CMD OP codes */
82 #define UART_START_READ 0x1
83 #define UART_PARAM 0x1
84
85 #define UART_OVERSAMPLING 32
86 #define STALE_TIMEOUT 16
87 #define DEFAULT_BITS_PER_CHAR 10
88 #define GENI_UART_CONS_PORTS 1
89 #define GENI_UART_PORTS 3
90 #define DEF_FIFO_DEPTH_WORDS 16
91 #define DEF_TX_WM 2
92 #define DEF_FIFO_WIDTH_BITS 32
93 #define UART_RX_WM 2
94
95 /* SE_UART_LOOPBACK_CFG */
96 #define RX_TX_SORTED BIT(0)
97 #define CTS_RTS_SORTED BIT(1)
98 #define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED)
99
100 /* UART pin swap value */
101 #define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0)
102 #define IO_MACRO_IO0_SEL 0x3
103 #define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4)
104 #define IO_MACRO_IO2_IO3_SWAP 0x4640
105
106 /* We always configure 4 bytes per FIFO word */
107 #define BYTES_PER_FIFO_WORD 4
108
109 struct qcom_geni_private_data {
110 /* NOTE: earlycon port will have NULL here */
111 struct uart_driver *drv;
112
113 u32 poll_cached_bytes;
114 unsigned int poll_cached_bytes_cnt;
115
116 u32 write_cached_bytes;
117 unsigned int write_cached_bytes_cnt;
118 };
119
120 struct qcom_geni_serial_port {
121 struct uart_port uport;
122 struct geni_se se;
123 const char *name;
124 u32 tx_fifo_depth;
125 u32 tx_fifo_width;
126 u32 rx_fifo_depth;
127 bool setup;
128 unsigned long clk_rate;
129 int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
130 unsigned int baud;
131 void *rx_fifo;
132 u32 loopback;
133 bool brk;
134
135 unsigned int tx_remaining;
136 int wakeup_irq;
137 bool rx_tx_swap;
138 bool cts_rts_swap;
139
140 struct qcom_geni_private_data private_data;
141 };
142
143 static const struct uart_ops qcom_geni_console_pops;
144 static const struct uart_ops qcom_geni_uart_pops;
145 static struct uart_driver qcom_geni_console_driver;
146 static struct uart_driver qcom_geni_uart_driver;
147 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
148 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
149 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
150 static void qcom_geni_serial_stop_rx(struct uart_port *uport);
151 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop);
152
153 static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
154 32000000, 48000000, 51200000, 64000000,
155 80000000, 96000000, 100000000,
156 102400000, 112000000, 120000000,
157 128000000};
158
159 #define to_dev_port(ptr, member) \
160 container_of(ptr, struct qcom_geni_serial_port, member)
161
162 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
163 [0] = {
164 .uport = {
165 .iotype = UPIO_MEM,
166 .ops = &qcom_geni_uart_pops,
167 .flags = UPF_BOOT_AUTOCONF,
168 .line = 0,
169 },
170 },
171 [1] = {
172 .uport = {
173 .iotype = UPIO_MEM,
174 .ops = &qcom_geni_uart_pops,
175 .flags = UPF_BOOT_AUTOCONF,
176 .line = 1,
177 },
178 },
179 [2] = {
180 .uport = {
181 .iotype = UPIO_MEM,
182 .ops = &qcom_geni_uart_pops,
183 .flags = UPF_BOOT_AUTOCONF,
184 .line = 2,
185 },
186 },
187 };
188
189 static struct qcom_geni_serial_port qcom_geni_console_port = {
190 .uport = {
191 .iotype = UPIO_MEM,
192 .ops = &qcom_geni_console_pops,
193 .flags = UPF_BOOT_AUTOCONF,
194 .line = 0,
195 },
196 };
197
qcom_geni_serial_request_port(struct uart_port * uport)198 static int qcom_geni_serial_request_port(struct uart_port *uport)
199 {
200 struct platform_device *pdev = to_platform_device(uport->dev);
201 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
202
203 uport->membase = devm_platform_ioremap_resource(pdev, 0);
204 if (IS_ERR(uport->membase))
205 return PTR_ERR(uport->membase);
206 port->se.base = uport->membase;
207 return 0;
208 }
209
qcom_geni_serial_config_port(struct uart_port * uport,int cfg_flags)210 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
211 {
212 if (cfg_flags & UART_CONFIG_TYPE) {
213 uport->type = PORT_MSM;
214 qcom_geni_serial_request_port(uport);
215 }
216 }
217
qcom_geni_serial_get_mctrl(struct uart_port * uport)218 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
219 {
220 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
221 u32 geni_ios;
222
223 if (uart_console(uport)) {
224 mctrl |= TIOCM_CTS;
225 } else {
226 geni_ios = readl(uport->membase + SE_GENI_IOS);
227 if (!(geni_ios & IO2_DATA_IN))
228 mctrl |= TIOCM_CTS;
229 }
230
231 return mctrl;
232 }
233
qcom_geni_serial_set_mctrl(struct uart_port * uport,unsigned int mctrl)234 static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
235 unsigned int mctrl)
236 {
237 u32 uart_manual_rfr = 0;
238 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
239
240 if (uart_console(uport))
241 return;
242
243 if (mctrl & TIOCM_LOOP)
244 port->loopback = RX_TX_CTS_RTS_SORTED;
245
246 if (!(mctrl & TIOCM_RTS) && !uport->suspended)
247 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
248 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
249 }
250
qcom_geni_serial_get_type(struct uart_port * uport)251 static const char *qcom_geni_serial_get_type(struct uart_port *uport)
252 {
253 return "MSM";
254 }
255
get_port_from_line(int line,bool console)256 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
257 {
258 struct qcom_geni_serial_port *port;
259 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
260
261 if (line < 0 || line >= nr_ports)
262 return ERR_PTR(-ENXIO);
263
264 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
265 return port;
266 }
267
qcom_geni_serial_poll_bit(struct uart_port * uport,int offset,int field,bool set)268 static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
269 int offset, int field, bool set)
270 {
271 u32 reg;
272 struct qcom_geni_serial_port *port;
273 unsigned int baud;
274 unsigned int fifo_bits;
275 unsigned long timeout_us = 20000;
276 struct qcom_geni_private_data *private_data = uport->private_data;
277
278 if (private_data->drv) {
279 port = to_dev_port(uport, uport);
280 baud = port->baud;
281 if (!baud)
282 baud = 115200;
283 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
284 /*
285 * Total polling iterations based on FIFO worth of bytes to be
286 * sent at current baud. Add a little fluff to the wait.
287 */
288 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
289 }
290
291 /*
292 * Use custom implementation instead of readl_poll_atomic since ktimer
293 * is not ready at the time of early console.
294 */
295 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
296 while (timeout_us) {
297 reg = readl(uport->membase + offset);
298 if ((bool)(reg & field) == set)
299 return true;
300 udelay(10);
301 timeout_us -= 10;
302 }
303 return false;
304 }
305
qcom_geni_serial_setup_tx(struct uart_port * uport,u32 xmit_size)306 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
307 {
308 u32 m_cmd;
309
310 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
311 m_cmd = UART_START_TX << M_OPCODE_SHFT;
312 writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
313 }
314
qcom_geni_serial_poll_tx_done(struct uart_port * uport)315 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
316 {
317 int done;
318 u32 irq_clear = M_CMD_DONE_EN;
319
320 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
321 M_CMD_DONE_EN, true);
322 if (!done) {
323 writel(M_GENI_CMD_ABORT, uport->membase +
324 SE_GENI_M_CMD_CTRL_REG);
325 irq_clear |= M_CMD_ABORT_EN;
326 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
327 M_CMD_ABORT_EN, true);
328 }
329 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
330 }
331
qcom_geni_serial_abort_rx(struct uart_port * uport)332 static void qcom_geni_serial_abort_rx(struct uart_port *uport)
333 {
334 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
335
336 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
337 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
338 S_GENI_CMD_ABORT, false);
339 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
340 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
341 }
342
343 #ifdef CONFIG_CONSOLE_POLL
344
qcom_geni_serial_get_char(struct uart_port * uport)345 static int qcom_geni_serial_get_char(struct uart_port *uport)
346 {
347 struct qcom_geni_private_data *private_data = uport->private_data;
348 u32 status;
349 u32 word_cnt;
350 int ret;
351
352 if (!private_data->poll_cached_bytes_cnt) {
353 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
354 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
355
356 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
357 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
358
359 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
360 word_cnt = status & RX_FIFO_WC_MSK;
361 if (!word_cnt)
362 return NO_POLL_CHAR;
363
364 if (word_cnt == 1 && (status & RX_LAST))
365 /*
366 * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be
367 * treated as if it was BYTES_PER_FIFO_WORD.
368 */
369 private_data->poll_cached_bytes_cnt =
370 (status & RX_LAST_BYTE_VALID_MSK) >>
371 RX_LAST_BYTE_VALID_SHFT;
372
373 if (private_data->poll_cached_bytes_cnt == 0)
374 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD;
375
376 private_data->poll_cached_bytes =
377 readl(uport->membase + SE_GENI_RX_FIFOn);
378 }
379
380 private_data->poll_cached_bytes_cnt--;
381 ret = private_data->poll_cached_bytes & 0xff;
382 private_data->poll_cached_bytes >>= 8;
383
384 return ret;
385 }
386
qcom_geni_serial_poll_put_char(struct uart_port * uport,unsigned char c)387 static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
388 unsigned char c)
389 {
390 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
391 qcom_geni_serial_setup_tx(uport, 1);
392 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
393 M_TX_FIFO_WATERMARK_EN, true));
394 writel(c, uport->membase + SE_GENI_TX_FIFOn);
395 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
396 qcom_geni_serial_poll_tx_done(uport);
397 }
398 #endif
399
400 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
qcom_geni_serial_wr_char(struct uart_port * uport,int ch)401 static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
402 {
403 struct qcom_geni_private_data *private_data = uport->private_data;
404
405 private_data->write_cached_bytes =
406 (private_data->write_cached_bytes >> 8) | (ch << 24);
407 private_data->write_cached_bytes_cnt++;
408
409 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) {
410 writel(private_data->write_cached_bytes,
411 uport->membase + SE_GENI_TX_FIFOn);
412 private_data->write_cached_bytes_cnt = 0;
413 }
414 }
415
416 static void
__qcom_geni_serial_console_write(struct uart_port * uport,const char * s,unsigned int count)417 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
418 unsigned int count)
419 {
420 struct qcom_geni_private_data *private_data = uport->private_data;
421
422 int i;
423 u32 bytes_to_send = count;
424
425 for (i = 0; i < count; i++) {
426 /*
427 * uart_console_write() adds a carriage return for each newline.
428 * Account for additional bytes to be written.
429 */
430 if (s[i] == '\n')
431 bytes_to_send++;
432 }
433
434 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
435 qcom_geni_serial_setup_tx(uport, bytes_to_send);
436 for (i = 0; i < count; ) {
437 size_t chars_to_write = 0;
438 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
439
440 /*
441 * If the WM bit never set, then the Tx state machine is not
442 * in a valid state, so break, cancel/abort any existing
443 * command. Unfortunately the current data being written is
444 * lost.
445 */
446 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
447 M_TX_FIFO_WATERMARK_EN, true))
448 break;
449 chars_to_write = min_t(size_t, count - i, avail / 2);
450 uart_console_write(uport, s + i, chars_to_write,
451 qcom_geni_serial_wr_char);
452 writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
453 SE_GENI_M_IRQ_CLEAR);
454 i += chars_to_write;
455 }
456
457 if (private_data->write_cached_bytes_cnt) {
458 private_data->write_cached_bytes >>= BITS_PER_BYTE *
459 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt);
460 writel(private_data->write_cached_bytes,
461 uport->membase + SE_GENI_TX_FIFOn);
462 private_data->write_cached_bytes_cnt = 0;
463 }
464
465 qcom_geni_serial_poll_tx_done(uport);
466 }
467
qcom_geni_serial_console_write(struct console * co,const char * s,unsigned int count)468 static void qcom_geni_serial_console_write(struct console *co, const char *s,
469 unsigned int count)
470 {
471 struct uart_port *uport;
472 struct qcom_geni_serial_port *port;
473 bool locked = true;
474 unsigned long flags;
475 u32 geni_status;
476 u32 irq_en;
477
478 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
479
480 port = get_port_from_line(co->index, true);
481 if (IS_ERR(port))
482 return;
483
484 uport = &port->uport;
485 if (oops_in_progress)
486 locked = spin_trylock_irqsave(&uport->lock, flags);
487 else
488 spin_lock_irqsave(&uport->lock, flags);
489
490 geni_status = readl(uport->membase + SE_GENI_STATUS);
491
492 /* Cancel the current write to log the fault */
493 if (!locked) {
494 geni_se_cancel_m_cmd(&port->se);
495 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
496 M_CMD_CANCEL_EN, true)) {
497 geni_se_abort_m_cmd(&port->se);
498 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
499 M_CMD_ABORT_EN, true);
500 writel(M_CMD_ABORT_EN, uport->membase +
501 SE_GENI_M_IRQ_CLEAR);
502 }
503 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
504 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
505 /*
506 * It seems we can't interrupt existing transfers if all data
507 * has been sent, in which case we need to look for done first.
508 */
509 qcom_geni_serial_poll_tx_done(uport);
510
511 if (uart_circ_chars_pending(&uport->state->xmit)) {
512 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
513 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
514 uport->membase + SE_GENI_M_IRQ_EN);
515 }
516 }
517
518 __qcom_geni_serial_console_write(uport, s, count);
519
520 if (port->tx_remaining)
521 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
522
523 if (locked)
524 spin_unlock_irqrestore(&uport->lock, flags);
525 }
526
handle_rx_console(struct uart_port * uport,u32 bytes,bool drop)527 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
528 {
529 u32 i;
530 unsigned char buf[sizeof(u32)];
531 struct tty_port *tport;
532 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
533
534 tport = &uport->state->port;
535 for (i = 0; i < bytes; ) {
536 int c;
537 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD);
538
539 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
540 i += chunk;
541 if (drop)
542 continue;
543
544 for (c = 0; c < chunk; c++) {
545 int sysrq;
546
547 uport->icount.rx++;
548 if (port->brk && buf[c] == 0) {
549 port->brk = false;
550 if (uart_handle_break(uport))
551 continue;
552 }
553
554 sysrq = uart_prepare_sysrq_char(uport, buf[c]);
555
556 if (!sysrq)
557 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
558 }
559 }
560 if (!drop)
561 tty_flip_buffer_push(tport);
562 return 0;
563 }
564 #else
handle_rx_console(struct uart_port * uport,u32 bytes,bool drop)565 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
566 {
567 return -EPERM;
568 }
569
570 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
571
handle_rx_uart(struct uart_port * uport,u32 bytes,bool drop)572 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
573 {
574 struct tty_port *tport;
575 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
576 u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
577 u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
578 int ret;
579
580 tport = &uport->state->port;
581 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
582 if (drop)
583 return 0;
584
585 ret = tty_insert_flip_string(tport, port->rx_fifo, bytes);
586 if (ret != bytes) {
587 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
588 __func__, ret, bytes);
589 WARN_ON_ONCE(1);
590 }
591 uport->icount.rx += ret;
592 tty_flip_buffer_push(tport);
593 return ret;
594 }
595
qcom_geni_serial_start_tx(struct uart_port * uport)596 static void qcom_geni_serial_start_tx(struct uart_port *uport)
597 {
598 u32 irq_en;
599 u32 status;
600
601 status = readl(uport->membase + SE_GENI_STATUS);
602 if (status & M_GENI_CMD_ACTIVE)
603 return;
604
605 if (!qcom_geni_serial_tx_empty(uport))
606 return;
607
608 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
609 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
610
611 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
612 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
613 }
614
qcom_geni_serial_stop_tx(struct uart_port * uport)615 static void qcom_geni_serial_stop_tx(struct uart_port *uport)
616 {
617 u32 irq_en;
618 u32 status;
619 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
620
621 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
622 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
623 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
624 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
625 status = readl(uport->membase + SE_GENI_STATUS);
626 /* Possible stop tx is called multiple times. */
627 if (!(status & M_GENI_CMD_ACTIVE))
628 return;
629
630 geni_se_cancel_m_cmd(&port->se);
631 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
632 M_CMD_CANCEL_EN, true)) {
633 geni_se_abort_m_cmd(&port->se);
634 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
635 M_CMD_ABORT_EN, true);
636 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
637 }
638 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
639 }
640
qcom_geni_serial_start_rx(struct uart_port * uport)641 static void qcom_geni_serial_start_rx(struct uart_port *uport)
642 {
643 u32 irq_en;
644 u32 status;
645 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
646
647 status = readl(uport->membase + SE_GENI_STATUS);
648 if (status & S_GENI_CMD_ACTIVE)
649 qcom_geni_serial_stop_rx(uport);
650
651 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
652
653 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
654 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
655 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
656
657 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
658 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
659 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
660 }
661
qcom_geni_serial_stop_rx(struct uart_port * uport)662 static void qcom_geni_serial_stop_rx(struct uart_port *uport)
663 {
664 u32 irq_en;
665 u32 status;
666 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
667 u32 s_irq_status;
668
669 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
670 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
671 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
672
673 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
674 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
675 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
676
677 status = readl(uport->membase + SE_GENI_STATUS);
678 /* Possible stop rx is called multiple times. */
679 if (!(status & S_GENI_CMD_ACTIVE))
680 return;
681
682 geni_se_cancel_s_cmd(&port->se);
683 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
684 S_CMD_CANCEL_EN, true);
685 /*
686 * If timeout occurs secondary engine remains active
687 * and Abort sequence is executed.
688 */
689 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
690 /* Flush the Rx buffer */
691 if (s_irq_status & S_RX_FIFO_LAST_EN)
692 qcom_geni_serial_handle_rx(uport, true);
693 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
694
695 status = readl(uport->membase + SE_GENI_STATUS);
696 if (status & S_GENI_CMD_ACTIVE)
697 qcom_geni_serial_abort_rx(uport);
698 }
699
qcom_geni_serial_handle_rx(struct uart_port * uport,bool drop)700 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
701 {
702 u32 status;
703 u32 word_cnt;
704 u32 last_word_byte_cnt;
705 u32 last_word_partial;
706 u32 total_bytes;
707 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
708
709 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
710 word_cnt = status & RX_FIFO_WC_MSK;
711 last_word_partial = status & RX_LAST;
712 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
713 RX_LAST_BYTE_VALID_SHFT;
714
715 if (!word_cnt)
716 return;
717 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1);
718 if (last_word_partial && last_word_byte_cnt)
719 total_bytes += last_word_byte_cnt;
720 else
721 total_bytes += BYTES_PER_FIFO_WORD;
722 port->handle_rx(uport, total_bytes, drop);
723 }
724
qcom_geni_serial_handle_tx(struct uart_port * uport,bool done,bool active)725 static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
726 bool active)
727 {
728 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
729 struct circ_buf *xmit = &uport->state->xmit;
730 size_t avail;
731 size_t remaining;
732 size_t pending;
733 int i;
734 u32 status;
735 u32 irq_en;
736 unsigned int chunk;
737 int tail;
738
739 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
740
741 /* Complete the current tx command before taking newly added data */
742 if (active)
743 pending = port->tx_remaining;
744 else
745 pending = uart_circ_chars_pending(xmit);
746
747 /* All data has been transmitted and acknowledged as received */
748 if (!pending && !status && done) {
749 qcom_geni_serial_stop_tx(uport);
750 goto out_write_wakeup;
751 }
752
753 avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
754 avail *= BYTES_PER_FIFO_WORD;
755
756 tail = xmit->tail;
757 chunk = min(avail, pending);
758 if (!chunk)
759 goto out_write_wakeup;
760
761 if (!port->tx_remaining) {
762 qcom_geni_serial_setup_tx(uport, pending);
763 port->tx_remaining = pending;
764
765 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
766 if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
767 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
768 uport->membase + SE_GENI_M_IRQ_EN);
769 }
770
771 remaining = chunk;
772 for (i = 0; i < chunk; ) {
773 unsigned int tx_bytes;
774 u8 buf[sizeof(u32)];
775 int c;
776
777 memset(buf, 0, sizeof(buf));
778 tx_bytes = min_t(size_t, remaining, BYTES_PER_FIFO_WORD);
779
780 for (c = 0; c < tx_bytes ; c++) {
781 buf[c] = xmit->buf[tail++];
782 tail &= UART_XMIT_SIZE - 1;
783 }
784
785 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
786
787 i += tx_bytes;
788 uport->icount.tx += tx_bytes;
789 remaining -= tx_bytes;
790 port->tx_remaining -= tx_bytes;
791 }
792
793 xmit->tail = tail;
794
795 /*
796 * The tx fifo watermark is level triggered and latched. Though we had
797 * cleared it in qcom_geni_serial_isr it will have already reasserted
798 * so we must clear it again here after our writes.
799 */
800 writel(M_TX_FIFO_WATERMARK_EN,
801 uport->membase + SE_GENI_M_IRQ_CLEAR);
802
803 out_write_wakeup:
804 if (!port->tx_remaining) {
805 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
806 if (irq_en & M_TX_FIFO_WATERMARK_EN)
807 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
808 uport->membase + SE_GENI_M_IRQ_EN);
809 }
810
811 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
812 uart_write_wakeup(uport);
813 }
814
qcom_geni_serial_isr(int isr,void * dev)815 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
816 {
817 u32 m_irq_en;
818 u32 m_irq_status;
819 u32 s_irq_status;
820 u32 geni_status;
821 struct uart_port *uport = dev;
822 unsigned long flags;
823 bool drop_rx = false;
824 struct tty_port *tport = &uport->state->port;
825 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
826
827 if (uport->suspended)
828 return IRQ_NONE;
829
830 spin_lock_irqsave(&uport->lock, flags);
831 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
832 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
833 geni_status = readl(uport->membase + SE_GENI_STATUS);
834 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
835 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
836 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
837
838 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
839 goto out_unlock;
840
841 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
842 uport->icount.overrun++;
843 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
844 }
845
846 if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
847 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
848 geni_status & M_GENI_CMD_ACTIVE);
849
850 if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
851 if (s_irq_status & S_GP_IRQ_0_EN)
852 uport->icount.parity++;
853 drop_rx = true;
854 } else if (s_irq_status & S_GP_IRQ_2_EN ||
855 s_irq_status & S_GP_IRQ_3_EN) {
856 uport->icount.brk++;
857 port->brk = true;
858 }
859
860 if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
861 s_irq_status & S_RX_FIFO_LAST_EN)
862 qcom_geni_serial_handle_rx(uport, drop_rx);
863
864 out_unlock:
865 uart_unlock_and_check_sysrq(uport, flags);
866
867 return IRQ_HANDLED;
868 }
869
setup_fifos(struct qcom_geni_serial_port * port)870 static int setup_fifos(struct qcom_geni_serial_port *port)
871 {
872 struct uart_port *uport;
873 u32 old_rx_fifo_depth = port->rx_fifo_depth;
874
875 uport = &port->uport;
876 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
877 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
878 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
879 uport->fifosize =
880 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
881
882 if (port->rx_fifo && (old_rx_fifo_depth != port->rx_fifo_depth) && port->rx_fifo_depth) {
883 port->rx_fifo = devm_krealloc(uport->dev, port->rx_fifo,
884 port->rx_fifo_depth * sizeof(u32),
885 GFP_KERNEL);
886 if (!port->rx_fifo)
887 return -ENOMEM;
888 }
889
890 return 0;
891 }
892
893
qcom_geni_serial_shutdown(struct uart_port * uport)894 static void qcom_geni_serial_shutdown(struct uart_port *uport)
895 {
896 disable_irq(uport->irq);
897 }
898
qcom_geni_serial_port_setup(struct uart_port * uport)899 static int qcom_geni_serial_port_setup(struct uart_port *uport)
900 {
901 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
902 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
903 u32 proto;
904 u32 pin_swap;
905 int ret;
906
907 proto = geni_se_read_proto(&port->se);
908 if (proto != GENI_SE_UART) {
909 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
910 return -ENXIO;
911 }
912
913 qcom_geni_serial_stop_rx(uport);
914
915 ret = setup_fifos(port);
916 if (ret)
917 return ret;
918
919 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
920
921 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL);
922 if (port->rx_tx_swap) {
923 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK;
924 pin_swap |= IO_MACRO_IO2_IO3_SWAP;
925 }
926 if (port->cts_rts_swap) {
927 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK;
928 pin_swap |= IO_MACRO_IO0_SEL;
929 }
930 /* Configure this register if RX-TX, CTS-RTS pins are swapped */
931 if (port->rx_tx_swap || port->cts_rts_swap)
932 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL);
933
934 /*
935 * Make an unconditional cancel on the main sequencer to reset
936 * it else we could end up in data loss scenarios.
937 */
938 if (uart_console(uport))
939 qcom_geni_serial_poll_tx_done(uport);
940 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
941 false, true, true);
942 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
943 geni_se_select_mode(&port->se, GENI_SE_FIFO);
944 port->setup = true;
945
946 return 0;
947 }
948
qcom_geni_serial_startup(struct uart_port * uport)949 static int qcom_geni_serial_startup(struct uart_port *uport)
950 {
951 int ret;
952 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
953
954 if (!port->setup) {
955 ret = qcom_geni_serial_port_setup(uport);
956 if (ret)
957 return ret;
958 }
959 enable_irq(uport->irq);
960
961 return 0;
962 }
963
get_clk_cfg(unsigned long clk_freq)964 static unsigned long get_clk_cfg(unsigned long clk_freq)
965 {
966 int i;
967
968 for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
969 if (!(root_freq[i] % clk_freq))
970 return root_freq[i];
971 }
972 return 0;
973 }
974
get_clk_div_rate(unsigned int baud,unsigned int sampling_rate,unsigned int * clk_div)975 static unsigned long get_clk_div_rate(unsigned int baud,
976 unsigned int sampling_rate, unsigned int *clk_div)
977 {
978 unsigned long ser_clk;
979 unsigned long desired_clk;
980
981 desired_clk = baud * sampling_rate;
982 ser_clk = get_clk_cfg(desired_clk);
983 if (!ser_clk) {
984 pr_err("%s: Can't find matching DFS entry for baud %d\n",
985 __func__, baud);
986 return ser_clk;
987 }
988
989 *clk_div = ser_clk / desired_clk;
990 return ser_clk;
991 }
992
qcom_geni_serial_set_termios(struct uart_port * uport,struct ktermios * termios,struct ktermios * old)993 static void qcom_geni_serial_set_termios(struct uart_port *uport,
994 struct ktermios *termios, struct ktermios *old)
995 {
996 unsigned int baud;
997 u32 bits_per_char;
998 u32 tx_trans_cfg;
999 u32 tx_parity_cfg;
1000 u32 rx_trans_cfg;
1001 u32 rx_parity_cfg;
1002 u32 stop_bit_len;
1003 unsigned int clk_div;
1004 u32 ser_clk_cfg;
1005 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1006 unsigned long clk_rate;
1007 u32 ver, sampling_rate;
1008 unsigned int avg_bw_core;
1009
1010 qcom_geni_serial_stop_rx(uport);
1011 /* baud rate */
1012 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
1013 port->baud = baud;
1014
1015 sampling_rate = UART_OVERSAMPLING;
1016 /* Sampling rate is halved for IP versions >= 2.5 */
1017 ver = geni_se_get_qup_hw_version(&port->se);
1018 if (ver >= QUP_SE_VERSION_2_5)
1019 sampling_rate /= 2;
1020
1021 clk_rate = get_clk_div_rate(baud, sampling_rate, &clk_div);
1022 if (!clk_rate)
1023 goto out_restart_rx;
1024
1025 uport->uartclk = clk_rate;
1026 port->clk_rate = clk_rate;
1027 dev_pm_opp_set_rate(uport->dev, clk_rate);
1028 ser_clk_cfg = SER_CLK_EN;
1029 ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
1030
1031 /*
1032 * Bump up BW vote on CPU and CORE path as driver supports FIFO mode
1033 * only.
1034 */
1035 avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ)
1036 : GENI_DEFAULT_BW;
1037 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;
1038 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);
1039 geni_icc_set_bw(&port->se);
1040
1041 /* parity */
1042 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
1043 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
1044 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
1045 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
1046 if (termios->c_cflag & PARENB) {
1047 tx_trans_cfg |= UART_TX_PAR_EN;
1048 rx_trans_cfg |= UART_RX_PAR_EN;
1049 tx_parity_cfg |= PAR_CALC_EN;
1050 rx_parity_cfg |= PAR_CALC_EN;
1051 if (termios->c_cflag & PARODD) {
1052 tx_parity_cfg |= PAR_ODD;
1053 rx_parity_cfg |= PAR_ODD;
1054 } else if (termios->c_cflag & CMSPAR) {
1055 tx_parity_cfg |= PAR_SPACE;
1056 rx_parity_cfg |= PAR_SPACE;
1057 } else {
1058 tx_parity_cfg |= PAR_EVEN;
1059 rx_parity_cfg |= PAR_EVEN;
1060 }
1061 } else {
1062 tx_trans_cfg &= ~UART_TX_PAR_EN;
1063 rx_trans_cfg &= ~UART_RX_PAR_EN;
1064 tx_parity_cfg &= ~PAR_CALC_EN;
1065 rx_parity_cfg &= ~PAR_CALC_EN;
1066 }
1067
1068 /* bits per char */
1069 switch (termios->c_cflag & CSIZE) {
1070 case CS5:
1071 bits_per_char = 5;
1072 break;
1073 case CS6:
1074 bits_per_char = 6;
1075 break;
1076 case CS7:
1077 bits_per_char = 7;
1078 break;
1079 case CS8:
1080 default:
1081 bits_per_char = 8;
1082 break;
1083 }
1084
1085 /* stop bits */
1086 if (termios->c_cflag & CSTOPB)
1087 stop_bit_len = TX_STOP_BIT_LEN_2;
1088 else
1089 stop_bit_len = TX_STOP_BIT_LEN_1;
1090
1091 /* flow control, clear the CTS_MASK bit if using flow control. */
1092 if (termios->c_cflag & CRTSCTS)
1093 tx_trans_cfg &= ~UART_CTS_MASK;
1094 else
1095 tx_trans_cfg |= UART_CTS_MASK;
1096
1097 if (baud)
1098 uart_update_timeout(uport, termios->c_cflag, baud);
1099
1100 if (!uart_console(uport))
1101 writel(port->loopback,
1102 uport->membase + SE_UART_LOOPBACK_CFG);
1103 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1104 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1105 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1106 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1107 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1108 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1109 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1110 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1111 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1112 out_restart_rx:
1113 qcom_geni_serial_start_rx(uport);
1114 }
1115
qcom_geni_serial_tx_empty(struct uart_port * uport)1116 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1117 {
1118 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1119 }
1120
1121 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
qcom_geni_console_setup(struct console * co,char * options)1122 static int qcom_geni_console_setup(struct console *co, char *options)
1123 {
1124 struct uart_port *uport;
1125 struct qcom_geni_serial_port *port;
1126 int baud = 115200;
1127 int bits = 8;
1128 int parity = 'n';
1129 int flow = 'n';
1130 int ret;
1131
1132 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0)
1133 return -ENXIO;
1134
1135 port = get_port_from_line(co->index, true);
1136 if (IS_ERR(port)) {
1137 pr_err("Invalid line %d\n", co->index);
1138 return PTR_ERR(port);
1139 }
1140
1141 uport = &port->uport;
1142
1143 if (unlikely(!uport->membase))
1144 return -ENXIO;
1145
1146 if (!port->setup) {
1147 ret = qcom_geni_serial_port_setup(uport);
1148 if (ret)
1149 return ret;
1150 }
1151
1152 if (options)
1153 uart_parse_options(options, &baud, &parity, &bits, &flow);
1154
1155 return uart_set_options(uport, co, baud, parity, bits, flow);
1156 }
1157
qcom_geni_serial_earlycon_write(struct console * con,const char * s,unsigned int n)1158 static void qcom_geni_serial_earlycon_write(struct console *con,
1159 const char *s, unsigned int n)
1160 {
1161 struct earlycon_device *dev = con->data;
1162
1163 __qcom_geni_serial_console_write(&dev->port, s, n);
1164 }
1165
1166 #ifdef CONFIG_CONSOLE_POLL
qcom_geni_serial_earlycon_read(struct console * con,char * s,unsigned int n)1167 static int qcom_geni_serial_earlycon_read(struct console *con,
1168 char *s, unsigned int n)
1169 {
1170 struct earlycon_device *dev = con->data;
1171 struct uart_port *uport = &dev->port;
1172 int num_read = 0;
1173 int ch;
1174
1175 while (num_read < n) {
1176 ch = qcom_geni_serial_get_char(uport);
1177 if (ch == NO_POLL_CHAR)
1178 break;
1179 s[num_read++] = ch;
1180 }
1181
1182 return num_read;
1183 }
1184
qcom_geni_serial_enable_early_read(struct geni_se * se,struct console * con)1185 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se,
1186 struct console *con)
1187 {
1188 geni_se_setup_s_cmd(se, UART_START_READ, 0);
1189 con->read = qcom_geni_serial_earlycon_read;
1190 }
1191 #else
qcom_geni_serial_enable_early_read(struct geni_se * se,struct console * con)1192 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se,
1193 struct console *con) { }
1194 #endif
1195
1196 static struct qcom_geni_private_data earlycon_private_data;
1197
qcom_geni_serial_earlycon_setup(struct earlycon_device * dev,const char * opt)1198 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1199 const char *opt)
1200 {
1201 struct uart_port *uport = &dev->port;
1202 u32 tx_trans_cfg;
1203 u32 tx_parity_cfg = 0; /* Disable Tx Parity */
1204 u32 rx_trans_cfg = 0;
1205 u32 rx_parity_cfg = 0; /* Disable Rx Parity */
1206 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */
1207 u32 bits_per_char;
1208 struct geni_se se;
1209
1210 if (!uport->membase)
1211 return -EINVAL;
1212
1213 uport->private_data = &earlycon_private_data;
1214
1215 memset(&se, 0, sizeof(se));
1216 se.base = uport->membase;
1217 if (geni_se_read_proto(&se) != GENI_SE_UART)
1218 return -ENXIO;
1219 /*
1220 * Ignore Flow control.
1221 * n = 8.
1222 */
1223 tx_trans_cfg = UART_CTS_MASK;
1224 bits_per_char = BITS_PER_BYTE;
1225
1226 /*
1227 * Make an unconditional cancel on the main sequencer to reset
1228 * it else we could end up in data loss scenarios.
1229 */
1230 qcom_geni_serial_poll_tx_done(uport);
1231 qcom_geni_serial_abort_rx(uport);
1232 geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
1233 false, true, true);
1234 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1235 geni_se_select_mode(&se, GENI_SE_FIFO);
1236
1237 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1238 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1239 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1240 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1241 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1242 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1243 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1244
1245 dev->con->write = qcom_geni_serial_earlycon_write;
1246 dev->con->setup = NULL;
1247 qcom_geni_serial_enable_early_read(&se, dev->con);
1248
1249 return 0;
1250 }
1251 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1252 qcom_geni_serial_earlycon_setup);
1253
console_register(struct uart_driver * drv)1254 static int __init console_register(struct uart_driver *drv)
1255 {
1256 return uart_register_driver(drv);
1257 }
1258
console_unregister(struct uart_driver * drv)1259 static void console_unregister(struct uart_driver *drv)
1260 {
1261 uart_unregister_driver(drv);
1262 }
1263
1264 static struct console cons_ops = {
1265 .name = "ttyMSM",
1266 .write = qcom_geni_serial_console_write,
1267 .device = uart_console_device,
1268 .setup = qcom_geni_console_setup,
1269 .flags = CON_PRINTBUFFER,
1270 .index = -1,
1271 .data = &qcom_geni_console_driver,
1272 };
1273
1274 static struct uart_driver qcom_geni_console_driver = {
1275 .owner = THIS_MODULE,
1276 .driver_name = "qcom_geni_console",
1277 .dev_name = "ttyMSM",
1278 .nr = GENI_UART_CONS_PORTS,
1279 .cons = &cons_ops,
1280 };
1281 #else
console_register(struct uart_driver * drv)1282 static int console_register(struct uart_driver *drv)
1283 {
1284 return 0;
1285 }
1286
console_unregister(struct uart_driver * drv)1287 static void console_unregister(struct uart_driver *drv)
1288 {
1289 }
1290 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1291
1292 static struct uart_driver qcom_geni_uart_driver = {
1293 .owner = THIS_MODULE,
1294 .driver_name = "qcom_geni_uart",
1295 .dev_name = "ttyHS",
1296 .nr = GENI_UART_PORTS,
1297 };
1298
qcom_geni_serial_pm(struct uart_port * uport,unsigned int new_state,unsigned int old_state)1299 static void qcom_geni_serial_pm(struct uart_port *uport,
1300 unsigned int new_state, unsigned int old_state)
1301 {
1302 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1303
1304 /* If we've never been called, treat it as off */
1305 if (old_state == UART_PM_STATE_UNDEFINED)
1306 old_state = UART_PM_STATE_OFF;
1307
1308 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
1309 geni_icc_enable(&port->se);
1310 if (port->clk_rate)
1311 dev_pm_opp_set_rate(uport->dev, port->clk_rate);
1312 geni_se_resources_on(&port->se);
1313 } else if (new_state == UART_PM_STATE_OFF &&
1314 old_state == UART_PM_STATE_ON) {
1315 geni_se_resources_off(&port->se);
1316 dev_pm_opp_set_rate(uport->dev, 0);
1317 geni_icc_disable(&port->se);
1318 }
1319 }
1320
1321 static const struct uart_ops qcom_geni_console_pops = {
1322 .tx_empty = qcom_geni_serial_tx_empty,
1323 .stop_tx = qcom_geni_serial_stop_tx,
1324 .start_tx = qcom_geni_serial_start_tx,
1325 .stop_rx = qcom_geni_serial_stop_rx,
1326 .set_termios = qcom_geni_serial_set_termios,
1327 .startup = qcom_geni_serial_startup,
1328 .request_port = qcom_geni_serial_request_port,
1329 .config_port = qcom_geni_serial_config_port,
1330 .shutdown = qcom_geni_serial_shutdown,
1331 .type = qcom_geni_serial_get_type,
1332 .set_mctrl = qcom_geni_serial_set_mctrl,
1333 .get_mctrl = qcom_geni_serial_get_mctrl,
1334 #ifdef CONFIG_CONSOLE_POLL
1335 .poll_get_char = qcom_geni_serial_get_char,
1336 .poll_put_char = qcom_geni_serial_poll_put_char,
1337 #endif
1338 .pm = qcom_geni_serial_pm,
1339 };
1340
1341 static const struct uart_ops qcom_geni_uart_pops = {
1342 .tx_empty = qcom_geni_serial_tx_empty,
1343 .stop_tx = qcom_geni_serial_stop_tx,
1344 .start_tx = qcom_geni_serial_start_tx,
1345 .stop_rx = qcom_geni_serial_stop_rx,
1346 .set_termios = qcom_geni_serial_set_termios,
1347 .startup = qcom_geni_serial_startup,
1348 .request_port = qcom_geni_serial_request_port,
1349 .config_port = qcom_geni_serial_config_port,
1350 .shutdown = qcom_geni_serial_shutdown,
1351 .type = qcom_geni_serial_get_type,
1352 .set_mctrl = qcom_geni_serial_set_mctrl,
1353 .get_mctrl = qcom_geni_serial_get_mctrl,
1354 .pm = qcom_geni_serial_pm,
1355 };
1356
qcom_geni_serial_probe(struct platform_device * pdev)1357 static int qcom_geni_serial_probe(struct platform_device *pdev)
1358 {
1359 int ret = 0;
1360 int line = -1;
1361 struct qcom_geni_serial_port *port;
1362 struct uart_port *uport;
1363 struct resource *res;
1364 int irq;
1365 bool console = false;
1366 struct uart_driver *drv;
1367
1368 if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1369 console = true;
1370
1371 if (console) {
1372 drv = &qcom_geni_console_driver;
1373 line = of_alias_get_id(pdev->dev.of_node, "serial");
1374 } else {
1375 drv = &qcom_geni_uart_driver;
1376 line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1377 }
1378
1379 port = get_port_from_line(line, console);
1380 if (IS_ERR(port)) {
1381 dev_err(&pdev->dev, "Invalid line %d\n", line);
1382 return PTR_ERR(port);
1383 }
1384
1385 uport = &port->uport;
1386 /* Don't allow 2 drivers to access the same port */
1387 if (uport->private_data)
1388 return -ENODEV;
1389
1390 uport->dev = &pdev->dev;
1391 port->se.dev = &pdev->dev;
1392 port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1393 port->se.clk = devm_clk_get(&pdev->dev, "se");
1394 if (IS_ERR(port->se.clk)) {
1395 ret = PTR_ERR(port->se.clk);
1396 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1397 return ret;
1398 }
1399
1400 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1401 if (!res)
1402 return -EINVAL;
1403 uport->mapbase = res->start;
1404
1405 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1406 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1407 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1408
1409 if (!console) {
1410 port->rx_fifo = devm_kcalloc(uport->dev,
1411 port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
1412 if (!port->rx_fifo)
1413 return -ENOMEM;
1414 }
1415
1416 ret = geni_icc_get(&port->se, NULL);
1417 if (ret)
1418 return ret;
1419 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
1420 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1421
1422 /* Set BW for register access */
1423 ret = geni_icc_set_bw(&port->se);
1424 if (ret)
1425 return ret;
1426
1427 port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
1428 "qcom_geni_serial_%s%d",
1429 uart_console(uport) ? "console" : "uart", uport->line);
1430 if (!port->name)
1431 return -ENOMEM;
1432
1433 irq = platform_get_irq(pdev, 0);
1434 if (irq < 0)
1435 return irq;
1436 uport->irq = irq;
1437 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
1438
1439 if (!console)
1440 port->wakeup_irq = platform_get_irq_optional(pdev, 1);
1441
1442 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"))
1443 port->rx_tx_swap = true;
1444
1445 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))
1446 port->cts_rts_swap = true;
1447
1448 port->se.opp_table = dev_pm_opp_set_clkname(&pdev->dev, "se");
1449 if (IS_ERR(port->se.opp_table))
1450 return PTR_ERR(port->se.opp_table);
1451 /* OPP table is optional */
1452 ret = dev_pm_opp_of_add_table(&pdev->dev);
1453 if (ret && ret != -ENODEV) {
1454 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1455 goto put_clkname;
1456 }
1457
1458 port->private_data.drv = drv;
1459 uport->private_data = &port->private_data;
1460 platform_set_drvdata(pdev, port);
1461 port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1462
1463 ret = uart_add_one_port(drv, uport);
1464 if (ret)
1465 goto err;
1466
1467 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
1468 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
1469 IRQF_TRIGGER_HIGH, port->name, uport);
1470 if (ret) {
1471 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
1472 uart_remove_one_port(drv, uport);
1473 goto err;
1474 }
1475
1476 if (port->wakeup_irq > 0) {
1477 device_init_wakeup(&pdev->dev, true);
1478 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1479 port->wakeup_irq);
1480 if (ret) {
1481 device_init_wakeup(&pdev->dev, false);
1482 uart_remove_one_port(drv, uport);
1483 goto err;
1484 }
1485 }
1486
1487 return 0;
1488 err:
1489 dev_pm_opp_of_remove_table(&pdev->dev);
1490 put_clkname:
1491 dev_pm_opp_put_clkname(port->se.opp_table);
1492 return ret;
1493 }
1494
qcom_geni_serial_remove(struct platform_device * pdev)1495 static int qcom_geni_serial_remove(struct platform_device *pdev)
1496 {
1497 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1498 struct uart_driver *drv = port->private_data.drv;
1499
1500 dev_pm_opp_of_remove_table(&pdev->dev);
1501 dev_pm_opp_put_clkname(port->se.opp_table);
1502 dev_pm_clear_wake_irq(&pdev->dev);
1503 device_init_wakeup(&pdev->dev, false);
1504 uart_remove_one_port(drv, &port->uport);
1505
1506 return 0;
1507 }
1508
qcom_geni_serial_sys_suspend(struct device * dev)1509 static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev)
1510 {
1511 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1512 struct uart_port *uport = &port->uport;
1513 struct qcom_geni_private_data *private_data = uport->private_data;
1514
1515 /*
1516 * This is done so we can hit the lowest possible state in suspend
1517 * even with no_console_suspend
1518 */
1519 if (uart_console(uport)) {
1520 geni_icc_set_tag(&port->se, 0x3);
1521 geni_icc_set_bw(&port->se);
1522 }
1523 return uart_suspend_port(private_data->drv, uport);
1524 }
1525
qcom_geni_serial_sys_resume(struct device * dev)1526 static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
1527 {
1528 int ret;
1529 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1530 struct uart_port *uport = &port->uport;
1531 struct qcom_geni_private_data *private_data = uport->private_data;
1532
1533 ret = uart_resume_port(private_data->drv, uport);
1534 if (uart_console(uport)) {
1535 geni_icc_set_tag(&port->se, 0x7);
1536 geni_icc_set_bw(&port->se);
1537 }
1538 return ret;
1539 }
1540
1541 static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1542 SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend,
1543 qcom_geni_serial_sys_resume)
1544 };
1545
1546 static const struct of_device_id qcom_geni_serial_match_table[] = {
1547 { .compatible = "qcom,geni-debug-uart", },
1548 { .compatible = "qcom,geni-uart", },
1549 {}
1550 };
1551 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1552
1553 static struct platform_driver qcom_geni_serial_platform_driver = {
1554 .remove = qcom_geni_serial_remove,
1555 .probe = qcom_geni_serial_probe,
1556 .driver = {
1557 .name = "qcom_geni_serial",
1558 .of_match_table = qcom_geni_serial_match_table,
1559 .pm = &qcom_geni_serial_pm_ops,
1560 },
1561 };
1562
qcom_geni_serial_init(void)1563 static int __init qcom_geni_serial_init(void)
1564 {
1565 int ret;
1566
1567 ret = console_register(&qcom_geni_console_driver);
1568 if (ret)
1569 return ret;
1570
1571 ret = uart_register_driver(&qcom_geni_uart_driver);
1572 if (ret) {
1573 console_unregister(&qcom_geni_console_driver);
1574 return ret;
1575 }
1576
1577 ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1578 if (ret) {
1579 console_unregister(&qcom_geni_console_driver);
1580 uart_unregister_driver(&qcom_geni_uart_driver);
1581 }
1582 return ret;
1583 }
1584 module_init(qcom_geni_serial_init);
1585
qcom_geni_serial_exit(void)1586 static void __exit qcom_geni_serial_exit(void)
1587 {
1588 platform_driver_unregister(&qcom_geni_serial_platform_driver);
1589 console_unregister(&qcom_geni_console_driver);
1590 uart_unregister_driver(&qcom_geni_uart_driver);
1591 }
1592 module_exit(qcom_geni_serial_exit);
1593
1594 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1595 MODULE_LICENSE("GPL v2");
1596