1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver core for Samsung SoC onboard UARTs.
4 *
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
6 * http://armlinux.simtec.co.uk/
7 */
8
9 /* Note on 2410 error handling
10 *
11 * The s3c2410 manual has a love/hate affair with the contents of the
12 * UERSTAT register in the UART blocks, and keeps marking some of the
13 * error bits as reserved. Having checked with the s3c2410x01,
14 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
15 * feature from the latter versions of the manual.
16 *
17 * If it becomes aparrent that latter versions of the 2410 remove these
18 * bits, then action will have to be taken to differentiate the versions
19 * and change the policy on BREAK
20 *
21 * BJD, 04-Nov-2004
22 */
23
24 #include <linux/dmaengine.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/slab.h>
27 #include <linux/module.h>
28 #include <linux/ioport.h>
29 #include <linux/io.h>
30 #include <linux/platform_device.h>
31 #include <linux/init.h>
32 #include <linux/sysrq.h>
33 #include <linux/console.h>
34 #include <linux/tty.h>
35 #include <linux/tty_flip.h>
36 #include <linux/serial_core.h>
37 #include <linux/serial.h>
38 #include <linux/serial_s3c.h>
39 #include <linux/delay.h>
40 #include <linux/clk.h>
41 #include <linux/cpufreq.h>
42 #include <linux/of.h>
43 #include <asm/irq.h>
44
45 /* UART name and device definitions */
46
47 #define S3C24XX_SERIAL_NAME "ttySAC"
48 #define S3C24XX_SERIAL_MAJOR 204
49 #define S3C24XX_SERIAL_MINOR 64
50
51 #define S3C24XX_TX_PIO 1
52 #define S3C24XX_TX_DMA 2
53 #define S3C24XX_RX_PIO 1
54 #define S3C24XX_RX_DMA 2
55
56 /* flag to ignore all characters coming in */
57 #define RXSTAT_DUMMY_READ (0x10000000)
58
59 struct s3c24xx_uart_info {
60 char *name;
61 unsigned int type;
62 unsigned int fifosize;
63 unsigned long rx_fifomask;
64 unsigned long rx_fifoshift;
65 unsigned long rx_fifofull;
66 unsigned long tx_fifomask;
67 unsigned long tx_fifoshift;
68 unsigned long tx_fifofull;
69 unsigned int def_clk_sel;
70 unsigned long num_clks;
71 unsigned long clksel_mask;
72 unsigned long clksel_shift;
73
74 /* uart port features */
75
76 unsigned int has_divslot:1;
77 };
78
79 struct s3c24xx_serial_drv_data {
80 struct s3c24xx_uart_info *info;
81 struct s3c2410_uartcfg *def_cfg;
82 unsigned int fifosize[CONFIG_SERIAL_SAMSUNG_UARTS];
83 };
84
85 struct s3c24xx_uart_dma {
86 unsigned int rx_chan_id;
87 unsigned int tx_chan_id;
88
89 struct dma_slave_config rx_conf;
90 struct dma_slave_config tx_conf;
91
92 struct dma_chan *rx_chan;
93 struct dma_chan *tx_chan;
94
95 dma_addr_t rx_addr;
96 dma_addr_t tx_addr;
97
98 dma_cookie_t rx_cookie;
99 dma_cookie_t tx_cookie;
100
101 char *rx_buf;
102
103 dma_addr_t tx_transfer_addr;
104
105 size_t rx_size;
106 size_t tx_size;
107
108 struct dma_async_tx_descriptor *tx_desc;
109 struct dma_async_tx_descriptor *rx_desc;
110
111 int tx_bytes_requested;
112 int rx_bytes_requested;
113 };
114
115 struct s3c24xx_uart_port {
116 unsigned char rx_claimed;
117 unsigned char tx_claimed;
118 unsigned char rx_enabled;
119 unsigned char tx_enabled;
120 unsigned int pm_level;
121 unsigned long baudclk_rate;
122 unsigned int min_dma_size;
123
124 unsigned int rx_irq;
125 unsigned int tx_irq;
126
127 unsigned int tx_in_progress;
128 unsigned int tx_mode;
129 unsigned int rx_mode;
130
131 struct s3c24xx_uart_info *info;
132 struct clk *clk;
133 struct clk *baudclk;
134 struct uart_port port;
135 struct s3c24xx_serial_drv_data *drv_data;
136
137 /* reference to platform data */
138 struct s3c2410_uartcfg *cfg;
139
140 struct s3c24xx_uart_dma *dma;
141
142 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
143 struct notifier_block freq_transition;
144 #endif
145 };
146
147 /* conversion functions */
148
149 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
150
151 /* register access controls */
152
153 #define portaddr(port, reg) ((port)->membase + (reg))
154 #define portaddrl(port, reg) \
155 ((unsigned long *)(unsigned long)((port)->membase + (reg)))
156
rd_reg(struct uart_port * port,u32 reg)157 static u32 rd_reg(struct uart_port *port, u32 reg)
158 {
159 switch (port->iotype) {
160 case UPIO_MEM:
161 return readb_relaxed(portaddr(port, reg));
162 case UPIO_MEM32:
163 return readl_relaxed(portaddr(port, reg));
164 default:
165 return 0;
166 }
167 return 0;
168 }
169
170 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
171
wr_reg(struct uart_port * port,u32 reg,u32 val)172 static void wr_reg(struct uart_port *port, u32 reg, u32 val)
173 {
174 switch (port->iotype) {
175 case UPIO_MEM:
176 writeb_relaxed(val, portaddr(port, reg));
177 break;
178 case UPIO_MEM32:
179 writel_relaxed(val, portaddr(port, reg));
180 break;
181 }
182 }
183
184 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
185
186 /* Byte-order aware bit setting/clearing functions. */
187
s3c24xx_set_bit(struct uart_port * port,int idx,unsigned int reg)188 static inline void s3c24xx_set_bit(struct uart_port *port, int idx,
189 unsigned int reg)
190 {
191 unsigned long flags;
192 u32 val;
193
194 local_irq_save(flags);
195 val = rd_regl(port, reg);
196 val |= (1 << idx);
197 wr_regl(port, reg, val);
198 local_irq_restore(flags);
199 }
200
s3c24xx_clear_bit(struct uart_port * port,int idx,unsigned int reg)201 static inline void s3c24xx_clear_bit(struct uart_port *port, int idx,
202 unsigned int reg)
203 {
204 unsigned long flags;
205 u32 val;
206
207 local_irq_save(flags);
208 val = rd_regl(port, reg);
209 val &= ~(1 << idx);
210 wr_regl(port, reg, val);
211 local_irq_restore(flags);
212 }
213
to_ourport(struct uart_port * port)214 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
215 {
216 return container_of(port, struct s3c24xx_uart_port, port);
217 }
218
219 /* translate a port to the device name */
220
s3c24xx_serial_portname(struct uart_port * port)221 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
222 {
223 return to_platform_device(port->dev)->name;
224 }
225
s3c24xx_serial_txempty_nofifo(struct uart_port * port)226 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
227 {
228 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
229 }
230
231 /*
232 * s3c64xx and later SoC's include the interrupt mask and status registers in
233 * the controller itself, unlike the s3c24xx SoC's which have these registers
234 * in the interrupt controller. Check if the port type is s3c64xx or higher.
235 */
s3c24xx_serial_has_interrupt_mask(struct uart_port * port)236 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
237 {
238 return to_ourport(port)->info->type == PORT_S3C6400;
239 }
240
s3c24xx_serial_rx_enable(struct uart_port * port)241 static void s3c24xx_serial_rx_enable(struct uart_port *port)
242 {
243 struct s3c24xx_uart_port *ourport = to_ourport(port);
244 unsigned long flags;
245 unsigned int ucon, ufcon;
246 int count = 10000;
247
248 spin_lock_irqsave(&port->lock, flags);
249
250 while (--count && !s3c24xx_serial_txempty_nofifo(port))
251 udelay(100);
252
253 ufcon = rd_regl(port, S3C2410_UFCON);
254 ufcon |= S3C2410_UFCON_RESETRX;
255 wr_regl(port, S3C2410_UFCON, ufcon);
256
257 ucon = rd_regl(port, S3C2410_UCON);
258 ucon |= S3C2410_UCON_RXIRQMODE;
259 wr_regl(port, S3C2410_UCON, ucon);
260
261 ourport->rx_enabled = 1;
262 spin_unlock_irqrestore(&port->lock, flags);
263 }
264
s3c24xx_serial_rx_disable(struct uart_port * port)265 static void s3c24xx_serial_rx_disable(struct uart_port *port)
266 {
267 struct s3c24xx_uart_port *ourport = to_ourport(port);
268 unsigned long flags;
269 unsigned int ucon;
270
271 spin_lock_irqsave(&port->lock, flags);
272
273 ucon = rd_regl(port, S3C2410_UCON);
274 ucon &= ~S3C2410_UCON_RXIRQMODE;
275 wr_regl(port, S3C2410_UCON, ucon);
276
277 ourport->rx_enabled = 0;
278 spin_unlock_irqrestore(&port->lock, flags);
279 }
280
s3c24xx_serial_stop_tx(struct uart_port * port)281 static void s3c24xx_serial_stop_tx(struct uart_port *port)
282 {
283 struct s3c24xx_uart_port *ourport = to_ourport(port);
284 struct s3c24xx_uart_dma *dma = ourport->dma;
285 struct circ_buf *xmit = &port->state->xmit;
286 struct dma_tx_state state;
287 int count;
288
289 if (!ourport->tx_enabled)
290 return;
291
292 if (s3c24xx_serial_has_interrupt_mask(port))
293 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
294 else
295 disable_irq_nosync(ourport->tx_irq);
296
297 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
298 dmaengine_pause(dma->tx_chan);
299 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
300 dmaengine_terminate_all(dma->tx_chan);
301 dma_sync_single_for_cpu(ourport->port.dev,
302 dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
303 async_tx_ack(dma->tx_desc);
304 count = dma->tx_bytes_requested - state.residue;
305 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
306 port->icount.tx += count;
307 }
308
309 ourport->tx_enabled = 0;
310 ourport->tx_in_progress = 0;
311
312 if (port->flags & UPF_CONS_FLOW)
313 s3c24xx_serial_rx_enable(port);
314
315 ourport->tx_mode = 0;
316 }
317
318 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
319
s3c24xx_serial_tx_dma_complete(void * args)320 static void s3c24xx_serial_tx_dma_complete(void *args)
321 {
322 struct s3c24xx_uart_port *ourport = args;
323 struct uart_port *port = &ourport->port;
324 struct circ_buf *xmit = &port->state->xmit;
325 struct s3c24xx_uart_dma *dma = ourport->dma;
326 struct dma_tx_state state;
327 unsigned long flags;
328 int count;
329
330 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
331 count = dma->tx_bytes_requested - state.residue;
332 async_tx_ack(dma->tx_desc);
333
334 dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
335 dma->tx_size, DMA_TO_DEVICE);
336
337 spin_lock_irqsave(&port->lock, flags);
338
339 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
340 port->icount.tx += count;
341 ourport->tx_in_progress = 0;
342
343 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
344 uart_write_wakeup(port);
345
346 s3c24xx_serial_start_next_tx(ourport);
347 spin_unlock_irqrestore(&port->lock, flags);
348 }
349
enable_tx_dma(struct s3c24xx_uart_port * ourport)350 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
351 {
352 struct uart_port *port = &ourport->port;
353 u32 ucon;
354
355 /* Mask Tx interrupt */
356 if (s3c24xx_serial_has_interrupt_mask(port))
357 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
358 else
359 disable_irq_nosync(ourport->tx_irq);
360
361 /* Enable tx dma mode */
362 ucon = rd_regl(port, S3C2410_UCON);
363 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
364 ucon |= S3C64XX_UCON_TXBURST_1;
365 ucon |= S3C64XX_UCON_TXMODE_DMA;
366 wr_regl(port, S3C2410_UCON, ucon);
367
368 ourport->tx_mode = S3C24XX_TX_DMA;
369 }
370
enable_tx_pio(struct s3c24xx_uart_port * ourport)371 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
372 {
373 struct uart_port *port = &ourport->port;
374 u32 ucon, ufcon;
375
376 /* Set ufcon txtrig */
377 ourport->tx_in_progress = S3C24XX_TX_PIO;
378 ufcon = rd_regl(port, S3C2410_UFCON);
379 wr_regl(port, S3C2410_UFCON, ufcon);
380
381 /* Enable tx pio mode */
382 ucon = rd_regl(port, S3C2410_UCON);
383 ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
384 ucon |= S3C64XX_UCON_TXMODE_CPU;
385 wr_regl(port, S3C2410_UCON, ucon);
386
387 /* Unmask Tx interrupt */
388 if (s3c24xx_serial_has_interrupt_mask(port))
389 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
390 S3C64XX_UINTM);
391 else
392 enable_irq(ourport->tx_irq);
393
394 ourport->tx_mode = S3C24XX_TX_PIO;
395 }
396
s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port * ourport)397 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
398 {
399 if (ourport->tx_mode != S3C24XX_TX_PIO)
400 enable_tx_pio(ourport);
401 }
402
s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port * ourport,unsigned int count)403 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
404 unsigned int count)
405 {
406 struct uart_port *port = &ourport->port;
407 struct circ_buf *xmit = &port->state->xmit;
408 struct s3c24xx_uart_dma *dma = ourport->dma;
409
410 if (ourport->tx_mode != S3C24XX_TX_DMA)
411 enable_tx_dma(ourport);
412
413 dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
414 dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
415
416 dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
417 dma->tx_size, DMA_TO_DEVICE);
418
419 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
420 dma->tx_transfer_addr, dma->tx_size,
421 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
422 if (!dma->tx_desc) {
423 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
424 return -EIO;
425 }
426
427 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
428 dma->tx_desc->callback_param = ourport;
429 dma->tx_bytes_requested = dma->tx_size;
430
431 ourport->tx_in_progress = S3C24XX_TX_DMA;
432 dma->tx_cookie = dmaengine_submit(dma->tx_desc);
433 dma_async_issue_pending(dma->tx_chan);
434 return 0;
435 }
436
s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port * ourport)437 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
438 {
439 struct uart_port *port = &ourport->port;
440 struct circ_buf *xmit = &port->state->xmit;
441 unsigned long count;
442
443 /* Get data size up to the end of buffer */
444 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
445
446 if (!count) {
447 s3c24xx_serial_stop_tx(port);
448 return;
449 }
450
451 if (!ourport->dma || !ourport->dma->tx_chan ||
452 count < ourport->min_dma_size ||
453 xmit->tail & (dma_get_cache_alignment() - 1))
454 s3c24xx_serial_start_tx_pio(ourport);
455 else
456 s3c24xx_serial_start_tx_dma(ourport, count);
457 }
458
s3c24xx_serial_start_tx(struct uart_port * port)459 static void s3c24xx_serial_start_tx(struct uart_port *port)
460 {
461 struct s3c24xx_uart_port *ourport = to_ourport(port);
462 struct circ_buf *xmit = &port->state->xmit;
463
464 if (!ourport->tx_enabled) {
465 if (port->flags & UPF_CONS_FLOW)
466 s3c24xx_serial_rx_disable(port);
467
468 ourport->tx_enabled = 1;
469 if (!ourport->dma || !ourport->dma->tx_chan)
470 s3c24xx_serial_start_tx_pio(ourport);
471 }
472
473 if (ourport->dma && ourport->dma->tx_chan) {
474 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
475 s3c24xx_serial_start_next_tx(ourport);
476 }
477 }
478
s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port * ourport,struct tty_port * tty,int count)479 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
480 struct tty_port *tty, int count)
481 {
482 struct s3c24xx_uart_dma *dma = ourport->dma;
483 int copied;
484
485 if (!count)
486 return;
487
488 dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
489 dma->rx_size, DMA_FROM_DEVICE);
490
491 ourport->port.icount.rx += count;
492 if (!tty) {
493 dev_err(ourport->port.dev, "No tty port\n");
494 return;
495 }
496 copied = tty_insert_flip_string(tty,
497 ((unsigned char *)(ourport->dma->rx_buf)), count);
498 if (copied != count) {
499 WARN_ON(1);
500 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
501 }
502 }
503
s3c24xx_serial_stop_rx(struct uart_port * port)504 static void s3c24xx_serial_stop_rx(struct uart_port *port)
505 {
506 struct s3c24xx_uart_port *ourport = to_ourport(port);
507 struct s3c24xx_uart_dma *dma = ourport->dma;
508 struct tty_port *t = &port->state->port;
509 struct dma_tx_state state;
510 enum dma_status dma_status;
511 unsigned int received;
512
513 if (ourport->rx_enabled) {
514 dev_dbg(port->dev, "stopping rx\n");
515 if (s3c24xx_serial_has_interrupt_mask(port))
516 s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
517 S3C64XX_UINTM);
518 else
519 disable_irq_nosync(ourport->rx_irq);
520 ourport->rx_enabled = 0;
521 }
522 if (dma && dma->rx_chan) {
523 dmaengine_pause(dma->tx_chan);
524 dma_status = dmaengine_tx_status(dma->rx_chan,
525 dma->rx_cookie, &state);
526 if (dma_status == DMA_IN_PROGRESS ||
527 dma_status == DMA_PAUSED) {
528 received = dma->rx_bytes_requested - state.residue;
529 dmaengine_terminate_all(dma->rx_chan);
530 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
531 }
532 }
533 }
534
535 static inline struct s3c24xx_uart_info
s3c24xx_port_to_info(struct uart_port * port)536 *s3c24xx_port_to_info(struct uart_port *port)
537 {
538 return to_ourport(port)->info;
539 }
540
541 static inline struct s3c2410_uartcfg
s3c24xx_port_to_cfg(struct uart_port * port)542 *s3c24xx_port_to_cfg(struct uart_port *port)
543 {
544 struct s3c24xx_uart_port *ourport;
545
546 if (port->dev == NULL)
547 return NULL;
548
549 ourport = container_of(port, struct s3c24xx_uart_port, port);
550 return ourport->cfg;
551 }
552
s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port * ourport,unsigned long ufstat)553 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
554 unsigned long ufstat)
555 {
556 struct s3c24xx_uart_info *info = ourport->info;
557
558 if (ufstat & info->rx_fifofull)
559 return ourport->port.fifosize;
560
561 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
562 }
563
564 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
s3c24xx_serial_rx_dma_complete(void * args)565 static void s3c24xx_serial_rx_dma_complete(void *args)
566 {
567 struct s3c24xx_uart_port *ourport = args;
568 struct uart_port *port = &ourport->port;
569
570 struct s3c24xx_uart_dma *dma = ourport->dma;
571 struct tty_port *t = &port->state->port;
572 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
573
574 struct dma_tx_state state;
575 unsigned long flags;
576 int received;
577
578 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
579 received = dma->rx_bytes_requested - state.residue;
580 async_tx_ack(dma->rx_desc);
581
582 spin_lock_irqsave(&port->lock, flags);
583
584 if (received)
585 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
586
587 if (tty) {
588 tty_flip_buffer_push(t);
589 tty_kref_put(tty);
590 }
591
592 s3c64xx_start_rx_dma(ourport);
593
594 spin_unlock_irqrestore(&port->lock, flags);
595 }
596
s3c64xx_start_rx_dma(struct s3c24xx_uart_port * ourport)597 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
598 {
599 struct s3c24xx_uart_dma *dma = ourport->dma;
600
601 dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
602 dma->rx_size, DMA_FROM_DEVICE);
603
604 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
605 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
606 DMA_PREP_INTERRUPT);
607 if (!dma->rx_desc) {
608 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
609 return;
610 }
611
612 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
613 dma->rx_desc->callback_param = ourport;
614 dma->rx_bytes_requested = dma->rx_size;
615
616 dma->rx_cookie = dmaengine_submit(dma->rx_desc);
617 dma_async_issue_pending(dma->rx_chan);
618 }
619
620 /* ? - where has parity gone?? */
621 #define S3C2410_UERSTAT_PARITY (0x1000)
622
enable_rx_dma(struct s3c24xx_uart_port * ourport)623 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
624 {
625 struct uart_port *port = &ourport->port;
626 unsigned int ucon;
627
628 /* set Rx mode to DMA mode */
629 ucon = rd_regl(port, S3C2410_UCON);
630 ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
631 S3C64XX_UCON_TIMEOUT_MASK |
632 S3C64XX_UCON_EMPTYINT_EN |
633 S3C64XX_UCON_DMASUS_EN |
634 S3C64XX_UCON_TIMEOUT_EN |
635 S3C64XX_UCON_RXMODE_MASK);
636 ucon |= S3C64XX_UCON_RXBURST_1 |
637 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
638 S3C64XX_UCON_EMPTYINT_EN |
639 S3C64XX_UCON_TIMEOUT_EN |
640 S3C64XX_UCON_RXMODE_DMA;
641 wr_regl(port, S3C2410_UCON, ucon);
642
643 ourport->rx_mode = S3C24XX_RX_DMA;
644 }
645
enable_rx_pio(struct s3c24xx_uart_port * ourport)646 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
647 {
648 struct uart_port *port = &ourport->port;
649 unsigned int ucon;
650
651 /* set Rx mode to DMA mode */
652 ucon = rd_regl(port, S3C2410_UCON);
653 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
654 S3C64XX_UCON_EMPTYINT_EN |
655 S3C64XX_UCON_DMASUS_EN |
656 S3C64XX_UCON_TIMEOUT_EN |
657 S3C64XX_UCON_RXMODE_MASK);
658 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
659 S3C64XX_UCON_TIMEOUT_EN |
660 S3C64XX_UCON_RXMODE_CPU;
661 wr_regl(port, S3C2410_UCON, ucon);
662
663 ourport->rx_mode = S3C24XX_RX_PIO;
664 }
665
666 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
667
s3c24xx_serial_rx_chars_dma(void * dev_id)668 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
669 {
670 unsigned int utrstat, received;
671 struct s3c24xx_uart_port *ourport = dev_id;
672 struct uart_port *port = &ourport->port;
673 struct s3c24xx_uart_dma *dma = ourport->dma;
674 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
675 struct tty_port *t = &port->state->port;
676 unsigned long flags;
677 struct dma_tx_state state;
678
679 utrstat = rd_regl(port, S3C2410_UTRSTAT);
680 rd_regl(port, S3C2410_UFSTAT);
681
682 spin_lock_irqsave(&port->lock, flags);
683
684 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
685 s3c64xx_start_rx_dma(ourport);
686 if (ourport->rx_mode == S3C24XX_RX_PIO)
687 enable_rx_dma(ourport);
688 goto finish;
689 }
690
691 if (ourport->rx_mode == S3C24XX_RX_DMA) {
692 dmaengine_pause(dma->rx_chan);
693 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
694 dmaengine_terminate_all(dma->rx_chan);
695 received = dma->rx_bytes_requested - state.residue;
696 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
697
698 enable_rx_pio(ourport);
699 }
700
701 s3c24xx_serial_rx_drain_fifo(ourport);
702
703 if (tty) {
704 tty_flip_buffer_push(t);
705 tty_kref_put(tty);
706 }
707
708 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
709
710 finish:
711 spin_unlock_irqrestore(&port->lock, flags);
712
713 return IRQ_HANDLED;
714 }
715
s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port * ourport)716 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
717 {
718 struct uart_port *port = &ourport->port;
719 unsigned int ufcon, ch, flag, ufstat, uerstat;
720 unsigned int fifocnt = 0;
721 int max_count = port->fifosize;
722
723 while (max_count-- > 0) {
724 /*
725 * Receive all characters known to be in FIFO
726 * before reading FIFO level again
727 */
728 if (fifocnt == 0) {
729 ufstat = rd_regl(port, S3C2410_UFSTAT);
730 fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
731 if (fifocnt == 0)
732 break;
733 }
734 fifocnt--;
735
736 uerstat = rd_regl(port, S3C2410_UERSTAT);
737 ch = rd_reg(port, S3C2410_URXH);
738
739 if (port->flags & UPF_CONS_FLOW) {
740 int txe = s3c24xx_serial_txempty_nofifo(port);
741
742 if (ourport->rx_enabled) {
743 if (!txe) {
744 ourport->rx_enabled = 0;
745 continue;
746 }
747 } else {
748 if (txe) {
749 ufcon = rd_regl(port, S3C2410_UFCON);
750 ufcon |= S3C2410_UFCON_RESETRX;
751 wr_regl(port, S3C2410_UFCON, ufcon);
752 ourport->rx_enabled = 1;
753 return;
754 }
755 continue;
756 }
757 }
758
759 /* insert the character into the buffer */
760
761 flag = TTY_NORMAL;
762 port->icount.rx++;
763
764 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
765 dev_dbg(port->dev,
766 "rxerr: port ch=0x%02x, rxs=0x%08x\n",
767 ch, uerstat);
768
769 /* check for break */
770 if (uerstat & S3C2410_UERSTAT_BREAK) {
771 dev_dbg(port->dev, "break!\n");
772 port->icount.brk++;
773 if (uart_handle_break(port))
774 continue; /* Ignore character */
775 }
776
777 if (uerstat & S3C2410_UERSTAT_FRAME)
778 port->icount.frame++;
779 if (uerstat & S3C2410_UERSTAT_OVERRUN)
780 port->icount.overrun++;
781
782 uerstat &= port->read_status_mask;
783
784 if (uerstat & S3C2410_UERSTAT_BREAK)
785 flag = TTY_BREAK;
786 else if (uerstat & S3C2410_UERSTAT_PARITY)
787 flag = TTY_PARITY;
788 else if (uerstat & (S3C2410_UERSTAT_FRAME |
789 S3C2410_UERSTAT_OVERRUN))
790 flag = TTY_FRAME;
791 }
792
793 if (uart_handle_sysrq_char(port, ch))
794 continue; /* Ignore character */
795
796 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
797 ch, flag);
798 }
799
800 tty_flip_buffer_push(&port->state->port);
801 }
802
s3c24xx_serial_rx_chars_pio(void * dev_id)803 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
804 {
805 struct s3c24xx_uart_port *ourport = dev_id;
806 struct uart_port *port = &ourport->port;
807 unsigned long flags;
808
809 spin_lock_irqsave(&port->lock, flags);
810 s3c24xx_serial_rx_drain_fifo(ourport);
811 spin_unlock_irqrestore(&port->lock, flags);
812
813 return IRQ_HANDLED;
814 }
815
s3c24xx_serial_rx_chars(int irq,void * dev_id)816 static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
817 {
818 struct s3c24xx_uart_port *ourport = dev_id;
819
820 if (ourport->dma && ourport->dma->rx_chan)
821 return s3c24xx_serial_rx_chars_dma(dev_id);
822 return s3c24xx_serial_rx_chars_pio(dev_id);
823 }
824
s3c24xx_serial_tx_chars(int irq,void * id)825 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
826 {
827 struct s3c24xx_uart_port *ourport = id;
828 struct uart_port *port = &ourport->port;
829 struct circ_buf *xmit = &port->state->xmit;
830 unsigned long flags;
831 int count, dma_count = 0;
832
833 spin_lock_irqsave(&port->lock, flags);
834
835 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
836
837 if (ourport->dma && ourport->dma->tx_chan &&
838 count >= ourport->min_dma_size) {
839 int align = dma_get_cache_alignment() -
840 (xmit->tail & (dma_get_cache_alignment() - 1));
841 if (count - align >= ourport->min_dma_size) {
842 dma_count = count - align;
843 count = align;
844 }
845 }
846
847 if (port->x_char) {
848 wr_reg(port, S3C2410_UTXH, port->x_char);
849 port->icount.tx++;
850 port->x_char = 0;
851 goto out;
852 }
853
854 /* if there isn't anything more to transmit, or the uart is now
855 * stopped, disable the uart and exit
856 */
857
858 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
859 s3c24xx_serial_stop_tx(port);
860 goto out;
861 }
862
863 /* try and drain the buffer... */
864
865 if (count > port->fifosize) {
866 count = port->fifosize;
867 dma_count = 0;
868 }
869
870 while (!uart_circ_empty(xmit) && count > 0) {
871 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
872 break;
873
874 wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
875 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
876 port->icount.tx++;
877 count--;
878 }
879
880 if (!count && dma_count) {
881 s3c24xx_serial_start_tx_dma(ourport, dma_count);
882 goto out;
883 }
884
885 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
886 uart_write_wakeup(port);
887
888 if (uart_circ_empty(xmit))
889 s3c24xx_serial_stop_tx(port);
890
891 out:
892 spin_unlock_irqrestore(&port->lock, flags);
893 return IRQ_HANDLED;
894 }
895
896 /* interrupt handler for s3c64xx and later SoC's.*/
s3c64xx_serial_handle_irq(int irq,void * id)897 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
898 {
899 struct s3c24xx_uart_port *ourport = id;
900 struct uart_port *port = &ourport->port;
901 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
902 irqreturn_t ret = IRQ_HANDLED;
903
904 if (pend & S3C64XX_UINTM_RXD_MSK) {
905 ret = s3c24xx_serial_rx_chars(irq, id);
906 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
907 }
908 if (pend & S3C64XX_UINTM_TXD_MSK) {
909 ret = s3c24xx_serial_tx_chars(irq, id);
910 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
911 }
912 return ret;
913 }
914
s3c24xx_serial_tx_empty(struct uart_port * port)915 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
916 {
917 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
918 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
919 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
920
921 if (ufcon & S3C2410_UFCON_FIFOMODE) {
922 if ((ufstat & info->tx_fifomask) != 0 ||
923 (ufstat & info->tx_fifofull))
924 return 0;
925
926 return 1;
927 }
928
929 return s3c24xx_serial_txempty_nofifo(port);
930 }
931
932 /* no modem control lines */
s3c24xx_serial_get_mctrl(struct uart_port * port)933 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
934 {
935 unsigned int umstat = rd_reg(port, S3C2410_UMSTAT);
936
937 if (umstat & S3C2410_UMSTAT_CTS)
938 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
939 else
940 return TIOCM_CAR | TIOCM_DSR;
941 }
942
s3c24xx_serial_set_mctrl(struct uart_port * port,unsigned int mctrl)943 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
944 {
945 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
946
947 if (mctrl & TIOCM_RTS)
948 umcon |= S3C2410_UMCOM_RTS_LOW;
949 else
950 umcon &= ~S3C2410_UMCOM_RTS_LOW;
951
952 wr_regl(port, S3C2410_UMCON, umcon);
953 }
954
s3c24xx_serial_break_ctl(struct uart_port * port,int break_state)955 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
956 {
957 unsigned long flags;
958 unsigned int ucon;
959
960 spin_lock_irqsave(&port->lock, flags);
961
962 ucon = rd_regl(port, S3C2410_UCON);
963
964 if (break_state)
965 ucon |= S3C2410_UCON_SBREAK;
966 else
967 ucon &= ~S3C2410_UCON_SBREAK;
968
969 wr_regl(port, S3C2410_UCON, ucon);
970
971 spin_unlock_irqrestore(&port->lock, flags);
972 }
973
s3c24xx_serial_request_dma(struct s3c24xx_uart_port * p)974 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
975 {
976 struct s3c24xx_uart_dma *dma = p->dma;
977 struct dma_slave_caps dma_caps;
978 const char *reason = NULL;
979 int ret;
980
981 /* Default slave configuration parameters */
982 dma->rx_conf.direction = DMA_DEV_TO_MEM;
983 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
984 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH;
985 dma->rx_conf.src_maxburst = 1;
986
987 dma->tx_conf.direction = DMA_MEM_TO_DEV;
988 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
989 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH;
990 dma->tx_conf.dst_maxburst = 1;
991
992 dma->rx_chan = dma_request_chan(p->port.dev, "rx");
993
994 if (IS_ERR(dma->rx_chan)) {
995 reason = "DMA RX channel request failed";
996 ret = PTR_ERR(dma->rx_chan);
997 goto err_warn;
998 }
999
1000 ret = dma_get_slave_caps(dma->rx_chan, &dma_caps);
1001 if (ret < 0 ||
1002 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1003 reason = "insufficient DMA RX engine capabilities";
1004 ret = -EOPNOTSUPP;
1005 goto err_release_rx;
1006 }
1007
1008 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
1009
1010 dma->tx_chan = dma_request_chan(p->port.dev, "tx");
1011 if (IS_ERR(dma->tx_chan)) {
1012 reason = "DMA TX channel request failed";
1013 ret = PTR_ERR(dma->tx_chan);
1014 goto err_release_rx;
1015 }
1016
1017 ret = dma_get_slave_caps(dma->tx_chan, &dma_caps);
1018 if (ret < 0 ||
1019 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1020 reason = "insufficient DMA TX engine capabilities";
1021 ret = -EOPNOTSUPP;
1022 goto err_release_tx;
1023 }
1024
1025 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
1026
1027 /* RX buffer */
1028 dma->rx_size = PAGE_SIZE;
1029
1030 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
1031 if (!dma->rx_buf) {
1032 ret = -ENOMEM;
1033 goto err_release_tx;
1034 }
1035
1036 dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf,
1037 dma->rx_size, DMA_FROM_DEVICE);
1038 if (dma_mapping_error(p->port.dev, dma->rx_addr)) {
1039 reason = "DMA mapping error for RX buffer";
1040 ret = -EIO;
1041 goto err_free_rx;
1042 }
1043
1044 /* TX buffer */
1045 dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf,
1046 UART_XMIT_SIZE, DMA_TO_DEVICE);
1047 if (dma_mapping_error(p->port.dev, dma->tx_addr)) {
1048 reason = "DMA mapping error for TX buffer";
1049 ret = -EIO;
1050 goto err_unmap_rx;
1051 }
1052
1053 return 0;
1054
1055 err_unmap_rx:
1056 dma_unmap_single(p->port.dev, dma->rx_addr, dma->rx_size,
1057 DMA_FROM_DEVICE);
1058 err_free_rx:
1059 kfree(dma->rx_buf);
1060 err_release_tx:
1061 dma_release_channel(dma->tx_chan);
1062 err_release_rx:
1063 dma_release_channel(dma->rx_chan);
1064 err_warn:
1065 if (reason)
1066 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason);
1067 return ret;
1068 }
1069
s3c24xx_serial_release_dma(struct s3c24xx_uart_port * p)1070 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
1071 {
1072 struct s3c24xx_uart_dma *dma = p->dma;
1073
1074 if (dma->rx_chan) {
1075 dmaengine_terminate_all(dma->rx_chan);
1076 dma_unmap_single(p->port.dev, dma->rx_addr,
1077 dma->rx_size, DMA_FROM_DEVICE);
1078 kfree(dma->rx_buf);
1079 dma_release_channel(dma->rx_chan);
1080 dma->rx_chan = NULL;
1081 }
1082
1083 if (dma->tx_chan) {
1084 dmaengine_terminate_all(dma->tx_chan);
1085 dma_unmap_single(p->port.dev, dma->tx_addr,
1086 UART_XMIT_SIZE, DMA_TO_DEVICE);
1087 dma_release_channel(dma->tx_chan);
1088 dma->tx_chan = NULL;
1089 }
1090 }
1091
s3c24xx_serial_shutdown(struct uart_port * port)1092 static void s3c24xx_serial_shutdown(struct uart_port *port)
1093 {
1094 struct s3c24xx_uart_port *ourport = to_ourport(port);
1095
1096 if (ourport->tx_claimed) {
1097 if (!s3c24xx_serial_has_interrupt_mask(port))
1098 free_irq(ourport->tx_irq, ourport);
1099 ourport->tx_enabled = 0;
1100 ourport->tx_claimed = 0;
1101 ourport->tx_mode = 0;
1102 }
1103
1104 if (ourport->rx_claimed) {
1105 if (!s3c24xx_serial_has_interrupt_mask(port))
1106 free_irq(ourport->rx_irq, ourport);
1107 ourport->rx_claimed = 0;
1108 ourport->rx_enabled = 0;
1109 }
1110
1111 /* Clear pending interrupts and mask all interrupts */
1112 if (s3c24xx_serial_has_interrupt_mask(port)) {
1113 free_irq(port->irq, ourport);
1114
1115 wr_regl(port, S3C64XX_UINTP, 0xf);
1116 wr_regl(port, S3C64XX_UINTM, 0xf);
1117 }
1118
1119 if (ourport->dma)
1120 s3c24xx_serial_release_dma(ourport);
1121
1122 ourport->tx_in_progress = 0;
1123 }
1124
s3c24xx_serial_startup(struct uart_port * port)1125 static int s3c24xx_serial_startup(struct uart_port *port)
1126 {
1127 struct s3c24xx_uart_port *ourport = to_ourport(port);
1128 int ret;
1129
1130 ourport->rx_enabled = 1;
1131
1132 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
1133 s3c24xx_serial_portname(port), ourport);
1134
1135 if (ret != 0) {
1136 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
1137 return ret;
1138 }
1139
1140 ourport->rx_claimed = 1;
1141
1142 dev_dbg(port->dev, "requesting tx irq...\n");
1143
1144 ourport->tx_enabled = 1;
1145
1146 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
1147 s3c24xx_serial_portname(port), ourport);
1148
1149 if (ret) {
1150 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1151 goto err;
1152 }
1153
1154 ourport->tx_claimed = 1;
1155
1156 /* the port reset code should have done the correct
1157 * register setup for the port controls
1158 */
1159
1160 return ret;
1161
1162 err:
1163 s3c24xx_serial_shutdown(port);
1164 return ret;
1165 }
1166
s3c64xx_serial_startup(struct uart_port * port)1167 static int s3c64xx_serial_startup(struct uart_port *port)
1168 {
1169 struct s3c24xx_uart_port *ourport = to_ourport(port);
1170 unsigned long flags;
1171 unsigned int ufcon;
1172 int ret;
1173
1174 wr_regl(port, S3C64XX_UINTM, 0xf);
1175 if (ourport->dma) {
1176 ret = s3c24xx_serial_request_dma(ourport);
1177 if (ret < 0) {
1178 devm_kfree(port->dev, ourport->dma);
1179 ourport->dma = NULL;
1180 }
1181 }
1182
1183 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1184 s3c24xx_serial_portname(port), ourport);
1185 if (ret) {
1186 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1187 return ret;
1188 }
1189
1190 /* For compatibility with s3c24xx Soc's */
1191 ourport->rx_enabled = 1;
1192 ourport->rx_claimed = 1;
1193 ourport->tx_enabled = 0;
1194 ourport->tx_claimed = 1;
1195
1196 spin_lock_irqsave(&port->lock, flags);
1197
1198 ufcon = rd_regl(port, S3C2410_UFCON);
1199 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1200 if (!uart_console(port))
1201 ufcon |= S3C2410_UFCON_RESETTX;
1202 wr_regl(port, S3C2410_UFCON, ufcon);
1203
1204 enable_rx_pio(ourport);
1205
1206 spin_unlock_irqrestore(&port->lock, flags);
1207
1208 /* Enable Rx Interrupt */
1209 s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1210
1211 return ret;
1212 }
1213
1214 /* power power management control */
1215
s3c24xx_serial_pm(struct uart_port * port,unsigned int level,unsigned int old)1216 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1217 unsigned int old)
1218 {
1219 struct s3c24xx_uart_port *ourport = to_ourport(port);
1220 int timeout = 10000;
1221
1222 ourport->pm_level = level;
1223
1224 switch (level) {
1225 case 3:
1226 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1227 udelay(100);
1228
1229 if (!IS_ERR(ourport->baudclk))
1230 clk_disable_unprepare(ourport->baudclk);
1231
1232 clk_disable_unprepare(ourport->clk);
1233 break;
1234
1235 case 0:
1236 clk_prepare_enable(ourport->clk);
1237
1238 if (!IS_ERR(ourport->baudclk))
1239 clk_prepare_enable(ourport->baudclk);
1240
1241 break;
1242 default:
1243 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1244 }
1245 }
1246
1247 /* baud rate calculation
1248 *
1249 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1250 * of different sources, including the peripheral clock ("pclk") and an
1251 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1252 * with a programmable extra divisor.
1253 *
1254 * The following code goes through the clock sources, and calculates the
1255 * baud clocks (and the resultant actual baud rates) and then tries to
1256 * pick the closest one and select that.
1257 *
1258 */
1259
1260 #define MAX_CLK_NAME_LENGTH 15
1261
s3c24xx_serial_getsource(struct uart_port * port)1262 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1263 {
1264 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1265 unsigned int ucon;
1266
1267 if (info->num_clks == 1)
1268 return 0;
1269
1270 ucon = rd_regl(port, S3C2410_UCON);
1271 ucon &= info->clksel_mask;
1272 return ucon >> info->clksel_shift;
1273 }
1274
s3c24xx_serial_setsource(struct uart_port * port,unsigned int clk_sel)1275 static void s3c24xx_serial_setsource(struct uart_port *port,
1276 unsigned int clk_sel)
1277 {
1278 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1279 unsigned int ucon;
1280
1281 if (info->num_clks == 1)
1282 return;
1283
1284 ucon = rd_regl(port, S3C2410_UCON);
1285 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1286 return;
1287
1288 ucon &= ~info->clksel_mask;
1289 ucon |= clk_sel << info->clksel_shift;
1290 wr_regl(port, S3C2410_UCON, ucon);
1291 }
1292
s3c24xx_serial_getclk(struct s3c24xx_uart_port * ourport,unsigned int req_baud,struct clk ** best_clk,unsigned int * clk_num)1293 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1294 unsigned int req_baud, struct clk **best_clk,
1295 unsigned int *clk_num)
1296 {
1297 struct s3c24xx_uart_info *info = ourport->info;
1298 struct clk *clk;
1299 unsigned long rate;
1300 unsigned int cnt, baud, quot, best_quot = 0;
1301 char clkname[MAX_CLK_NAME_LENGTH];
1302 int calc_deviation, deviation = (1 << 30) - 1;
1303
1304 for (cnt = 0; cnt < info->num_clks; cnt++) {
1305 /* Keep selected clock if provided */
1306 if (ourport->cfg->clk_sel &&
1307 !(ourport->cfg->clk_sel & (1 << cnt)))
1308 continue;
1309
1310 sprintf(clkname, "clk_uart_baud%d", cnt);
1311 clk = clk_get(ourport->port.dev, clkname);
1312 if (IS_ERR(clk))
1313 continue;
1314
1315 rate = clk_get_rate(clk);
1316 if (!rate) {
1317 dev_err(ourport->port.dev,
1318 "Failed to get clock rate for %s.\n", clkname);
1319 clk_put(clk);
1320 continue;
1321 }
1322
1323 if (ourport->info->has_divslot) {
1324 unsigned long div = rate / req_baud;
1325
1326 /* The UDIVSLOT register on the newer UARTs allows us to
1327 * get a divisor adjustment of 1/16th on the baud clock.
1328 *
1329 * We don't keep the UDIVSLOT value (the 16ths we
1330 * calculated by not multiplying the baud by 16) as it
1331 * is easy enough to recalculate.
1332 */
1333
1334 quot = div / 16;
1335 baud = rate / div;
1336 } else {
1337 quot = (rate + (8 * req_baud)) / (16 * req_baud);
1338 baud = rate / (quot * 16);
1339 }
1340 quot--;
1341
1342 calc_deviation = req_baud - baud;
1343 if (calc_deviation < 0)
1344 calc_deviation = -calc_deviation;
1345
1346 if (calc_deviation < deviation) {
1347 /*
1348 * If we find a better clk, release the previous one, if
1349 * any.
1350 */
1351 if (!IS_ERR(*best_clk))
1352 clk_put(*best_clk);
1353 *best_clk = clk;
1354 best_quot = quot;
1355 *clk_num = cnt;
1356 deviation = calc_deviation;
1357 } else {
1358 clk_put(clk);
1359 }
1360 }
1361
1362 return best_quot;
1363 }
1364
1365 /* udivslot_table[]
1366 *
1367 * This table takes the fractional value of the baud divisor and gives
1368 * the recommended setting for the UDIVSLOT register.
1369 */
1370 static u16 udivslot_table[16] = {
1371 [0] = 0x0000,
1372 [1] = 0x0080,
1373 [2] = 0x0808,
1374 [3] = 0x0888,
1375 [4] = 0x2222,
1376 [5] = 0x4924,
1377 [6] = 0x4A52,
1378 [7] = 0x54AA,
1379 [8] = 0x5555,
1380 [9] = 0xD555,
1381 [10] = 0xD5D5,
1382 [11] = 0xDDD5,
1383 [12] = 0xDDDD,
1384 [13] = 0xDFDD,
1385 [14] = 0xDFDF,
1386 [15] = 0xFFDF,
1387 };
1388
s3c24xx_serial_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)1389 static void s3c24xx_serial_set_termios(struct uart_port *port,
1390 struct ktermios *termios,
1391 struct ktermios *old)
1392 {
1393 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1394 struct s3c24xx_uart_port *ourport = to_ourport(port);
1395 struct clk *clk = ERR_PTR(-EINVAL);
1396 unsigned long flags;
1397 unsigned int baud, quot, clk_sel = 0;
1398 unsigned int ulcon;
1399 unsigned int umcon;
1400 unsigned int udivslot = 0;
1401
1402 /*
1403 * We don't support modem control lines.
1404 */
1405 termios->c_cflag &= ~(HUPCL | CMSPAR);
1406 termios->c_cflag |= CLOCAL;
1407
1408 /*
1409 * Ask the core to calculate the divisor for us.
1410 */
1411
1412 baud = uart_get_baud_rate(port, termios, old, 0, 3000000);
1413 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1414 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1415 quot = port->custom_divisor;
1416 if (IS_ERR(clk))
1417 return;
1418
1419 /* check to see if we need to change clock source */
1420
1421 if (ourport->baudclk != clk) {
1422 clk_prepare_enable(clk);
1423
1424 s3c24xx_serial_setsource(port, clk_sel);
1425
1426 if (!IS_ERR(ourport->baudclk)) {
1427 clk_disable_unprepare(ourport->baudclk);
1428 ourport->baudclk = ERR_PTR(-EINVAL);
1429 }
1430
1431 ourport->baudclk = clk;
1432 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1433 }
1434
1435 if (ourport->info->has_divslot) {
1436 unsigned int div = ourport->baudclk_rate / baud;
1437
1438 if (cfg->has_fracval) {
1439 udivslot = (div & 15);
1440 dev_dbg(port->dev, "fracval = %04x\n", udivslot);
1441 } else {
1442 udivslot = udivslot_table[div & 15];
1443 dev_dbg(port->dev, "udivslot = %04x (div %d)\n",
1444 udivslot, div & 15);
1445 }
1446 }
1447
1448 switch (termios->c_cflag & CSIZE) {
1449 case CS5:
1450 dev_dbg(port->dev, "config: 5bits/char\n");
1451 ulcon = S3C2410_LCON_CS5;
1452 break;
1453 case CS6:
1454 dev_dbg(port->dev, "config: 6bits/char\n");
1455 ulcon = S3C2410_LCON_CS6;
1456 break;
1457 case CS7:
1458 dev_dbg(port->dev, "config: 7bits/char\n");
1459 ulcon = S3C2410_LCON_CS7;
1460 break;
1461 case CS8:
1462 default:
1463 dev_dbg(port->dev, "config: 8bits/char\n");
1464 ulcon = S3C2410_LCON_CS8;
1465 break;
1466 }
1467
1468 /* preserve original lcon IR settings */
1469 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1470
1471 if (termios->c_cflag & CSTOPB)
1472 ulcon |= S3C2410_LCON_STOPB;
1473
1474 if (termios->c_cflag & PARENB) {
1475 if (termios->c_cflag & PARODD)
1476 ulcon |= S3C2410_LCON_PODD;
1477 else
1478 ulcon |= S3C2410_LCON_PEVEN;
1479 } else {
1480 ulcon |= S3C2410_LCON_PNONE;
1481 }
1482
1483 spin_lock_irqsave(&port->lock, flags);
1484
1485 dev_dbg(port->dev,
1486 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1487 ulcon, quot, udivslot);
1488
1489 wr_regl(port, S3C2410_ULCON, ulcon);
1490 wr_regl(port, S3C2410_UBRDIV, quot);
1491
1492 port->status &= ~UPSTAT_AUTOCTS;
1493
1494 umcon = rd_regl(port, S3C2410_UMCON);
1495 if (termios->c_cflag & CRTSCTS) {
1496 umcon |= S3C2410_UMCOM_AFC;
1497 /* Disable RTS when RX FIFO contains 63 bytes */
1498 umcon &= ~S3C2412_UMCON_AFC_8;
1499 port->status = UPSTAT_AUTOCTS;
1500 } else {
1501 umcon &= ~S3C2410_UMCOM_AFC;
1502 }
1503 wr_regl(port, S3C2410_UMCON, umcon);
1504
1505 if (ourport->info->has_divslot)
1506 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1507
1508 dev_dbg(port->dev,
1509 "uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1510 rd_regl(port, S3C2410_ULCON),
1511 rd_regl(port, S3C2410_UCON),
1512 rd_regl(port, S3C2410_UFCON));
1513
1514 /*
1515 * Update the per-port timeout.
1516 */
1517 uart_update_timeout(port, termios->c_cflag, baud);
1518
1519 /*
1520 * Which character status flags are we interested in?
1521 */
1522 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1523 if (termios->c_iflag & INPCK)
1524 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1525 S3C2410_UERSTAT_PARITY;
1526 /*
1527 * Which character status flags should we ignore?
1528 */
1529 port->ignore_status_mask = 0;
1530 if (termios->c_iflag & IGNPAR)
1531 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1532 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1533 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1534
1535 /*
1536 * Ignore all characters if CREAD is not set.
1537 */
1538 if ((termios->c_cflag & CREAD) == 0)
1539 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1540
1541 spin_unlock_irqrestore(&port->lock, flags);
1542 }
1543
s3c24xx_serial_type(struct uart_port * port)1544 static const char *s3c24xx_serial_type(struct uart_port *port)
1545 {
1546 switch (port->type) {
1547 case PORT_S3C2410:
1548 return "S3C2410";
1549 case PORT_S3C2440:
1550 return "S3C2440";
1551 case PORT_S3C2412:
1552 return "S3C2412";
1553 case PORT_S3C6400:
1554 return "S3C6400/10";
1555 default:
1556 return NULL;
1557 }
1558 }
1559
1560 #define MAP_SIZE (0x100)
1561
s3c24xx_serial_release_port(struct uart_port * port)1562 static void s3c24xx_serial_release_port(struct uart_port *port)
1563 {
1564 release_mem_region(port->mapbase, MAP_SIZE);
1565 }
1566
s3c24xx_serial_request_port(struct uart_port * port)1567 static int s3c24xx_serial_request_port(struct uart_port *port)
1568 {
1569 const char *name = s3c24xx_serial_portname(port);
1570
1571 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1572 }
1573
s3c24xx_serial_config_port(struct uart_port * port,int flags)1574 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1575 {
1576 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1577
1578 if (flags & UART_CONFIG_TYPE &&
1579 s3c24xx_serial_request_port(port) == 0)
1580 port->type = info->type;
1581 }
1582
1583 /*
1584 * verify the new serial_struct (for TIOCSSERIAL).
1585 */
1586 static int
s3c24xx_serial_verify_port(struct uart_port * port,struct serial_struct * ser)1587 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1588 {
1589 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1590
1591 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1592 return -EINVAL;
1593
1594 return 0;
1595 }
1596
1597 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1598
1599 static struct console s3c24xx_serial_console;
1600
s3c24xx_serial_console_init(void)1601 static int __init s3c24xx_serial_console_init(void)
1602 {
1603 register_console(&s3c24xx_serial_console);
1604 return 0;
1605 }
1606 console_initcall(s3c24xx_serial_console_init);
1607
1608 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1609 #else
1610 #define S3C24XX_SERIAL_CONSOLE NULL
1611 #endif
1612
1613 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1614 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1615 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1616 unsigned char c);
1617 #endif
1618
1619 static struct uart_ops s3c24xx_serial_ops = {
1620 .pm = s3c24xx_serial_pm,
1621 .tx_empty = s3c24xx_serial_tx_empty,
1622 .get_mctrl = s3c24xx_serial_get_mctrl,
1623 .set_mctrl = s3c24xx_serial_set_mctrl,
1624 .stop_tx = s3c24xx_serial_stop_tx,
1625 .start_tx = s3c24xx_serial_start_tx,
1626 .stop_rx = s3c24xx_serial_stop_rx,
1627 .break_ctl = s3c24xx_serial_break_ctl,
1628 .startup = s3c24xx_serial_startup,
1629 .shutdown = s3c24xx_serial_shutdown,
1630 .set_termios = s3c24xx_serial_set_termios,
1631 .type = s3c24xx_serial_type,
1632 .release_port = s3c24xx_serial_release_port,
1633 .request_port = s3c24xx_serial_request_port,
1634 .config_port = s3c24xx_serial_config_port,
1635 .verify_port = s3c24xx_serial_verify_port,
1636 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1637 .poll_get_char = s3c24xx_serial_get_poll_char,
1638 .poll_put_char = s3c24xx_serial_put_poll_char,
1639 #endif
1640 };
1641
1642 static struct uart_driver s3c24xx_uart_drv = {
1643 .owner = THIS_MODULE,
1644 .driver_name = "s3c2410_serial",
1645 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
1646 .cons = S3C24XX_SERIAL_CONSOLE,
1647 .dev_name = S3C24XX_SERIAL_NAME,
1648 .major = S3C24XX_SERIAL_MAJOR,
1649 .minor = S3C24XX_SERIAL_MINOR,
1650 };
1651
1652 #define __PORT_LOCK_UNLOCKED(i) \
1653 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1654 static struct s3c24xx_uart_port
1655 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1656 [0] = {
1657 .port = {
1658 .lock = __PORT_LOCK_UNLOCKED(0),
1659 .iotype = UPIO_MEM,
1660 .uartclk = 0,
1661 .fifosize = 16,
1662 .ops = &s3c24xx_serial_ops,
1663 .flags = UPF_BOOT_AUTOCONF,
1664 .line = 0,
1665 }
1666 },
1667 [1] = {
1668 .port = {
1669 .lock = __PORT_LOCK_UNLOCKED(1),
1670 .iotype = UPIO_MEM,
1671 .uartclk = 0,
1672 .fifosize = 16,
1673 .ops = &s3c24xx_serial_ops,
1674 .flags = UPF_BOOT_AUTOCONF,
1675 .line = 1,
1676 }
1677 },
1678 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1679 [2] = {
1680 .port = {
1681 .lock = __PORT_LOCK_UNLOCKED(2),
1682 .iotype = UPIO_MEM,
1683 .uartclk = 0,
1684 .fifosize = 16,
1685 .ops = &s3c24xx_serial_ops,
1686 .flags = UPF_BOOT_AUTOCONF,
1687 .line = 2,
1688 }
1689 },
1690 #endif
1691 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1692 [3] = {
1693 .port = {
1694 .lock = __PORT_LOCK_UNLOCKED(3),
1695 .iotype = UPIO_MEM,
1696 .uartclk = 0,
1697 .fifosize = 16,
1698 .ops = &s3c24xx_serial_ops,
1699 .flags = UPF_BOOT_AUTOCONF,
1700 .line = 3,
1701 }
1702 }
1703 #endif
1704 };
1705 #undef __PORT_LOCK_UNLOCKED
1706
1707 /* s3c24xx_serial_resetport
1708 *
1709 * reset the fifos and other the settings.
1710 */
1711
s3c24xx_serial_resetport(struct uart_port * port,struct s3c2410_uartcfg * cfg)1712 static void s3c24xx_serial_resetport(struct uart_port *port,
1713 struct s3c2410_uartcfg *cfg)
1714 {
1715 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1716 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1717 unsigned int ucon_mask;
1718
1719 ucon_mask = info->clksel_mask;
1720 if (info->type == PORT_S3C2440)
1721 ucon_mask |= S3C2440_UCON0_DIVMASK;
1722
1723 ucon &= ucon_mask;
1724 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1725
1726 /* reset both fifos */
1727 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1728 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1729
1730 /* some delay is required after fifo reset */
1731 udelay(1);
1732 }
1733
1734 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1735
s3c24xx_serial_cpufreq_transition(struct notifier_block * nb,unsigned long val,void * data)1736 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1737 unsigned long val, void *data)
1738 {
1739 struct s3c24xx_uart_port *port;
1740 struct uart_port *uport;
1741
1742 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1743 uport = &port->port;
1744
1745 /* check to see if port is enabled */
1746
1747 if (port->pm_level != 0)
1748 return 0;
1749
1750 /* try and work out if the baudrate is changing, we can detect
1751 * a change in rate, but we do not have support for detecting
1752 * a disturbance in the clock-rate over the change.
1753 */
1754
1755 if (IS_ERR(port->baudclk))
1756 goto exit;
1757
1758 if (port->baudclk_rate == clk_get_rate(port->baudclk))
1759 goto exit;
1760
1761 if (val == CPUFREQ_PRECHANGE) {
1762 /* we should really shut the port down whilst the
1763 * frequency change is in progress.
1764 */
1765
1766 } else if (val == CPUFREQ_POSTCHANGE) {
1767 struct ktermios *termios;
1768 struct tty_struct *tty;
1769
1770 if (uport->state == NULL)
1771 goto exit;
1772
1773 tty = uport->state->port.tty;
1774
1775 if (tty == NULL)
1776 goto exit;
1777
1778 termios = &tty->termios;
1779
1780 if (termios == NULL) {
1781 dev_warn(uport->dev, "%s: no termios?\n", __func__);
1782 goto exit;
1783 }
1784
1785 s3c24xx_serial_set_termios(uport, termios, NULL);
1786 }
1787
1788 exit:
1789 return 0;
1790 }
1791
1792 static inline int
s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port * port)1793 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1794 {
1795 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1796
1797 return cpufreq_register_notifier(&port->freq_transition,
1798 CPUFREQ_TRANSITION_NOTIFIER);
1799 }
1800
1801 static inline void
s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port * port)1802 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1803 {
1804 cpufreq_unregister_notifier(&port->freq_transition,
1805 CPUFREQ_TRANSITION_NOTIFIER);
1806 }
1807
1808 #else
1809 static inline int
s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port * port)1810 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1811 {
1812 return 0;
1813 }
1814
1815 static inline void
s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port * port)1816 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1817 {
1818 }
1819 #endif
1820
s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port * ourport)1821 static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport)
1822 {
1823 struct device *dev = ourport->port.dev;
1824 struct s3c24xx_uart_info *info = ourport->info;
1825 char clk_name[MAX_CLK_NAME_LENGTH];
1826 unsigned int clk_sel;
1827 struct clk *clk;
1828 int clk_num;
1829 int ret;
1830
1831 clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel;
1832 for (clk_num = 0; clk_num < info->num_clks; clk_num++) {
1833 if (!(clk_sel & (1 << clk_num)))
1834 continue;
1835
1836 sprintf(clk_name, "clk_uart_baud%d", clk_num);
1837 clk = clk_get(dev, clk_name);
1838 if (IS_ERR(clk))
1839 continue;
1840
1841 ret = clk_prepare_enable(clk);
1842 if (ret) {
1843 clk_put(clk);
1844 continue;
1845 }
1846
1847 ourport->baudclk = clk;
1848 ourport->baudclk_rate = clk_get_rate(clk);
1849 s3c24xx_serial_setsource(&ourport->port, clk_num);
1850
1851 return 0;
1852 }
1853
1854 return -EINVAL;
1855 }
1856
1857 /* s3c24xx_serial_init_port
1858 *
1859 * initialise a single serial port from the platform device given
1860 */
1861
s3c24xx_serial_init_port(struct s3c24xx_uart_port * ourport,struct platform_device * platdev)1862 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1863 struct platform_device *platdev)
1864 {
1865 struct uart_port *port = &ourport->port;
1866 struct s3c2410_uartcfg *cfg = ourport->cfg;
1867 struct resource *res;
1868 int ret;
1869
1870 if (platdev == NULL)
1871 return -ENODEV;
1872
1873 if (port->mapbase != 0)
1874 return -EINVAL;
1875
1876 /* setup info for port */
1877 port->dev = &platdev->dev;
1878
1879 /* Startup sequence is different for s3c64xx and higher SoC's */
1880 if (s3c24xx_serial_has_interrupt_mask(port))
1881 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1882
1883 port->uartclk = 1;
1884
1885 if (cfg->uart_flags & UPF_CONS_FLOW) {
1886 dev_dbg(port->dev, "enabling flow control\n");
1887 port->flags |= UPF_CONS_FLOW;
1888 }
1889
1890 /* sort our the physical and virtual addresses for each UART */
1891
1892 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1893 if (res == NULL) {
1894 dev_err(port->dev, "failed to find memory resource for uart\n");
1895 return -EINVAL;
1896 }
1897
1898 dev_dbg(port->dev, "resource %pR)\n", res);
1899
1900 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1901 if (!port->membase) {
1902 dev_err(port->dev, "failed to remap controller address\n");
1903 return -EBUSY;
1904 }
1905
1906 port->mapbase = res->start;
1907 ret = platform_get_irq(platdev, 0);
1908 if (ret < 0) {
1909 port->irq = 0;
1910 } else {
1911 port->irq = ret;
1912 ourport->rx_irq = ret;
1913 ourport->tx_irq = ret + 1;
1914 }
1915
1916 if (!s3c24xx_serial_has_interrupt_mask(port)) {
1917 ret = platform_get_irq(platdev, 1);
1918 if (ret > 0)
1919 ourport->tx_irq = ret;
1920 }
1921 /*
1922 * DMA is currently supported only on DT platforms, if DMA properties
1923 * are specified.
1924 */
1925 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1926 "dmas", NULL)) {
1927 ourport->dma = devm_kzalloc(port->dev,
1928 sizeof(*ourport->dma),
1929 GFP_KERNEL);
1930 if (!ourport->dma) {
1931 ret = -ENOMEM;
1932 goto err;
1933 }
1934 }
1935
1936 ourport->clk = clk_get(&platdev->dev, "uart");
1937 if (IS_ERR(ourport->clk)) {
1938 pr_err("%s: Controller clock not found\n",
1939 dev_name(&platdev->dev));
1940 ret = PTR_ERR(ourport->clk);
1941 goto err;
1942 }
1943
1944 ret = clk_prepare_enable(ourport->clk);
1945 if (ret) {
1946 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1947 clk_put(ourport->clk);
1948 goto err;
1949 }
1950
1951 ret = s3c24xx_serial_enable_baudclk(ourport);
1952 if (ret)
1953 pr_warn("uart: failed to enable baudclk\n");
1954
1955 /* Keep all interrupts masked and cleared */
1956 if (s3c24xx_serial_has_interrupt_mask(port)) {
1957 wr_regl(port, S3C64XX_UINTM, 0xf);
1958 wr_regl(port, S3C64XX_UINTP, 0xf);
1959 wr_regl(port, S3C64XX_UINTSP, 0xf);
1960 }
1961
1962 dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1963 &port->mapbase, port->membase, port->irq,
1964 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1965
1966 /* reset the fifos (and setup the uart) */
1967 s3c24xx_serial_resetport(port, cfg);
1968
1969 return 0;
1970
1971 err:
1972 port->mapbase = 0;
1973 return ret;
1974 }
1975
1976 /* Device driver serial port probe */
1977
1978 #ifdef CONFIG_OF
1979 static const struct of_device_id s3c24xx_uart_dt_match[];
1980 #endif
1981
1982 static int probe_index;
1983
1984 static inline struct s3c24xx_serial_drv_data *
s3c24xx_get_driver_data(struct platform_device * pdev)1985 s3c24xx_get_driver_data(struct platform_device *pdev)
1986 {
1987 #ifdef CONFIG_OF
1988 if (pdev->dev.of_node) {
1989 const struct of_device_id *match;
1990
1991 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1992 return (struct s3c24xx_serial_drv_data *)match->data;
1993 }
1994 #endif
1995 return (struct s3c24xx_serial_drv_data *)
1996 platform_get_device_id(pdev)->driver_data;
1997 }
1998
s3c24xx_serial_probe(struct platform_device * pdev)1999 static int s3c24xx_serial_probe(struct platform_device *pdev)
2000 {
2001 struct device_node *np = pdev->dev.of_node;
2002 struct s3c24xx_uart_port *ourport;
2003 int index = probe_index;
2004 int ret, prop = 0;
2005
2006 if (np) {
2007 ret = of_alias_get_id(np, "serial");
2008 if (ret >= 0)
2009 index = ret;
2010 }
2011
2012 if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
2013 dev_err(&pdev->dev, "serial%d out of range\n", index);
2014 return -EINVAL;
2015 }
2016 ourport = &s3c24xx_serial_ports[index];
2017
2018 ourport->drv_data = s3c24xx_get_driver_data(pdev);
2019 if (!ourport->drv_data) {
2020 dev_err(&pdev->dev, "could not find driver data\n");
2021 return -ENODEV;
2022 }
2023
2024 ourport->baudclk = ERR_PTR(-EINVAL);
2025 ourport->info = ourport->drv_data->info;
2026 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
2027 dev_get_platdata(&pdev->dev) :
2028 ourport->drv_data->def_cfg;
2029
2030 if (np) {
2031 of_property_read_u32(np,
2032 "samsung,uart-fifosize", &ourport->port.fifosize);
2033
2034 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
2035 switch (prop) {
2036 case 1:
2037 ourport->port.iotype = UPIO_MEM;
2038 break;
2039 case 4:
2040 ourport->port.iotype = UPIO_MEM32;
2041 break;
2042 default:
2043 dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n",
2044 prop);
2045 ret = -EINVAL;
2046 break;
2047 }
2048 }
2049 }
2050
2051 if (ourport->drv_data->fifosize[index])
2052 ourport->port.fifosize = ourport->drv_data->fifosize[index];
2053 else if (ourport->info->fifosize)
2054 ourport->port.fifosize = ourport->info->fifosize;
2055 ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE);
2056
2057 /*
2058 * DMA transfers must be aligned at least to cache line size,
2059 * so find minimal transfer size suitable for DMA mode
2060 */
2061 ourport->min_dma_size = max_t(int, ourport->port.fifosize,
2062 dma_get_cache_alignment());
2063
2064 dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport);
2065
2066 ret = s3c24xx_serial_init_port(ourport, pdev);
2067 if (ret < 0)
2068 return ret;
2069
2070 if (!s3c24xx_uart_drv.state) {
2071 ret = uart_register_driver(&s3c24xx_uart_drv);
2072 if (ret < 0) {
2073 pr_err("Failed to register Samsung UART driver\n");
2074 return ret;
2075 }
2076 }
2077
2078 dev_dbg(&pdev->dev, "%s: adding port\n", __func__);
2079 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
2080 platform_set_drvdata(pdev, &ourport->port);
2081
2082 /*
2083 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
2084 * so that a potential re-enablement through the pm-callback overlaps
2085 * and keeps the clock enabled in this case.
2086 */
2087 clk_disable_unprepare(ourport->clk);
2088 if (!IS_ERR(ourport->baudclk))
2089 clk_disable_unprepare(ourport->baudclk);
2090
2091 ret = s3c24xx_serial_cpufreq_register(ourport);
2092 if (ret < 0)
2093 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
2094
2095 probe_index++;
2096
2097 return 0;
2098 }
2099
s3c24xx_serial_remove(struct platform_device * dev)2100 static int s3c24xx_serial_remove(struct platform_device *dev)
2101 {
2102 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
2103
2104 if (port) {
2105 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
2106 uart_remove_one_port(&s3c24xx_uart_drv, port);
2107 }
2108
2109 uart_unregister_driver(&s3c24xx_uart_drv);
2110
2111 return 0;
2112 }
2113
2114 /* UART power management code */
2115 #ifdef CONFIG_PM_SLEEP
s3c24xx_serial_suspend(struct device * dev)2116 static int s3c24xx_serial_suspend(struct device *dev)
2117 {
2118 struct uart_port *port = s3c24xx_dev_to_port(dev);
2119
2120 if (port)
2121 uart_suspend_port(&s3c24xx_uart_drv, port);
2122
2123 return 0;
2124 }
2125
s3c24xx_serial_resume(struct device * dev)2126 static int s3c24xx_serial_resume(struct device *dev)
2127 {
2128 struct uart_port *port = s3c24xx_dev_to_port(dev);
2129 struct s3c24xx_uart_port *ourport = to_ourport(port);
2130
2131 if (port) {
2132 clk_prepare_enable(ourport->clk);
2133 if (!IS_ERR(ourport->baudclk))
2134 clk_prepare_enable(ourport->baudclk);
2135 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
2136 if (!IS_ERR(ourport->baudclk))
2137 clk_disable_unprepare(ourport->baudclk);
2138 clk_disable_unprepare(ourport->clk);
2139
2140 uart_resume_port(&s3c24xx_uart_drv, port);
2141 }
2142
2143 return 0;
2144 }
2145
s3c24xx_serial_resume_noirq(struct device * dev)2146 static int s3c24xx_serial_resume_noirq(struct device *dev)
2147 {
2148 struct uart_port *port = s3c24xx_dev_to_port(dev);
2149 struct s3c24xx_uart_port *ourport = to_ourport(port);
2150
2151 if (port) {
2152 /* restore IRQ mask */
2153 if (s3c24xx_serial_has_interrupt_mask(port)) {
2154 unsigned int uintm = 0xf;
2155
2156 if (ourport->tx_enabled)
2157 uintm &= ~S3C64XX_UINTM_TXD_MSK;
2158 if (ourport->rx_enabled)
2159 uintm &= ~S3C64XX_UINTM_RXD_MSK;
2160 clk_prepare_enable(ourport->clk);
2161 if (!IS_ERR(ourport->baudclk))
2162 clk_prepare_enable(ourport->baudclk);
2163 wr_regl(port, S3C64XX_UINTM, uintm);
2164 if (!IS_ERR(ourport->baudclk))
2165 clk_disable_unprepare(ourport->baudclk);
2166 clk_disable_unprepare(ourport->clk);
2167 }
2168 }
2169
2170 return 0;
2171 }
2172
2173 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
2174 .suspend = s3c24xx_serial_suspend,
2175 .resume = s3c24xx_serial_resume,
2176 .resume_noirq = s3c24xx_serial_resume_noirq,
2177 };
2178 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
2179
2180 #else /* !CONFIG_PM_SLEEP */
2181
2182 #define SERIAL_SAMSUNG_PM_OPS NULL
2183 #endif /* CONFIG_PM_SLEEP */
2184
2185 /* Console code */
2186
2187 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2188
2189 static struct uart_port *cons_uart;
2190
2191 static int
s3c24xx_serial_console_txrdy(struct uart_port * port,unsigned int ufcon)2192 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
2193 {
2194 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
2195 unsigned long ufstat, utrstat;
2196
2197 if (ufcon & S3C2410_UFCON_FIFOMODE) {
2198 /* fifo mode - check amount of data in fifo registers... */
2199
2200 ufstat = rd_regl(port, S3C2410_UFSTAT);
2201 return (ufstat & info->tx_fifofull) ? 0 : 1;
2202 }
2203
2204 /* in non-fifo mode, we go and use the tx buffer empty */
2205
2206 utrstat = rd_regl(port, S3C2410_UTRSTAT);
2207 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
2208 }
2209
2210 static bool
s3c24xx_port_configured(unsigned int ucon)2211 s3c24xx_port_configured(unsigned int ucon)
2212 {
2213 /* consider the serial port configured if the tx/rx mode set */
2214 return (ucon & 0xf) != 0;
2215 }
2216
2217 #ifdef CONFIG_CONSOLE_POLL
2218 /*
2219 * Console polling routines for writing and reading from the uart while
2220 * in an interrupt or debug context.
2221 */
2222
s3c24xx_serial_get_poll_char(struct uart_port * port)2223 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2224 {
2225 struct s3c24xx_uart_port *ourport = to_ourport(port);
2226 unsigned int ufstat;
2227
2228 ufstat = rd_regl(port, S3C2410_UFSTAT);
2229 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2230 return NO_POLL_CHAR;
2231
2232 return rd_reg(port, S3C2410_URXH);
2233 }
2234
s3c24xx_serial_put_poll_char(struct uart_port * port,unsigned char c)2235 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2236 unsigned char c)
2237 {
2238 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2239 unsigned int ucon = rd_regl(port, S3C2410_UCON);
2240
2241 /* not possible to xmit on unconfigured port */
2242 if (!s3c24xx_port_configured(ucon))
2243 return;
2244
2245 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2246 cpu_relax();
2247 wr_reg(port, S3C2410_UTXH, c);
2248 }
2249
2250 #endif /* CONFIG_CONSOLE_POLL */
2251
2252 static void
s3c24xx_serial_console_putchar(struct uart_port * port,int ch)2253 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2254 {
2255 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2256
2257 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2258 cpu_relax();
2259 wr_reg(port, S3C2410_UTXH, ch);
2260 }
2261
2262 static void
s3c24xx_serial_console_write(struct console * co,const char * s,unsigned int count)2263 s3c24xx_serial_console_write(struct console *co, const char *s,
2264 unsigned int count)
2265 {
2266 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2267
2268 /* not possible to xmit on unconfigured port */
2269 if (!s3c24xx_port_configured(ucon))
2270 return;
2271
2272 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2273 }
2274
2275 static void __init
s3c24xx_serial_get_options(struct uart_port * port,int * baud,int * parity,int * bits)2276 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2277 int *parity, int *bits)
2278 {
2279 struct clk *clk;
2280 unsigned int ulcon;
2281 unsigned int ucon;
2282 unsigned int ubrdiv;
2283 unsigned long rate;
2284 unsigned int clk_sel;
2285 char clk_name[MAX_CLK_NAME_LENGTH];
2286
2287 ulcon = rd_regl(port, S3C2410_ULCON);
2288 ucon = rd_regl(port, S3C2410_UCON);
2289 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2290
2291 if (s3c24xx_port_configured(ucon)) {
2292 switch (ulcon & S3C2410_LCON_CSMASK) {
2293 case S3C2410_LCON_CS5:
2294 *bits = 5;
2295 break;
2296 case S3C2410_LCON_CS6:
2297 *bits = 6;
2298 break;
2299 case S3C2410_LCON_CS7:
2300 *bits = 7;
2301 break;
2302 case S3C2410_LCON_CS8:
2303 default:
2304 *bits = 8;
2305 break;
2306 }
2307
2308 switch (ulcon & S3C2410_LCON_PMASK) {
2309 case S3C2410_LCON_PEVEN:
2310 *parity = 'e';
2311 break;
2312
2313 case S3C2410_LCON_PODD:
2314 *parity = 'o';
2315 break;
2316
2317 case S3C2410_LCON_PNONE:
2318 default:
2319 *parity = 'n';
2320 }
2321
2322 /* now calculate the baud rate */
2323
2324 clk_sel = s3c24xx_serial_getsource(port);
2325 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2326
2327 clk = clk_get(port->dev, clk_name);
2328 if (!IS_ERR(clk))
2329 rate = clk_get_rate(clk);
2330 else
2331 rate = 1;
2332
2333 *baud = rate / (16 * (ubrdiv + 1));
2334 dev_dbg(port->dev, "calculated baud %d\n", *baud);
2335 }
2336 }
2337
2338 static int __init
s3c24xx_serial_console_setup(struct console * co,char * options)2339 s3c24xx_serial_console_setup(struct console *co, char *options)
2340 {
2341 struct uart_port *port;
2342 int baud = 9600;
2343 int bits = 8;
2344 int parity = 'n';
2345 int flow = 'n';
2346
2347 /* is this a valid port */
2348
2349 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2350 co->index = 0;
2351
2352 port = &s3c24xx_serial_ports[co->index].port;
2353
2354 /* is the port configured? */
2355
2356 if (port->mapbase == 0x0)
2357 return -ENODEV;
2358
2359 cons_uart = port;
2360
2361 /*
2362 * Check whether an invalid uart number has been specified, and
2363 * if so, search for the first available port that does have
2364 * console support.
2365 */
2366 if (options)
2367 uart_parse_options(options, &baud, &parity, &bits, &flow);
2368 else
2369 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2370
2371 dev_dbg(port->dev, "baud %d\n", baud);
2372
2373 return uart_set_options(port, co, baud, parity, bits, flow);
2374 }
2375
2376 static struct console s3c24xx_serial_console = {
2377 .name = S3C24XX_SERIAL_NAME,
2378 .device = uart_console_device,
2379 .flags = CON_PRINTBUFFER,
2380 .index = -1,
2381 .write = s3c24xx_serial_console_write,
2382 .setup = s3c24xx_serial_console_setup,
2383 .data = &s3c24xx_uart_drv,
2384 };
2385 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2386
2387 #ifdef CONFIG_CPU_S3C2410
2388 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2389 .info = &(struct s3c24xx_uart_info) {
2390 .name = "Samsung S3C2410 UART",
2391 .type = PORT_S3C2410,
2392 .fifosize = 16,
2393 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2394 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2395 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2396 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2397 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2398 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2399 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2400 .num_clks = 2,
2401 .clksel_mask = S3C2410_UCON_CLKMASK,
2402 .clksel_shift = S3C2410_UCON_CLKSHIFT,
2403 },
2404 .def_cfg = &(struct s3c2410_uartcfg) {
2405 .ucon = S3C2410_UCON_DEFAULT,
2406 .ufcon = S3C2410_UFCON_DEFAULT,
2407 },
2408 };
2409 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2410 #else
2411 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2412 #endif
2413
2414 #ifdef CONFIG_CPU_S3C2412
2415 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2416 .info = &(struct s3c24xx_uart_info) {
2417 .name = "Samsung S3C2412 UART",
2418 .type = PORT_S3C2412,
2419 .fifosize = 64,
2420 .has_divslot = 1,
2421 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2422 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2423 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2424 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2425 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2426 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2427 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2428 .num_clks = 4,
2429 .clksel_mask = S3C2412_UCON_CLKMASK,
2430 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2431 },
2432 .def_cfg = &(struct s3c2410_uartcfg) {
2433 .ucon = S3C2410_UCON_DEFAULT,
2434 .ufcon = S3C2410_UFCON_DEFAULT,
2435 },
2436 };
2437 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2438 #else
2439 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2440 #endif
2441
2442 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2443 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2444 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2445 .info = &(struct s3c24xx_uart_info) {
2446 .name = "Samsung S3C2440 UART",
2447 .type = PORT_S3C2440,
2448 .fifosize = 64,
2449 .has_divslot = 1,
2450 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2451 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2452 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2453 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2454 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2455 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2456 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2457 .num_clks = 4,
2458 .clksel_mask = S3C2412_UCON_CLKMASK,
2459 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2460 },
2461 .def_cfg = &(struct s3c2410_uartcfg) {
2462 .ucon = S3C2410_UCON_DEFAULT,
2463 .ufcon = S3C2410_UFCON_DEFAULT,
2464 },
2465 };
2466 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2467 #else
2468 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2469 #endif
2470
2471 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2472 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2473 .info = &(struct s3c24xx_uart_info) {
2474 .name = "Samsung S3C6400 UART",
2475 .type = PORT_S3C6400,
2476 .fifosize = 64,
2477 .has_divslot = 1,
2478 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2479 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2480 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2481 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2482 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2483 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2484 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2485 .num_clks = 4,
2486 .clksel_mask = S3C6400_UCON_CLKMASK,
2487 .clksel_shift = S3C6400_UCON_CLKSHIFT,
2488 },
2489 .def_cfg = &(struct s3c2410_uartcfg) {
2490 .ucon = S3C2410_UCON_DEFAULT,
2491 .ufcon = S3C2410_UFCON_DEFAULT,
2492 },
2493 };
2494 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2495 #else
2496 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2497 #endif
2498
2499 #ifdef CONFIG_CPU_S5PV210
2500 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2501 .info = &(struct s3c24xx_uart_info) {
2502 .name = "Samsung S5PV210 UART",
2503 .type = PORT_S3C6400,
2504 .has_divslot = 1,
2505 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2506 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2507 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2508 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2509 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2510 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2511 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2512 .num_clks = 2,
2513 .clksel_mask = S5PV210_UCON_CLKMASK,
2514 .clksel_shift = S5PV210_UCON_CLKSHIFT,
2515 },
2516 .def_cfg = &(struct s3c2410_uartcfg) {
2517 .ucon = S5PV210_UCON_DEFAULT,
2518 .ufcon = S5PV210_UFCON_DEFAULT,
2519 },
2520 .fifosize = { 256, 64, 16, 16 },
2521 };
2522 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2523 #else
2524 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2525 #endif
2526
2527 #if defined(CONFIG_ARCH_EXYNOS)
2528 #define EXYNOS_COMMON_SERIAL_DRV_DATA \
2529 .info = &(struct s3c24xx_uart_info) { \
2530 .name = "Samsung Exynos UART", \
2531 .type = PORT_S3C6400, \
2532 .has_divslot = 1, \
2533 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
2534 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
2535 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
2536 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
2537 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
2538 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
2539 .def_clk_sel = S3C2410_UCON_CLKSEL0, \
2540 .num_clks = 1, \
2541 .clksel_mask = 0, \
2542 .clksel_shift = 0, \
2543 }, \
2544 .def_cfg = &(struct s3c2410_uartcfg) { \
2545 .ucon = S5PV210_UCON_DEFAULT, \
2546 .ufcon = S5PV210_UFCON_DEFAULT, \
2547 .has_fracval = 1, \
2548 } \
2549
2550 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2551 EXYNOS_COMMON_SERIAL_DRV_DATA,
2552 .fifosize = { 256, 64, 16, 16 },
2553 };
2554
2555 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2556 EXYNOS_COMMON_SERIAL_DRV_DATA,
2557 .fifosize = { 64, 256, 16, 256 },
2558 };
2559
2560 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2561 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2562 #else
2563 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2564 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2565 #endif
2566
2567 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2568 {
2569 .name = "s3c2410-uart",
2570 .driver_data = S3C2410_SERIAL_DRV_DATA,
2571 }, {
2572 .name = "s3c2412-uart",
2573 .driver_data = S3C2412_SERIAL_DRV_DATA,
2574 }, {
2575 .name = "s3c2440-uart",
2576 .driver_data = S3C2440_SERIAL_DRV_DATA,
2577 }, {
2578 .name = "s3c6400-uart",
2579 .driver_data = S3C6400_SERIAL_DRV_DATA,
2580 }, {
2581 .name = "s5pv210-uart",
2582 .driver_data = S5PV210_SERIAL_DRV_DATA,
2583 }, {
2584 .name = "exynos4210-uart",
2585 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
2586 }, {
2587 .name = "exynos5433-uart",
2588 .driver_data = EXYNOS5433_SERIAL_DRV_DATA,
2589 },
2590 { },
2591 };
2592 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2593
2594 #ifdef CONFIG_OF
2595 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2596 { .compatible = "samsung,s3c2410-uart",
2597 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2598 { .compatible = "samsung,s3c2412-uart",
2599 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2600 { .compatible = "samsung,s3c2440-uart",
2601 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2602 { .compatible = "samsung,s3c6400-uart",
2603 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2604 { .compatible = "samsung,s5pv210-uart",
2605 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2606 { .compatible = "samsung,exynos4210-uart",
2607 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2608 { .compatible = "samsung,exynos5433-uart",
2609 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2610 {},
2611 };
2612 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2613 #endif
2614
2615 static struct platform_driver samsung_serial_driver = {
2616 .probe = s3c24xx_serial_probe,
2617 .remove = s3c24xx_serial_remove,
2618 .id_table = s3c24xx_serial_driver_ids,
2619 .driver = {
2620 .name = "samsung-uart",
2621 .pm = SERIAL_SAMSUNG_PM_OPS,
2622 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2623 },
2624 };
2625
2626 module_platform_driver(samsung_serial_driver);
2627
2628 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2629 /*
2630 * Early console.
2631 */
2632
wr_reg_barrier(struct uart_port * port,u32 reg,u32 val)2633 static void wr_reg_barrier(struct uart_port *port, u32 reg, u32 val)
2634 {
2635 switch (port->iotype) {
2636 case UPIO_MEM:
2637 writeb(val, portaddr(port, reg));
2638 break;
2639 case UPIO_MEM32:
2640 writel(val, portaddr(port, reg));
2641 break;
2642 }
2643 }
2644
2645 struct samsung_early_console_data {
2646 u32 txfull_mask;
2647 };
2648
samsung_early_busyuart(struct uart_port * port)2649 static void samsung_early_busyuart(struct uart_port *port)
2650 {
2651 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2652 ;
2653 }
2654
samsung_early_busyuart_fifo(struct uart_port * port)2655 static void samsung_early_busyuart_fifo(struct uart_port *port)
2656 {
2657 struct samsung_early_console_data *data = port->private_data;
2658
2659 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2660 ;
2661 }
2662
samsung_early_putc(struct uart_port * port,int c)2663 static void samsung_early_putc(struct uart_port *port, int c)
2664 {
2665 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2666 samsung_early_busyuart_fifo(port);
2667 else
2668 samsung_early_busyuart(port);
2669
2670 wr_reg_barrier(port, S3C2410_UTXH, c);
2671 }
2672
samsung_early_write(struct console * con,const char * s,unsigned int n)2673 static void samsung_early_write(struct console *con, const char *s,
2674 unsigned int n)
2675 {
2676 struct earlycon_device *dev = con->data;
2677
2678 uart_console_write(&dev->port, s, n, samsung_early_putc);
2679 }
2680
samsung_early_console_setup(struct earlycon_device * device,const char * opt)2681 static int __init samsung_early_console_setup(struct earlycon_device *device,
2682 const char *opt)
2683 {
2684 if (!device->port.membase)
2685 return -ENODEV;
2686
2687 device->con->write = samsung_early_write;
2688 return 0;
2689 }
2690
2691 /* S3C2410 */
2692 static struct samsung_early_console_data s3c2410_early_console_data = {
2693 .txfull_mask = S3C2410_UFSTAT_TXFULL,
2694 };
2695
s3c2410_early_console_setup(struct earlycon_device * device,const char * opt)2696 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2697 const char *opt)
2698 {
2699 device->port.private_data = &s3c2410_early_console_data;
2700 return samsung_early_console_setup(device, opt);
2701 }
2702
2703 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2704 s3c2410_early_console_setup);
2705
2706 /* S3C2412, S3C2440, S3C64xx */
2707 static struct samsung_early_console_data s3c2440_early_console_data = {
2708 .txfull_mask = S3C2440_UFSTAT_TXFULL,
2709 };
2710
s3c2440_early_console_setup(struct earlycon_device * device,const char * opt)2711 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2712 const char *opt)
2713 {
2714 device->port.private_data = &s3c2440_early_console_data;
2715 return samsung_early_console_setup(device, opt);
2716 }
2717
2718 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2719 s3c2440_early_console_setup);
2720 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2721 s3c2440_early_console_setup);
2722 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2723 s3c2440_early_console_setup);
2724
2725 /* S5PV210, Exynos */
2726 static struct samsung_early_console_data s5pv210_early_console_data = {
2727 .txfull_mask = S5PV210_UFSTAT_TXFULL,
2728 };
2729
s5pv210_early_console_setup(struct earlycon_device * device,const char * opt)2730 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2731 const char *opt)
2732 {
2733 device->port.private_data = &s5pv210_early_console_data;
2734 return samsung_early_console_setup(device, opt);
2735 }
2736
2737 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2738 s5pv210_early_console_setup);
2739 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2740 s5pv210_early_console_setup);
2741 #endif
2742
2743 MODULE_ALIAS("platform:samsung-uart");
2744 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2745 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2746 MODULE_LICENSE("GPL v2");
2747