1 /* 2 * This header was generated from the Linux kernel headers by update_headers.py, 3 * to provide necessary information from kernel to userspace, such as constants, 4 * structures, and macros, and thus, contains no copyrightable information. 5 */ 6 #ifndef __ARM_KVM_H__ 7 #define __ARM_KVM_H__ 8 #include <linux/types.h> 9 #include <linux/psci.h> 10 #include <asm/ptrace.h> 11 #define __KVM_HAVE_GUEST_DEBUG 12 #define __KVM_HAVE_IRQ_LINE 13 #define __KVM_HAVE_READONLY_MEM 14 #define __KVM_HAVE_VCPU_EVENTS 15 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 16 #define KVM_REG_SIZE(id) \ 17 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 18 #define KVM_ARM_SVC_sp svc_regs[0] 19 #define KVM_ARM_SVC_lr svc_regs[1] 20 #define KVM_ARM_SVC_spsr svc_regs[2] 21 #define KVM_ARM_ABT_sp abt_regs[0] 22 #define KVM_ARM_ABT_lr abt_regs[1] 23 #define KVM_ARM_ABT_spsr abt_regs[2] 24 #define KVM_ARM_UND_sp und_regs[0] 25 #define KVM_ARM_UND_lr und_regs[1] 26 #define KVM_ARM_UND_spsr und_regs[2] 27 #define KVM_ARM_IRQ_sp irq_regs[0] 28 #define KVM_ARM_IRQ_lr irq_regs[1] 29 #define KVM_ARM_IRQ_spsr irq_regs[2] 30 #define KVM_ARM_FIQ_r8 fiq_regs[0] 31 #define KVM_ARM_FIQ_r9 fiq_regs[1] 32 #define KVM_ARM_FIQ_r10 fiq_regs[2] 33 #define KVM_ARM_FIQ_fp fiq_regs[3] 34 #define KVM_ARM_FIQ_ip fiq_regs[4] 35 #define KVM_ARM_FIQ_sp fiq_regs[5] 36 #define KVM_ARM_FIQ_lr fiq_regs[6] 37 #define KVM_ARM_FIQ_spsr fiq_regs[7] 38 struct kvm_regs { 39 struct pt_regs usr_regs; 40 unsigned long svc_regs[3]; 41 unsigned long abt_regs[3]; 42 unsigned long und_regs[3]; 43 unsigned long irq_regs[3]; 44 unsigned long fiq_regs[8]; 45 }; 46 #define KVM_ARM_TARGET_CORTEX_A15 0 47 #define KVM_ARM_TARGET_CORTEX_A7 1 48 #define KVM_ARM_NUM_TARGETS 2 49 #define KVM_ARM_DEVICE_TYPE_SHIFT 0 50 #define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT) 51 #define KVM_ARM_DEVICE_ID_SHIFT 16 52 #define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT) 53 #define KVM_ARM_DEVICE_VGIC_V2 0 54 #define KVM_VGIC_V2_ADDR_TYPE_DIST 0 55 #define KVM_VGIC_V2_ADDR_TYPE_CPU 1 56 #define KVM_VGIC_V2_DIST_SIZE 0x1000 57 #define KVM_VGIC_V2_CPU_SIZE 0x2000 58 #define KVM_VGIC_V3_ADDR_TYPE_DIST 2 59 #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 60 #define KVM_VGIC_ITS_ADDR_TYPE 4 61 #define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5 62 #define KVM_VGIC_V3_DIST_SIZE SZ_64K 63 #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) 64 #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K) 65 #define KVM_ARM_VCPU_POWER_OFF 0 66 #define KVM_ARM_VCPU_PSCI_0_2 1 67 struct kvm_vcpu_init { 68 __u32 target; 69 __u32 features[7]; 70 }; 71 struct kvm_sregs { 72 }; 73 struct kvm_fpu { 74 }; 75 struct kvm_guest_debug_arch { 76 }; 77 struct kvm_debug_exit_arch { 78 }; 79 struct kvm_sync_regs { 80 81 __u64 device_irq_level; 82 }; 83 struct kvm_arch_memory_slot { 84 }; 85 struct kvm_vcpu_events { 86 struct { 87 __u8 serror_pending; 88 __u8 serror_has_esr; 89 90 __u8 pad[6]; 91 __u64 serror_esr; 92 } exception; 93 __u32 reserved[12]; 94 }; 95 #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 96 #define KVM_REG_ARM_COPROC_SHIFT 16 97 #define KVM_REG_ARM_32_OPC2_MASK 0x0000000000000007 98 #define KVM_REG_ARM_32_OPC2_SHIFT 0 99 #define KVM_REG_ARM_OPC1_MASK 0x0000000000000078 100 #define KVM_REG_ARM_OPC1_SHIFT 3 101 #define KVM_REG_ARM_CRM_MASK 0x0000000000000780 102 #define KVM_REG_ARM_CRM_SHIFT 7 103 #define KVM_REG_ARM_32_CRN_MASK 0x0000000000007800 104 #define KVM_REG_ARM_32_CRN_SHIFT 11 105 #define KVM_REG_ARM_SECURE_MASK 0x0000000010000000 106 #define KVM_REG_ARM_SECURE_SHIFT 28 107 #define ARM_CP15_REG_SHIFT_MASK(x,n) \ 108 (((x) << KVM_REG_ARM_ ## n ## _SHIFT) & KVM_REG_ARM_ ## n ## _MASK) 109 #define __ARM_CP15_REG(op1,crn,crm,op2) \ 110 (KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT) | \ 111 ARM_CP15_REG_SHIFT_MASK(op1, OPC1) | \ 112 ARM_CP15_REG_SHIFT_MASK(crn, 32_CRN) | \ 113 ARM_CP15_REG_SHIFT_MASK(crm, CRM) | \ 114 ARM_CP15_REG_SHIFT_MASK(op2, 32_OPC2)) 115 #define ARM_CP15_REG32(...) (__ARM_CP15_REG(__VA_ARGS__) | KVM_REG_SIZE_U32) 116 #define __ARM_CP15_REG64(op1,crm) \ 117 (__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64) 118 #define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__) 119 #define KVM_REG_ARM_PTIMER_CTL ARM_CP15_REG32(0, 14, 2, 1) 120 #define KVM_REG_ARM_PTIMER_CNT ARM_CP15_REG64(0, 14) 121 #define KVM_REG_ARM_PTIMER_CVAL ARM_CP15_REG64(2, 14) 122 #define KVM_REG_ARM_TIMER_CTL ARM_CP15_REG32(0, 14, 3, 1) 123 #define KVM_REG_ARM_TIMER_CNT ARM_CP15_REG64(1, 14) 124 #define KVM_REG_ARM_TIMER_CVAL ARM_CP15_REG64(3, 14) 125 #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) 126 #define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / 4) 127 #define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT) 128 #define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00 129 #define KVM_REG_ARM_DEMUX_ID_SHIFT 8 130 #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT) 131 #define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF 132 #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0 133 #define KVM_REG_ARM_VFP (0x0012 << KVM_REG_ARM_COPROC_SHIFT) 134 #define KVM_REG_ARM_VFP_MASK 0x000000000000FFFF 135 #define KVM_REG_ARM_VFP_BASE_REG 0x0 136 #define KVM_REG_ARM_VFP_FPSID 0x1000 137 #define KVM_REG_ARM_VFP_FPSCR 0x1001 138 #define KVM_REG_ARM_VFP_MVFR1 0x1006 139 #define KVM_REG_ARM_VFP_MVFR0 0x1007 140 #define KVM_REG_ARM_VFP_FPEXC 0x1008 141 #define KVM_REG_ARM_VFP_FPINST 0x1009 142 #define KVM_REG_ARM_VFP_FPINST2 0x100A 143 #define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT) 144 #define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM | KVM_REG_SIZE_U64 | \ 145 KVM_REG_ARM_FW | ((r) & 0xffff)) 146 #define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0) 147 #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 148 #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 149 #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2 150 #define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32 151 #define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT) 152 #define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32 153 #define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \ 154 (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT) 155 #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0 156 #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) 157 #define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff) 158 #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3 159 #define KVM_DEV_ARM_VGIC_GRP_CTRL 4 160 #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5 161 #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6 162 #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7 163 #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8 164 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10 165 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \ 166 (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) 167 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff 168 #define VGIC_LEVEL_INFO_LINE_LEVEL 0 169 #define KVM_ARM_VCPU_PMU_V3_CTRL 0 170 #define KVM_ARM_VCPU_PMU_V3_IRQ 0 171 #define KVM_ARM_VCPU_PMU_V3_INIT 1 172 #define KVM_ARM_VCPU_TIMER_CTRL 1 173 #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 174 #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 175 #define KVM_DEV_ARM_VGIC_CTRL_INIT 0 176 #define KVM_DEV_ARM_ITS_SAVE_TABLES 1 177 #define KVM_DEV_ARM_ITS_RESTORE_TABLES 2 178 #define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3 179 #define KVM_DEV_ARM_ITS_CTRL_RESET 4 180 #define KVM_ARM_IRQ_TYPE_SHIFT 24 181 #define KVM_ARM_IRQ_TYPE_MASK 0xff 182 #define KVM_ARM_IRQ_VCPU_SHIFT 16 183 #define KVM_ARM_IRQ_VCPU_MASK 0xff 184 #define KVM_ARM_IRQ_NUM_SHIFT 0 185 #define KVM_ARM_IRQ_NUM_MASK 0xffff 186 #define KVM_ARM_IRQ_TYPE_CPU 0 187 #define KVM_ARM_IRQ_TYPE_SPI 1 188 #define KVM_ARM_IRQ_TYPE_PPI 2 189 #define KVM_ARM_IRQ_CPU_IRQ 0 190 #define KVM_ARM_IRQ_CPU_FIQ 1 191 #define KVM_ARM_IRQ_GIC_MAX 127 192 #define KVM_NR_IRQCHIPS 1 193 #define KVM_PSCI_FN_BASE 0x95c1ba5e 194 #define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n)) 195 #define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0) 196 #define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1) 197 #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) 198 #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) 199 #define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS 200 #define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED 201 #define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS 202 #define KVM_PSCI_RET_DENIED PSCI_RET_DENIED 203 #endif 204