1 /* 2 * This header was generated from the Linux kernel headers by update_headers.py, 3 * to provide necessary information from kernel to userspace, such as constants, 4 * structures, and macros, and thus, contains no copyrightable information. 5 */ 6 #ifndef _UAPI_LINUX_CYCLADES_H 7 #define _UAPI_LINUX_CYCLADES_H 8 #include <linux/types.h> 9 struct cyclades_monitor { 10 unsigned long int_count; 11 unsigned long char_count; 12 unsigned long char_max; 13 unsigned long char_last; 14 }; 15 struct cyclades_idle_stats { 16 __kernel_time_t in_use; 17 __kernel_time_t recv_idle; 18 __kernel_time_t xmit_idle; 19 unsigned long recv_bytes; 20 unsigned long xmit_bytes; 21 unsigned long overruns; 22 unsigned long frame_errs; 23 unsigned long parity_errs; 24 }; 25 #define CYCLADES_MAGIC 0x4359 26 #define CYGETMON 0x435901 27 #define CYGETTHRESH 0x435902 28 #define CYSETTHRESH 0x435903 29 #define CYGETDEFTHRESH 0x435904 30 #define CYSETDEFTHRESH 0x435905 31 #define CYGETTIMEOUT 0x435906 32 #define CYSETTIMEOUT 0x435907 33 #define CYGETDEFTIMEOUT 0x435908 34 #define CYSETDEFTIMEOUT 0x435909 35 #define CYSETRFLOW 0x43590a 36 #define CYGETRFLOW 0x43590b 37 #define CYSETRTSDTR_INV 0x43590c 38 #define CYGETRTSDTR_INV 0x43590d 39 #define CYZSETPOLLCYCLE 0x43590e 40 #define CYZGETPOLLCYCLE 0x43590f 41 #define CYGETCD1400VER 0x435910 42 #define CYSETWAIT 0x435912 43 #define CYGETWAIT 0x435913 44 #define CZIOC ('M' << 8) 45 #define CZ_NBOARDS (CZIOC|0xfa) 46 #define CZ_BOOT_START (CZIOC|0xfb) 47 #define CZ_BOOT_DATA (CZIOC|0xfc) 48 #define CZ_BOOT_END (CZIOC|0xfd) 49 #define CZ_TEST (CZIOC|0xfe) 50 #define CZ_DEF_POLL (HZ/25) 51 #define MAX_BOARD 4 52 #define MAX_DEV 256 53 #define CYZ_MAX_SPEED 921600 54 #define CYZ_FIFO_SIZE 16 55 #define CYZ_BOOT_NWORDS 0x100 56 struct CYZ_BOOT_CTRL { 57 unsigned short nboard; 58 int status[MAX_BOARD]; 59 int nchannel[MAX_BOARD]; 60 int fw_rev[MAX_BOARD]; 61 unsigned long offset; 62 unsigned long data[CYZ_BOOT_NWORDS]; 63 }; 64 #ifndef DP_WINDOW_SIZE 65 #define DP_WINDOW_SIZE (0x00080000) 66 #define ZE_DP_WINDOW_SIZE (0x00100000) 67 #define CTRL_WINDOW_SIZE (0x00000080) 68 struct CUSTOM_REG { 69 __u32 fpga_id; 70 __u32 fpga_version; 71 __u32 cpu_start; 72 __u32 cpu_stop; 73 __u32 misc_reg; 74 __u32 idt_mode; 75 __u32 uart_irq_status; 76 __u32 clear_timer0_irq; 77 __u32 clear_timer1_irq; 78 __u32 clear_timer2_irq; 79 __u32 test_register; 80 __u32 test_count; 81 __u32 timer_select; 82 __u32 pr_uart_irq_status; 83 __u32 ram_wait_state; 84 __u32 uart_wait_state; 85 __u32 timer_wait_state; 86 __u32 ack_wait_state; 87 }; 88 struct RUNTIME_9060 { 89 __u32 loc_addr_range; 90 __u32 loc_addr_base; 91 __u32 loc_arbitr; 92 __u32 endian_descr; 93 __u32 loc_rom_range; 94 __u32 loc_rom_base; 95 __u32 loc_bus_descr; 96 __u32 loc_range_mst; 97 __u32 loc_base_mst; 98 __u32 loc_range_io; 99 __u32 pci_base_mst; 100 __u32 pci_conf_io; 101 __u32 filler1; 102 __u32 filler2; 103 __u32 filler3; 104 __u32 filler4; 105 __u32 mail_box_0; 106 __u32 mail_box_1; 107 __u32 mail_box_2; 108 __u32 mail_box_3; 109 __u32 filler5; 110 __u32 filler6; 111 __u32 filler7; 112 __u32 filler8; 113 __u32 pci_doorbell; 114 __u32 loc_doorbell; 115 __u32 intr_ctrl_stat; 116 __u32 init_ctrl; 117 }; 118 #define WIN_RAM 0x00000001L 119 #define WIN_CREG 0x14000001L 120 #define TIMER_BY_1M 0x00 121 #define TIMER_BY_256K 0x01 122 #define TIMER_BY_128K 0x02 123 #define TIMER_BY_32K 0x03 124 #endif 125 #ifndef ZFIRM_ID 126 #define MAX_CHAN 64 127 #define ID_ADDRESS 0x00000180L 128 #define ZFIRM_ID 0x5557465AL 129 #define ZFIRM_HLT 0x59505B5CL 130 #define ZFIRM_RST 0x56040674L 131 #define ZF_TINACT_DEF 1000 132 #define ZF_TINACT ZF_TINACT_DEF 133 struct FIRM_ID { 134 __u32 signature; 135 __u32 zfwctrl_addr; 136 }; 137 #define C_OS_LINUX 0x00000030 138 #define C_CH_DISABLE 0x00000000 139 #define C_CH_TXENABLE 0x00000001 140 #define C_CH_RXENABLE 0x00000002 141 #define C_CH_ENABLE 0x00000003 142 #define C_CH_LOOPBACK 0x00000004 143 #define C_PR_NONE 0x00000000 144 #define C_PR_ODD 0x00000001 145 #define C_PR_EVEN 0x00000002 146 #define C_PR_MARK 0x00000004 147 #define C_PR_SPACE 0x00000008 148 #define C_PR_PARITY 0x000000ff 149 #define C_PR_DISCARD 0x00000100 150 #define C_PR_IGNORE 0x00000200 151 #define C_DL_CS5 0x00000001 152 #define C_DL_CS6 0x00000002 153 #define C_DL_CS7 0x00000004 154 #define C_DL_CS8 0x00000008 155 #define C_DL_CS 0x0000000f 156 #define C_DL_1STOP 0x00000010 157 #define C_DL_15STOP 0x00000020 158 #define C_DL_2STOP 0x00000040 159 #define C_DL_STOP 0x000000f0 160 #define C_IN_DISABLE 0x00000000 161 #define C_IN_TXBEMPTY 0x00000001 162 #define C_IN_TXLOWWM 0x00000002 163 #define C_IN_RXHIWM 0x00000010 164 #define C_IN_RXNNDT 0x00000020 165 #define C_IN_MDCD 0x00000100 166 #define C_IN_MDSR 0x00000200 167 #define C_IN_MRI 0x00000400 168 #define C_IN_MCTS 0x00000800 169 #define C_IN_RXBRK 0x00001000 170 #define C_IN_PR_ERROR 0x00002000 171 #define C_IN_FR_ERROR 0x00004000 172 #define C_IN_OVR_ERROR 0x00008000 173 #define C_IN_RXOFL 0x00010000 174 #define C_IN_IOCTLW 0x00020000 175 #define C_IN_MRTS 0x00040000 176 #define C_IN_ICHAR 0x00080000 177 178 #define C_FL_OXX 0x00000001 179 #define C_FL_IXX 0x00000002 180 #define C_FL_OIXANY 0x00000004 181 #define C_FL_SWFLOW 0x0000000f 182 #define C_FS_TXIDLE 0x00000000 183 #define C_FS_SENDING 0x00000001 184 #define C_FS_SWFLOW 0x00000002 185 #define C_RS_PARAM 0x80000000 186 #define C_RS_RTS 0x00000001 187 #define C_RS_DTR 0x00000004 188 #define C_RS_DCD 0x00000100 189 #define C_RS_DSR 0x00000200 190 #define C_RS_RI 0x00000400 191 #define C_RS_CTS 0x00000800 192 #define C_CM_RESET 0x01 193 #define C_CM_IOCTL 0x02 194 #define C_CM_IOCTLW 0x03 195 #define C_CM_IOCTLM 0x04 196 #define C_CM_SENDXOFF 0x10 197 #define C_CM_SENDXON 0x11 198 #define C_CM_CLFLOW 0x12 199 #define C_CM_SENDBRK 0x41 200 #define C_CM_INTBACK 0x42 201 #define C_CM_SET_BREAK 0x43 202 #define C_CM_CLR_BREAK 0x44 203 #define C_CM_CMD_DONE 0x45 204 #define C_CM_INTBACK2 0x46 205 #define C_CM_TINACT 0x51 206 #define C_CM_IRQ_ENBL 0x52 207 #define C_CM_IRQ_DSBL 0x53 208 #define C_CM_ACK_ENBL 0x54 209 #define C_CM_ACK_DSBL 0x55 210 #define C_CM_FLUSH_RX 0x56 211 #define C_CM_FLUSH_TX 0x57 212 #define C_CM_Q_ENABLE 0x58 213 #define C_CM_Q_DISABLE 0x59 214 #define C_CM_TXBEMPTY 0x60 215 #define C_CM_TXLOWWM 0x61 216 #define C_CM_RXHIWM 0x62 217 #define C_CM_RXNNDT 0x63 218 #define C_CM_TXFEMPTY 0x64 219 #define C_CM_ICHAR 0x65 220 #define C_CM_MDCD 0x70 221 #define C_CM_MDSR 0x71 222 #define C_CM_MRI 0x72 223 #define C_CM_MCTS 0x73 224 #define C_CM_MRTS 0x74 225 #define C_CM_RXBRK 0x84 226 #define C_CM_PR_ERROR 0x85 227 #define C_CM_FR_ERROR 0x86 228 #define C_CM_OVR_ERROR 0x87 229 #define C_CM_RXOFL 0x88 230 #define C_CM_CMDERROR 0x90 231 #define C_CM_FATAL 0x91 232 #define C_CM_HW_RESET 0x92 233 struct CH_CTRL { 234 __u32 op_mode; 235 __u32 intr_enable; 236 __u32 sw_flow; 237 __u32 flow_status; 238 __u32 comm_baud; 239 __u32 comm_parity; 240 __u32 comm_data_l; 241 __u32 comm_flags; 242 __u32 hw_flow; 243 __u32 rs_control; 244 __u32 rs_status; 245 __u32 flow_xon; 246 __u32 flow_xoff; 247 __u32 hw_overflow; 248 __u32 sw_overflow; 249 __u32 comm_error; 250 __u32 ichar; 251 __u32 filler[7]; 252 }; 253 struct BUF_CTRL { 254 __u32 flag_dma; 255 __u32 tx_bufaddr; 256 __u32 tx_bufsize; 257 __u32 tx_threshold; 258 __u32 tx_get; 259 __u32 tx_put; 260 __u32 rx_bufaddr; 261 __u32 rx_bufsize; 262 __u32 rx_threshold; 263 __u32 rx_get; 264 __u32 rx_put; 265 __u32 filler[5]; 266 }; 267 struct BOARD_CTRL { 268 269 __u32 n_channel; 270 __u32 fw_version; 271 272 __u32 op_system; 273 __u32 dr_version; 274 275 __u32 inactivity; 276 277 __u32 hcmd_channel; 278 __u32 hcmd_param; 279 280 __u32 fwcmd_channel; 281 __u32 fwcmd_param; 282 __u32 zf_int_queue_addr; 283 284 __u32 filler[6]; 285 }; 286 #define QUEUE_SIZE (10*MAX_CHAN) 287 struct INT_QUEUE { 288 unsigned char intr_code[QUEUE_SIZE]; 289 unsigned long channel[QUEUE_SIZE]; 290 unsigned long param[QUEUE_SIZE]; 291 unsigned long put; 292 unsigned long get; 293 }; 294 295 struct ZFW_CTRL { 296 struct BOARD_CTRL board_ctrl; 297 struct CH_CTRL ch_ctrl[MAX_CHAN]; 298 struct BUF_CTRL buf_ctrl[MAX_CHAN]; 299 }; 300 #endif 301 #endif 302