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1 /*
2  * This header was generated from the Linux kernel headers by update_headers.py,
3  * to provide necessary information from kernel to userspace, such as constants,
4  * structures, and macros, and thus, contains no copyrightable information.
5  */
6 #ifndef __LINUX_DCBNL_H__
7 #define __LINUX_DCBNL_H__
8 #include <linux/types.h>
9 #define IEEE_8021QAZ_MAX_TCS	8
10 #define IEEE_8021QAZ_TSA_STRICT		0
11 #define IEEE_8021QAZ_TSA_CB_SHAPER	1
12 #define IEEE_8021QAZ_TSA_ETS		2
13 #define IEEE_8021QAZ_TSA_VENDOR		255
14 struct ieee_ets {
15 	__u8	willing;
16 	__u8	ets_cap;
17 	__u8	cbs;
18 	__u8	tc_tx_bw[IEEE_8021QAZ_MAX_TCS];
19 	__u8	tc_rx_bw[IEEE_8021QAZ_MAX_TCS];
20 	__u8	tc_tsa[IEEE_8021QAZ_MAX_TCS];
21 	__u8	prio_tc[IEEE_8021QAZ_MAX_TCS];
22 	__u8	tc_reco_bw[IEEE_8021QAZ_MAX_TCS];
23 	__u8	tc_reco_tsa[IEEE_8021QAZ_MAX_TCS];
24 	__u8	reco_prio_tc[IEEE_8021QAZ_MAX_TCS];
25 };
26 struct ieee_maxrate {
27 	__u64	tc_maxrate[IEEE_8021QAZ_MAX_TCS];
28 };
29 enum dcbnl_cndd_states {
30 	DCB_CNDD_RESET = 0,
31 	DCB_CNDD_EDGE,
32 	DCB_CNDD_INTERIOR,
33 	DCB_CNDD_INTERIOR_READY,
34 };
35 struct ieee_qcn {
36 	__u8 rpg_enable[IEEE_8021QAZ_MAX_TCS];
37 	__u32 rppp_max_rps[IEEE_8021QAZ_MAX_TCS];
38 	__u32 rpg_time_reset[IEEE_8021QAZ_MAX_TCS];
39 	__u32 rpg_byte_reset[IEEE_8021QAZ_MAX_TCS];
40 	__u32 rpg_threshold[IEEE_8021QAZ_MAX_TCS];
41 	__u32 rpg_max_rate[IEEE_8021QAZ_MAX_TCS];
42 	__u32 rpg_ai_rate[IEEE_8021QAZ_MAX_TCS];
43 	__u32 rpg_hai_rate[IEEE_8021QAZ_MAX_TCS];
44 	__u32 rpg_gd[IEEE_8021QAZ_MAX_TCS];
45 	__u32 rpg_min_dec_fac[IEEE_8021QAZ_MAX_TCS];
46 	__u32 rpg_min_rate[IEEE_8021QAZ_MAX_TCS];
47 	__u32 cndd_state_machine[IEEE_8021QAZ_MAX_TCS];
48 };
49 struct ieee_qcn_stats {
50 	__u64 rppp_rp_centiseconds[IEEE_8021QAZ_MAX_TCS];
51 	__u32 rppp_created_rps[IEEE_8021QAZ_MAX_TCS];
52 };
53 struct ieee_pfc {
54 	__u8	pfc_cap;
55 	__u8	pfc_en;
56 	__u8	mbc;
57 	__u16	delay;
58 	__u64	requests[IEEE_8021QAZ_MAX_TCS];
59 	__u64	indications[IEEE_8021QAZ_MAX_TCS];
60 };
61 #define IEEE_8021Q_MAX_PRIORITIES 8
62 #define DCBX_MAX_BUFFERS  8
63 struct dcbnl_buffer {
64 
65 	__u8    prio2buffer[IEEE_8021Q_MAX_PRIORITIES];
66 
67 	__u32   buffer_size[DCBX_MAX_BUFFERS];
68 	__u32   total_size;
69 };
70 #define CEE_DCBX_MAX_PGS	8
71 #define CEE_DCBX_MAX_PRIO	8
72 struct cee_pg {
73 	__u8    willing;
74 	__u8    error;
75 	__u8    pg_en;
76 	__u8    tcs_supported;
77 	__u8    pg_bw[CEE_DCBX_MAX_PGS];
78 	__u8    prio_pg[CEE_DCBX_MAX_PGS];
79 };
80 struct cee_pfc {
81 	__u8    willing;
82 	__u8    error;
83 	__u8    pfc_en;
84 	__u8    tcs_supported;
85 };
86 #define IEEE_8021QAZ_APP_SEL_ETHERTYPE	1
87 #define IEEE_8021QAZ_APP_SEL_STREAM	2
88 #define IEEE_8021QAZ_APP_SEL_DGRAM	3
89 #define IEEE_8021QAZ_APP_SEL_ANY	4
90 #define IEEE_8021QAZ_APP_SEL_DSCP       5
91 struct dcb_app {
92 	__u8	selector;
93 	__u8	priority;
94 	__u16	protocol;
95 };
96 struct dcb_peer_app_info {
97 	__u8	willing;
98 	__u8	error;
99 };
100 struct dcbmsg {
101 	__u8               dcb_family;
102 	__u8               cmd;
103 	__u16              dcb_pad;
104 };
105 enum dcbnl_commands {
106 	DCB_CMD_UNDEFINED,
107 	DCB_CMD_GSTATE,
108 	DCB_CMD_SSTATE,
109 	DCB_CMD_PGTX_GCFG,
110 	DCB_CMD_PGTX_SCFG,
111 	DCB_CMD_PGRX_GCFG,
112 	DCB_CMD_PGRX_SCFG,
113 	DCB_CMD_PFC_GCFG,
114 	DCB_CMD_PFC_SCFG,
115 	DCB_CMD_SET_ALL,
116 	DCB_CMD_GPERM_HWADDR,
117 	DCB_CMD_GCAP,
118 	DCB_CMD_GNUMTCS,
119 	DCB_CMD_SNUMTCS,
120 	DCB_CMD_PFC_GSTATE,
121 	DCB_CMD_PFC_SSTATE,
122 	DCB_CMD_BCN_GCFG,
123 	DCB_CMD_BCN_SCFG,
124 	DCB_CMD_GAPP,
125 	DCB_CMD_SAPP,
126 	DCB_CMD_IEEE_SET,
127 	DCB_CMD_IEEE_GET,
128 	DCB_CMD_GDCBX,
129 	DCB_CMD_SDCBX,
130 	DCB_CMD_GFEATCFG,
131 	DCB_CMD_SFEATCFG,
132 	DCB_CMD_CEE_GET,
133 	DCB_CMD_IEEE_DEL,
134 	__DCB_CMD_ENUM_MAX,
135 	DCB_CMD_MAX = __DCB_CMD_ENUM_MAX - 1,
136 };
137 enum dcbnl_attrs {
138 	DCB_ATTR_UNDEFINED,
139 	DCB_ATTR_IFNAME,
140 	DCB_ATTR_STATE,
141 	DCB_ATTR_PFC_STATE,
142 	DCB_ATTR_PFC_CFG,
143 	DCB_ATTR_NUM_TC,
144 	DCB_ATTR_PG_CFG,
145 	DCB_ATTR_SET_ALL,
146 	DCB_ATTR_PERM_HWADDR,
147 	DCB_ATTR_CAP,
148 	DCB_ATTR_NUMTCS,
149 	DCB_ATTR_BCN,
150 	DCB_ATTR_APP,
151 
152 	DCB_ATTR_IEEE,
153 	DCB_ATTR_DCBX,
154 	DCB_ATTR_FEATCFG,
155 
156 	DCB_ATTR_CEE,
157 	__DCB_ATTR_ENUM_MAX,
158 	DCB_ATTR_MAX = __DCB_ATTR_ENUM_MAX - 1,
159 };
160 enum ieee_attrs {
161 	DCB_ATTR_IEEE_UNSPEC,
162 	DCB_ATTR_IEEE_ETS,
163 	DCB_ATTR_IEEE_PFC,
164 	DCB_ATTR_IEEE_APP_TABLE,
165 	DCB_ATTR_IEEE_PEER_ETS,
166 	DCB_ATTR_IEEE_PEER_PFC,
167 	DCB_ATTR_IEEE_PEER_APP,
168 	DCB_ATTR_IEEE_MAXRATE,
169 	DCB_ATTR_IEEE_QCN,
170 	DCB_ATTR_IEEE_QCN_STATS,
171 	DCB_ATTR_DCB_BUFFER,
172 	__DCB_ATTR_IEEE_MAX
173 };
174 #define DCB_ATTR_IEEE_MAX (__DCB_ATTR_IEEE_MAX - 1)
175 enum ieee_attrs_app {
176 	DCB_ATTR_IEEE_APP_UNSPEC,
177 	DCB_ATTR_IEEE_APP,
178 	__DCB_ATTR_IEEE_APP_MAX
179 };
180 #define DCB_ATTR_IEEE_APP_MAX (__DCB_ATTR_IEEE_APP_MAX - 1)
181 enum cee_attrs {
182 	DCB_ATTR_CEE_UNSPEC,
183 	DCB_ATTR_CEE_PEER_PG,
184 	DCB_ATTR_CEE_PEER_PFC,
185 	DCB_ATTR_CEE_PEER_APP_TABLE,
186 	DCB_ATTR_CEE_TX_PG,
187 	DCB_ATTR_CEE_RX_PG,
188 	DCB_ATTR_CEE_PFC,
189 	DCB_ATTR_CEE_APP_TABLE,
190 	DCB_ATTR_CEE_FEAT,
191 	__DCB_ATTR_CEE_MAX
192 };
193 #define DCB_ATTR_CEE_MAX (__DCB_ATTR_CEE_MAX - 1)
194 enum peer_app_attr {
195 	DCB_ATTR_CEE_PEER_APP_UNSPEC,
196 	DCB_ATTR_CEE_PEER_APP_INFO,
197 	DCB_ATTR_CEE_PEER_APP,
198 	__DCB_ATTR_CEE_PEER_APP_MAX
199 };
200 #define DCB_ATTR_CEE_PEER_APP_MAX (__DCB_ATTR_CEE_PEER_APP_MAX - 1)
201 enum cee_attrs_app {
202 	DCB_ATTR_CEE_APP_UNSPEC,
203 	DCB_ATTR_CEE_APP,
204 	__DCB_ATTR_CEE_APP_MAX
205 };
206 #define DCB_ATTR_CEE_APP_MAX (__DCB_ATTR_CEE_APP_MAX - 1)
207 enum dcbnl_pfc_up_attrs {
208 	DCB_PFC_UP_ATTR_UNDEFINED,
209 	DCB_PFC_UP_ATTR_0,
210 	DCB_PFC_UP_ATTR_1,
211 	DCB_PFC_UP_ATTR_2,
212 	DCB_PFC_UP_ATTR_3,
213 	DCB_PFC_UP_ATTR_4,
214 	DCB_PFC_UP_ATTR_5,
215 	DCB_PFC_UP_ATTR_6,
216 	DCB_PFC_UP_ATTR_7,
217 	DCB_PFC_UP_ATTR_ALL,
218 	__DCB_PFC_UP_ATTR_ENUM_MAX,
219 	DCB_PFC_UP_ATTR_MAX = __DCB_PFC_UP_ATTR_ENUM_MAX - 1,
220 };
221 enum dcbnl_pg_attrs {
222 	DCB_PG_ATTR_UNDEFINED,
223 	DCB_PG_ATTR_TC_0,
224 	DCB_PG_ATTR_TC_1,
225 	DCB_PG_ATTR_TC_2,
226 	DCB_PG_ATTR_TC_3,
227 	DCB_PG_ATTR_TC_4,
228 	DCB_PG_ATTR_TC_5,
229 	DCB_PG_ATTR_TC_6,
230 	DCB_PG_ATTR_TC_7,
231 	DCB_PG_ATTR_TC_MAX,
232 	DCB_PG_ATTR_TC_ALL,
233 	DCB_PG_ATTR_BW_ID_0,
234 	DCB_PG_ATTR_BW_ID_1,
235 	DCB_PG_ATTR_BW_ID_2,
236 	DCB_PG_ATTR_BW_ID_3,
237 	DCB_PG_ATTR_BW_ID_4,
238 	DCB_PG_ATTR_BW_ID_5,
239 	DCB_PG_ATTR_BW_ID_6,
240 	DCB_PG_ATTR_BW_ID_7,
241 	DCB_PG_ATTR_BW_ID_MAX,
242 	DCB_PG_ATTR_BW_ID_ALL,
243 	__DCB_PG_ATTR_ENUM_MAX,
244 	DCB_PG_ATTR_MAX = __DCB_PG_ATTR_ENUM_MAX - 1,
245 };
246 enum dcbnl_tc_attrs {
247 	DCB_TC_ATTR_PARAM_UNDEFINED,
248 	DCB_TC_ATTR_PARAM_PGID,
249 	DCB_TC_ATTR_PARAM_UP_MAPPING,
250 	DCB_TC_ATTR_PARAM_STRICT_PRIO,
251 	DCB_TC_ATTR_PARAM_BW_PCT,
252 	DCB_TC_ATTR_PARAM_ALL,
253 	__DCB_TC_ATTR_PARAM_ENUM_MAX,
254 	DCB_TC_ATTR_PARAM_MAX = __DCB_TC_ATTR_PARAM_ENUM_MAX - 1,
255 };
256 enum dcbnl_cap_attrs {
257 	DCB_CAP_ATTR_UNDEFINED,
258 	DCB_CAP_ATTR_ALL,
259 	DCB_CAP_ATTR_PG,
260 	DCB_CAP_ATTR_PFC,
261 	DCB_CAP_ATTR_UP2TC,
262 	DCB_CAP_ATTR_PG_TCS,
263 	DCB_CAP_ATTR_PFC_TCS,
264 	DCB_CAP_ATTR_GSP,
265 	DCB_CAP_ATTR_BCN,
266 	DCB_CAP_ATTR_DCBX,
267 	__DCB_CAP_ATTR_ENUM_MAX,
268 	DCB_CAP_ATTR_MAX = __DCB_CAP_ATTR_ENUM_MAX - 1,
269 };
270 #define DCB_CAP_DCBX_HOST		0x01
271 #define DCB_CAP_DCBX_LLD_MANAGED	0x02
272 #define DCB_CAP_DCBX_VER_CEE		0x04
273 #define DCB_CAP_DCBX_VER_IEEE		0x08
274 #define DCB_CAP_DCBX_STATIC		0x10
275 enum dcbnl_numtcs_attrs {
276 	DCB_NUMTCS_ATTR_UNDEFINED,
277 	DCB_NUMTCS_ATTR_ALL,
278 	DCB_NUMTCS_ATTR_PG,
279 	DCB_NUMTCS_ATTR_PFC,
280 	__DCB_NUMTCS_ATTR_ENUM_MAX,
281 	DCB_NUMTCS_ATTR_MAX = __DCB_NUMTCS_ATTR_ENUM_MAX - 1,
282 };
283 enum dcbnl_bcn_attrs{
284 	DCB_BCN_ATTR_UNDEFINED = 0,
285 	DCB_BCN_ATTR_RP_0,
286 	DCB_BCN_ATTR_RP_1,
287 	DCB_BCN_ATTR_RP_2,
288 	DCB_BCN_ATTR_RP_3,
289 	DCB_BCN_ATTR_RP_4,
290 	DCB_BCN_ATTR_RP_5,
291 	DCB_BCN_ATTR_RP_6,
292 	DCB_BCN_ATTR_RP_7,
293 	DCB_BCN_ATTR_RP_ALL,
294 	DCB_BCN_ATTR_BCNA_0,
295 	DCB_BCN_ATTR_BCNA_1,
296 	DCB_BCN_ATTR_ALPHA,
297 	DCB_BCN_ATTR_BETA,
298 	DCB_BCN_ATTR_GD,
299 	DCB_BCN_ATTR_GI,
300 	DCB_BCN_ATTR_TMAX,
301 	DCB_BCN_ATTR_TD,
302 	DCB_BCN_ATTR_RMIN,
303 	DCB_BCN_ATTR_W,
304 	DCB_BCN_ATTR_RD,
305 	DCB_BCN_ATTR_RU,
306 	DCB_BCN_ATTR_WRTT,
307 	DCB_BCN_ATTR_RI,
308 	DCB_BCN_ATTR_C,
309 	DCB_BCN_ATTR_ALL,
310 	__DCB_BCN_ATTR_ENUM_MAX,
311 	DCB_BCN_ATTR_MAX = __DCB_BCN_ATTR_ENUM_MAX - 1,
312 };
313 enum dcb_general_attr_values {
314 	DCB_ATTR_VALUE_UNDEFINED = 0xff
315 };
316 #define DCB_APP_IDTYPE_ETHTYPE	0x00
317 #define DCB_APP_IDTYPE_PORTNUM	0x01
318 enum dcbnl_app_attrs {
319 	DCB_APP_ATTR_UNDEFINED,
320 	DCB_APP_ATTR_IDTYPE,
321 	DCB_APP_ATTR_ID,
322 	DCB_APP_ATTR_PRIORITY,
323 	__DCB_APP_ATTR_ENUM_MAX,
324 	DCB_APP_ATTR_MAX = __DCB_APP_ATTR_ENUM_MAX - 1,
325 };
326 #define DCB_FEATCFG_ERROR	0x01
327 #define DCB_FEATCFG_ENABLE	0x02
328 #define DCB_FEATCFG_WILLING	0x04
329 #define DCB_FEATCFG_ADVERTISE	0x08
330 enum dcbnl_featcfg_attrs {
331 	DCB_FEATCFG_ATTR_UNDEFINED,
332 	DCB_FEATCFG_ATTR_ALL,
333 	DCB_FEATCFG_ATTR_PG,
334 	DCB_FEATCFG_ATTR_PFC,
335 	DCB_FEATCFG_ATTR_APP,
336 	__DCB_FEATCFG_ATTR_ENUM_MAX,
337 	DCB_FEATCFG_ATTR_MAX = __DCB_FEATCFG_ATTR_ENUM_MAX - 1,
338 };
339 #endif
340