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1/*
2 * Copyright (c) 2013-2020, Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this list of
9 *    conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
12 *    of conditions and the following disclaimer in the documentation and/or other materials
13 *    provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
16 *    to endorse or promote products derived from this software without specific prior written
17 *    permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include "soc_common.h"
33
34.global  HalEnableIRQ
35.global  HalDisableIRQ
36.global  ArchIntLock
37.global  ArchIntUnLock
38.global  ArchIntRestore
39.global  HalStartToRun
40.global  HalTaskContextSwitch
41.extern  __irq_stack_top
42.section .interrupt.text
43
44.macro PUSH_ALL_REG
45    addi sp, sp, -(32 * REGBYTES)
46    SREG  t6, 2 * REGBYTES(sp)
47    SREG  t5, 3 * REGBYTES(sp)
48    SREG  t4, 4 * REGBYTES(sp)
49    SREG  t3, 5 * REGBYTES(sp)
50    SREG  t2, 6 * REGBYTES(sp)
51    SREG  t1, 7 * REGBYTES(sp)
52    SREG  t0, 8 * REGBYTES(sp)
53    SREG  s11, 9 * REGBYTES(sp)
54    SREG  s10, 10 * REGBYTES(sp)
55    SREG  s9, 11 * REGBYTES(sp)
56    SREG  s8, 12 * REGBYTES(sp)
57    SREG  s7, 13 * REGBYTES(sp)
58    SREG  s6, 14 * REGBYTES(sp)
59    SREG  s5, 15 * REGBYTES(sp)
60    SREG  a7, 18 * REGBYTES(sp)
61    SREG  a6, 19 * REGBYTES(sp)
62    SREG  a5, 20 * REGBYTES(sp)
63    SREG  a4, 21 * REGBYTES(sp)
64    SREG  a3, 22 * REGBYTES(sp)
65    SREG  a2, 23 * REGBYTES(sp)
66    SREG  a1, 24 * REGBYTES(sp)
67    SREG  a0, 25 * REGBYTES(sp)
68    SREG  s4, 26 * REGBYTES(sp)
69    SREG  s3, 27 * REGBYTES(sp)
70    SREG  s2, 28 * REGBYTES(sp)
71    SREG  s1, 29 * REGBYTES(sp)
72    SREG  s0, 30 * REGBYTES(sp)
73    SREG  ra, 31 * REGBYTES(sp)
74.endm
75
76.macro POP_ALL_REG
77    LREG  t6, 2 * REGBYTES(sp)
78    LREG  t5, 3 * REGBYTES(sp)
79    LREG  t4, 4 * REGBYTES(sp)
80    LREG  t3, 5 * REGBYTES(sp)
81    LREG  t2, 6 * REGBYTES(sp)
82    LREG  t1, 7 * REGBYTES(sp)
83    LREG  t0, 8 * REGBYTES(sp)
84    LREG  s11, 9 * REGBYTES(sp)
85    LREG  s10, 10 * REGBYTES(sp)
86    LREG  s9, 11 * REGBYTES(sp)
87    LREG  s8, 12 * REGBYTES(sp)
88    LREG  s7, 13 * REGBYTES(sp)
89    LREG  s6, 14 * REGBYTES(sp)
90    LREG  s5, 15 * REGBYTES(sp)
91    LREG  a7, 18 * REGBYTES(sp)
92    LREG  a6, 19 * REGBYTES(sp)
93    LREG  a5, 20 * REGBYTES(sp)
94    LREG  a4, 21 * REGBYTES(sp)
95    LREG  a3, 22 * REGBYTES(sp)
96    LREG  a2, 23 * REGBYTES(sp)
97    LREG  a1, 24 * REGBYTES(sp)
98    LREG  a0, 25 * REGBYTES(sp)
99    LREG  s4, 26 * REGBYTES(sp)
100    LREG  s3, 27 * REGBYTES(sp)
101    LREG  s2, 28 * REGBYTES(sp)
102    LREG  s1, 29 * REGBYTES(sp)
103    LREG  s0, 30 * REGBYTES(sp)
104    LREG  ra, 31 * REGBYTES(sp)
105    addi  sp, sp, 32 * REGBYTES
106.endm
107
108HalTaskContextSwitch:
109    PUSH_ALL_REG
110
111    // clear mpie
112    li   a2, RISCV_MSTATUS_MPIE
113    not  a2, a2
114    and  a0, a0, a2
115
116    // get mie
117    andi a1, a0, RISCV_MSTATUS_MIE
118
119    // must be in machine mode
120    ori  a1, a1, 0x180
121    slli a1, a1, 0x4
122    or   a0, a0, a1
123
124    // clear mie
125    li   a2, RISCV_MSTATUS_MIE
126    not  a2, a2
127    and  a0, a0, a2
128
129    SREG a0, 16 * REGBYTES(sp)
130    SREG ra, 17 * REGBYTES(sp)
131
132    la   a1, g_losTask
133    lw   a0, 0(a1)
134    sw   sp, TASK_CB_KERNEL_SP(a0)
135
136    lw   a0, 4(a1)
137    sw   a0, 0(a1)
138
139HalStartToRun:
140    la   a1, g_losTask
141    lw   a0, 4(a1)
142
143// retireve stack pointer
144    lw      sp, TASK_CB_KERNEL_SP(a0)
145
146// enable global interrupts
147    lw      t0, 16 * REGBYTES(sp)
148    csrw    mstatus, t0
149
150// retrieve the address at which exception happened
151    lw      t0, 17 * REGBYTES(sp)
152    csrw    mepc, t0
153
154// retrieve the registers
155    POP_ALL_REG
156
157    mret
158
159.section .text
160HalDisableIRQ:
161    li      t0, (RISCV_MSTATUS_MPIE | RISCV_MSTATUS_MIE) // mpie | mie
162    csrrc   zero, mstatus, t0
163    ret
164
165HalEnableIRQ:
166    csrsi  mstatus, RISCV_MSTATUS_MIE
167    ret
168
169ArchIntLock:
170    csrr    a0, mstatus           // return value
171    li      t0, RISCV_MSTATUS_MIE   // mie
172    csrrc   zero, mstatus, t0
173    ret
174
175ArchIntUnLock:
176    csrr    a0, mstatus           // return value
177    li      t0, RISCV_MSTATUS_MIE   // mie
178    csrrs   zero, mstatus, t0
179    ret
180
181ArchIntRestore:
182    csrw mstatus, a0
183    ret
184