1ENTRY(__text_start) 2 3_stack_size = 0x10000; 4_heap_size = 0x10000; 5 6MEMORY 7{ 8 IMU_SRAM (rwx) : ORIGIN = 0x93000000, LENGTH = 0x800000 9 MMU_MEM (rwx) : ORIGIN = 0x93800000, LENGTH = 0x800000 10} 11 12SECTIONS 13{ 14 text_start = .; 15 .start_bspinit : 16 { 17 __text_start = .; 18 KEEP(*(.text.bspinit)) 19 } > IMU_SRAM 20 21 .start_text : 22 { 23 KEEP(*(.text.startup)) 24 } > IMU_SRAM 25 26 .text : 27 { 28 *(.text) 29 *(.text.*) 30 *(*.text) 31 . = ALIGN(8); 32 __text_end = .; 33 } > IMU_SRAM 34 . = ALIGN(8); 35 data_copy_start = .; 36 37 .rodata : 38 { 39 . = ALIGN(8); 40 __rodata_start = .; 41 *(.rodata) 42 *(.rodata.*) 43 . = ALIGN(8); 44 __rodata_end = .; 45 } > IMU_SRAM 46 47 .eh_frame : 48 { 49 . = ALIGN(8); 50 __os_unwind_table_start = .; 51 *(.eh_frame) 52 __os_unwind_table_end = .; 53 } > IMU_SRAM 54 55 .heap (NOLOAD) : 56 { 57 . = ALIGN(8); 58 PROVIDE (__HEAP_INIT = .); 59 . = . + _heap_size; 60 . = ALIGN(8); 61 PROVIDE (__HEAP_END = .); 62 } > IMU_SRAM 63 64 .stack (NOLOAD) : 65 { 66 . = ALIGN(8); 67 PROVIDE (__os_sys_sp_start = .); 68 . = . + _stack_size; 69 . = ALIGN(8); 70 PROVIDE (__os_sys_sp_end = .); 71 } > IMU_SRAM 72 end = .; 73 74 .percpu.data : 75 { 76 __os_per_cpu_start = .; 77 *(.os.percpu.data) 78 __os_per_cpu_end = .; 79 LONG (ALIGNOF(.percpu.data)) 80 } > IMU_SRAM 81 82 .data : 83 { 84 . = ALIGN(8); 85 __data_start = .; 86 *(.data) 87 *(.data.*) 88 . = ALIGN(8); 89 __os_text_start = .; 90 QUAD(__text_start) 91 QUAD(__text_end) 92 __os_text_end = .; 93 __data_end = .; 94 } > IMU_SRAM 95 96 .llt.bss : 97 { 98 _llt_bss_start = .; 99 *__code_measure_stub*.o(.bss) 100 *__code_measure_stub*.o(.bss.*) 101 _llt_bss_end = .; 102 } > IMU_SRAM 103 104 .bss (NOLOAD) : 105 { 106 . = ALIGN(8); 107 __bss_start__ = .; 108 *(.bss) 109 *(.bss.*) 110 *(COMMON) 111 . = ALIGN(8); 112 __bss_end__ = .; 113 } > IMU_SRAM 114 115 .mmu.table.base : 116 { 117 PROVIDE (g_mmu_page_begin = .); 118 PROVIDE (g_mmu_page_end = g_mmu_page_begin + 0x8000); 119 } > MMU_MEM 120} 121