1@/* 2@ * Copyright (c) 2009-2022 Huawei Technologies Co., Ltd. All rights reserved. 3@ * 4@ * UniProton is licensed under Mulan PSL v2. 5@ * You can use this software according to the terms and conditions of the Mulan PSL v2. 6@ * You may obtain a copy of Mulan PSL v2 at: 7@ * http://license.coscl.org.cn/MulanPSL2 8@ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 9@ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 10@ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 11@ * See the Mulan PSL v2 for more details. 12@ * Create: 2009-12-22 13@ * Description: thread scheduler 14@ */ 15#include "prt_buildef.h" 16 17 .global OsResetVector 18 .global mmu_init 19 20 .type mmu_init, function 21 .type start, function 22 .section .text.bspinit, "ax" 23 .balign 4 24 25#define HCR_EL2_FMO (1 << 3) 26#define HCR_EL2_IMO (1 << 4) 27#define HCR_EL2_AMO (1 << 5) 28#define HCR_EL2_TWI (1 << 13) 29#define HCR_EL2_TWE (1 << 14) 30#define HCR_EL2_TVM (1 << 26) 31#define HCR_EL2_TGE (1 << 27) 32#define HCR_EL2_TDZ (1 << 28) 33#define HCR_EL2_HCD (1 << 29) 34#define HCR_EL2_TRVM (1 << 30) 35#define HCR_EL2_RW (1 << 31) 36 37#define SPSR_DBG_MASK (1 << 9) 38#define SPSR_SERR_MASK (1 << 8) 39#define SPSR_IRQ_MASK (1 << 7) 40#define SPSR_FIQ_MASK (1 << 6) 41#define SPSR_M_AARCH64 (0 << 4) 42#define SPSR_M_AARCH32 (1 << 4) 43#define SPSR_M_EL1H (5) 44#define SPSR_M_EL2H (9) 45 46#define CNTHCTL_EL2_EL1PCEN_EN (1 << 1) 47#define CNTHCTL_EL2_EL1PCTEN_EN (1 << 0) 48#define CPACR_EL1_FPEN_EN (3 << 20) 49 50 .global OsElxState 51 .type OsElxState, @function 52OsElxState: 53 MRS x6, CurrentEL 54 MOV x2, #0x4 55 CMP w6, w2 56 57 BEQ Start 58 59OsEl2Entry: 60 MRS x10, CNTHCTL_EL2 61 ORR x10, x10, #0x3 62 MSR CNTHCTL_EL2, x10 63 64 MRS x10, CNTKCTL_EL1 65 ORR x10, x10, #0x3 66 MSR CNTKCTL_EL1, x10 67 68 MRS x10, MIDR_EL1 69 MRS x1, MPIDR_EL1 70 MSR VPIDR_EL2, x10 71 MSR VMPIDR_EL2, x1 72 73 MOV x10, #0x33ff 74 MSR CPTR_EL2, x10 75 MSR HSTR_EL2, xzr 76 77 MRS x10, CPACR_EL1 78 MOV x10, #3 << 20 79 MSR CPACR_EL1, x10 80 81 MOV x10, #(HCR_EL2_RW) 82 ORR x10, x10, #(HCR_EL2_HCD) 83 BIC x10, x10, #(HCR_EL2_TVM) 84 BIC x10, x10, #(HCR_EL2_TRVM) 85 BIC x10, x10, #(HCR_EL2_TGE) 86 BIC x10, x10, #(HCR_EL2_AMO) 87 BIC x10, x10, #(HCR_EL2_IMO) 88 BIC x10, x10, #(HCR_EL2_FMO) 89 BIC x10, x10, #(HCR_EL2_TWI) 90 BIC x10, x10, #(HCR_EL2_TWE) 91 92 MSR HCR_EL2, x10 93 94OsEl2SwitchToEl1: 95 ADR x0, Start 96 MSR SP_EL1, XZR 97 MSR ELR_EL2, x0 98 MOV x0, XZR 99 100 LDR x20, =(SPSR_DBG_MASK | SPSR_SERR_MASK | \ 101 SPSR_IRQ_MASK | SPSR_FIQ_MASK | SPSR_M_EL1H) 102 MSR SPSR_EL2, x20 103 104 TLBI ALLE1IS 105 IC IALLU 106 DSB SY 107 ISB 108 ERET 109 110Start: 111 LDR x1, =__os_sys_sp_end 112 BIC sp, x1, #0xf 113 114 BL mmu_init 115 B OsResetVector 116 117OsEnterReset: 118 B OsEnterReset 119 120 .section .text, "ax" 121 .balign 4 122