1 // SPDX-License-Identifier: BSD-3-Clause 2 // 3 // Copyright(c) 2021 Intel Corporation. All rights reserved. 4 // 5 // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 6 // Keyon Jie <yang.jie@linux.intel.com> 7 // Rander Wang <rander.wang@linux.intel.com> 8 // Jaska Uimonen <jaska.uimonen@linux.intel.com> 9 10 #ifndef __SSP_MACROS_H 11 #define __SSP_MACROS_H 12 13 #include "ssp-intel.h" 14 15 #define SSP_MAX_DAIS 8 16 #define SSP_MAX_HW_CONFIG 8 17 #define SSP_TDM_MAX_SLOT_MAP_COUNT 8 18 19 struct ssp_aux_config_mn { 20 uint32_t m_div; 21 uint32_t n_div; 22 }; 23 24 struct ssp_aux_config_clk { 25 uint32_t clock_warm_up; 26 uint32_t mclk; 27 uint32_t warm_up_ovr; 28 uint32_t clock_stop_delay; 29 uint32_t keep_running; 30 uint32_t clock_stop_ovr; 31 }; 32 33 struct ssp_aux_config_tr { 34 uint32_t sampling_frequency; 35 uint32_t bit_depth; 36 uint32_t channel_map; 37 uint32_t channel_config; 38 uint32_t interleaving_style; 39 uint32_t number_of_channels; 40 uint32_t valid_bit_depth; 41 uint32_t sample_type; 42 }; 43 44 struct ssp_aux_config_run { 45 uint32_t always_run; 46 }; 47 48 struct ssp_aux_config_node { 49 uint32_t node_id; 50 uint32_t sampling_rate; 51 }; 52 53 struct ssp_aux_config_sync { 54 uint32_t sync_denominator; 55 uint32_t count; 56 struct ssp_aux_config_node nodes[SSP_MAX_DAIS]; 57 }; 58 59 struct ssp_aux_config_ext { 60 uint32_t mclk_policy_override; 61 uint32_t mclk_always_running; 62 uint32_t mclk_starts_on_gtw_init; 63 uint32_t mclk_starts_on_run; 64 uint32_t mclk_starts_on_pause; 65 uint32_t mclk_stops_on_pause; 66 uint32_t mclk_stops_on_reset; 67 uint32_t bclk_policy_override; 68 uint32_t bclk_always_running; 69 uint32_t bclk_starts_on_gtw_init; 70 uint32_t bclk_starts_on_run; 71 uint32_t bclk_starts_on_pause; 72 uint32_t bclk_stops_on_pause; 73 uint32_t bclk_stops_on_reset; 74 uint32_t sync_policy_override; 75 uint32_t sync_always_running; 76 uint32_t sync_starts_on_gtw_init; 77 uint32_t sync_starts_on_run; 78 uint32_t sync_starts_on_pause; 79 uint32_t sync_stops_on_pause; 80 uint32_t sync_stops_on_reset; 81 }; 82 83 struct ssp_aux_config_link { 84 uint32_t clock_source; 85 }; 86 87 struct ssp_config_aux { 88 /* bits set for found aux structs */ 89 uint32_t enabled; 90 struct ssp_aux_config_mn mn; 91 struct ssp_aux_config_clk clk; 92 struct ssp_aux_config_tr tr_start; 93 struct ssp_aux_config_tr tr_stop; 94 struct ssp_aux_config_run run; 95 struct ssp_aux_config_sync sync; 96 struct ssp_aux_config_ext ext; 97 struct ssp_aux_config_link link; 98 }; 99 100 struct ssp_aux_blob { 101 uint32_t size; 102 uint8_t aux_blob[256]; 103 }; 104 105 struct ssp_config_mdivr { 106 uint32_t count; 107 uint32_t mdivrs[8]; 108 }; 109 110 /* structs for gathering the ssp parameters from topology */ 111 struct ssp_config_hw { 112 uint32_t mclk_rate; 113 uint32_t bclk_rate; 114 uint32_t fsync_rate; 115 uint32_t tdm_slots; 116 uint32_t tdm_slot_width; 117 uint32_t tx_slots; 118 uint32_t rx_slots; 119 uint32_t format; 120 }; 121 122 struct ssp_config_dai { 123 uint32_t io_clk; 124 uint32_t dai_index; 125 uint16_t mclk_id; 126 uint32_t sample_valid_bits; 127 uint32_t mclk_direction; 128 uint16_t frame_pulse_width; 129 uint16_t tdm_per_slot_padding_flag; 130 uint32_t clks_control; 131 uint32_t quirks; 132 uint32_t bclk_delay; 133 uint8_t direction; 134 uint32_t version; 135 struct ssp_config_hw hw_cfg[SSP_MAX_HW_CONFIG]; 136 struct ssp_config_aux aux_cfg[SSP_MAX_HW_CONFIG]; 137 struct ssp_config_mdivr mdivr[SSP_MAX_HW_CONFIG]; 138 }; 139 140 struct intel_ssp_params { 141 /* structs to gather ssp params before calculations */ 142 struct ssp_config_dai ssp_prm[SSP_MAX_DAIS]; 143 uint32_t ssp_dai_index[SSP_MAX_DAIS]; 144 uint32_t ssp_hw_config_count[SSP_MAX_DAIS]; 145 int ssp_count; 146 147 /* ssp vendor blob structs */ 148 struct ssp_intel_config_data ssp_blob[SSP_MAX_DAIS][SSP_MAX_HW_CONFIG]; 149 struct ssp_intel_config_data_1_5 ssp_blob_1_5[SSP_MAX_DAIS][SSP_MAX_HW_CONFIG]; 150 struct ssp_aux_blob ssp_blob_ext[SSP_MAX_DAIS][SSP_MAX_HW_CONFIG]; 151 }; 152 153 #define SSP_MN_DIVIDER_CONTROLS 0 154 #define SSP_DMA_CLK_CONTROLS 1 155 #define SSP_DMA_TRANSMISSION_START 2 156 #define SSP_DMA_TRANSMISSION_STOP 3 157 #define SSP_DMA_ALWAYS_RUNNING_MODE 4 158 #define SSP_DMA_SYNC_DATA 5 159 #define SSP_DMA_CLK_CONTROLS_EXT 6 160 #define SSP_LINK_CLK_SOURCE 7 161 /* officially "undefined" node for topology parsing */ 162 #define SSP_DMA_SYNC_NODE 32 163 164 #define SSP_CLOCK_XTAL_OSCILLATOR 0x0 165 #define SSP_CLOCK_AUDIO_CARDINAL 0x1 166 #define SSP_CLOCK_PLL_FIXED 0x2 167 168 #define MCDSS(x) SET_BITS(17, 16, x) 169 #define MNDSS(x) SET_BITS(21, 20, x) 170 171 #define SSP_FMT_I2S 1 /**< I2S mode */ 172 #define SSP_FMT_RIGHT_J 2 /**< Right Justified mode */ 173 #define SSP_FMT_LEFT_J 3 /**< Left Justified mode */ 174 #define SSP_FMT_DSP_A 4 /**< L data MSB after FRM LRC */ 175 #define SSP_FMT_DSP_B 5 /**< L data MSB during FRM LRC */ 176 #define SSP_FMT_PDM 6 /**< Pulse density modulation */ 177 178 #define SSP_FMT_CONT (1 << 4) /**< continuous clock */ 179 #define SSP_FMT_GATED (0 << 4) /**< clock is gated */ 180 181 #define SSP_FMT_NB_NF (0 << 8) /**< normal bit clock + frame */ 182 #define SSP_FMT_NB_IF (2 << 8) /**< normal BCLK + inv FRM */ 183 #define SSP_FMT_IB_NF (3 << 8) /**< invert BCLK + nor FRM */ 184 #define SSP_FMT_IB_IF (4 << 8) /**< invert BCLK + FRM */ 185 186 #define SSP_FMT_CBP_CFP (0 << 12) /**< codec bclk provider & frame provider */ 187 #define SSP_FMT_CBC_CFP (2 << 12) /**< codec bclk consumer & frame provider */ 188 #define SSP_FMT_CBP_CFC (3 << 12) /**< codec bclk provider & frame consumer */ 189 #define SSP_FMT_CBC_CFC (4 << 12) /**< codec bclk consumer & frame consumer */ 190 191 #define SSP_FMT_FORMAT_MASK 0x000f 192 #define SSP_FMT_CLOCK_MASK 0x00f0 193 #define SSP_FMT_INV_MASK 0x0f00 194 #define SSP_FMT_CLOCK_PROVIDER_MASK 0xf000 195 196 /* SSCR0 bits */ 197 #define SSCR0_DSIZE(x) SET_BITS(3, 0, (x) - 1) 198 #define SSCR0_FRF MASK(5, 4) 199 #define SSCR0_MOT SET_BITS(5, 4, 0) 200 #define SSCR0_TI SET_BITS(5, 4, 1) 201 #define SSCR0_NAT SET_BITS(5, 4, 2) 202 #define SSCR0_PSP SET_BITS(5, 4, 3) 203 #define SSCR0_ECS BIT(6) 204 #define SSCR0_SSE BIT(7) 205 #define SSCR0_SCR_MASK MASK(19, 8) 206 #define SSCR0_SCR(x) SET_BITS(19, 8, x) 207 #define SSCR0_EDSS BIT(20) 208 #define SSCR0_NCS BIT(21) 209 #define SSCR0_RIM BIT(22) 210 #define SSCR0_TIM BIT(23) 211 #define SSCR0_FRDC(x) SET_BITS(26, 24, (x) - 1) 212 #define SSCR0_ACS BIT(30) 213 #define SSCR0_MOD BIT(31) 214 215 /* SSCR1 bits */ 216 #define SSCR1_RIE BIT(0) 217 #define SSCR1_TIE BIT(1) 218 #define SSCR1_LBM BIT(2) 219 #define SSCR1_SPO BIT(3) 220 #define SSCR1_SPH BIT(4) 221 #define SSCR1_MWDS BIT(5) 222 #define SSCR1_TFT_MASK MASK(9, 6) 223 #define SSCR1_TFT(x) SET_BITS(9, 6, (x) - 1) 224 #define SSCR1_RFT_MASK MASK(13, 10) 225 #define SSCR1_RFT(x) SET_BITS(13, 10, (x) - 1) 226 #define SSCR1_EFWR BIT(14) 227 #define SSCR1_STRF BIT(15) 228 #define SSCR1_IFS BIT(16) 229 #define SSCR1_PINTE BIT(18) 230 #define SSCR1_TINTE BIT(19) 231 #define SSCR1_RSRE BIT(20) 232 #define SSCR1_TSRE BIT(21) 233 #define SSCR1_TRAIL BIT(22) 234 #define SSCR1_RWOT BIT(23) 235 #define SSCR1_SFRMDIR BIT(24) 236 #define SSCR1_SCLKDIR BIT(25) 237 #define SSCR1_ECRB BIT(26) 238 #define SSCR1_ECRA BIT(27) 239 #define SSCR1_SCFR BIT(28) 240 #define SSCR1_EBCEI BIT(29) 241 #define SSCR1_TTE BIT(30) 242 #define SSCR1_TTELP BIT(31) 243 244 /* SSCR2 bits */ 245 #define SSCR2_URUN_FIX0 BIT(0) 246 #define SSCR2_URUN_FIX1 BIT(1) 247 #define SSCR2_SLV_EXT_CLK_RUN_EN BIT(2) 248 #define SSCR2_CLK_DEL_EN BIT(3) 249 #define SSCR2_UNDRN_FIX_EN BIT(6) 250 #define SSCR2_FIFO_EMPTY_FIX_EN BIT(7) 251 #define SSCR2_ASRC_CNTR_EN BIT(8) 252 #define SSCR2_ASRC_CNTR_CLR BIT(9) 253 #define SSCR2_ASRC_FRM_CNRT_EN BIT(10) 254 #define SSCR2_ASRC_INTR_MASK BIT(11) 255 #define SSCR2_TURM1 BIT(1) 256 #define SSCR2_PSPSRWFDFD BIT(3) 257 #define SSCR2_PSPSTWFDFD BIT(4) 258 #define SSCR2_SDFD BIT(14) 259 #define SSCR2_SDPM BIT(16) 260 #define SSCR2_LJDFD BIT(17) 261 #define SSCR2_MMRATF BIT(18) 262 #define SSCR2_SMTATF BIT(19) 263 264 /* SSR bits */ 265 #define SSSR_TNF BIT(2) 266 #define SSSR_RNE BIT(3) 267 #define SSSR_BSY BIT(4) 268 #define SSSR_TFS BIT(5) 269 #define SSSR_RFS BIT(6) 270 #define SSSR_ROR BIT(7) 271 #define SSSR_TUR BIT(21) 272 273 /* SSPSP bits */ 274 #define SSPSP_SCMODE(x) SET_BITS(1, 0, x) 275 #define SSPSP_SFRMP(x) SET_BIT(2, x) 276 #define SSPSP_ETDS BIT(3) 277 #define SSPSP_STRTDLY(x) SET_BITS(6, 4, x) 278 #define SSPSP_DMYSTRT(x) SET_BITS(8, 7, x) 279 #define SSPSP_SFRMDLY(x) SET_BITS(15, 9, x) 280 #define SSPSP_SFRMWDTH(x) SET_BITS(21, 16, x) 281 #define SSPSP_DMYSTOP(x) SET_BITS(24, 23, x) 282 #define SSPSP_DMYSTOP_BITS 2 283 #define SSPSP_DMYSTOP_MASK MASK(SSPSP_DMYSTOP_BITS - 1, 0) 284 #define SSPSP_FSRT BIT(25) 285 #define SSPSP_EDMYSTOP(x) SET_BITS(28, 26, x) 286 287 #define SSPSP2 0x44 288 #define SSPSP2_FEP_MASK 0xff 289 290 #define SSCR3 0x48 291 #define SSIOC 0x4C 292 #define SSP_REG_MAX SSIOC 293 294 /* SSTSA bits */ 295 #define SSTSA_SSTSA(x) SET_BITS(7, 0, x) 296 #define SSTSA_TXEN BIT(8) 297 298 /* SSRSA bits */ 299 #define SSRSA_SSRSA(x) SET_BITS(7, 0, x) 300 #define SSRSA_RXEN BIT(8) 301 302 /* SSCR3 bits */ 303 #define SSCR3_FRM_MST_EN BIT(0) 304 #define SSCR3_I2S_MODE_EN BIT(1) 305 #define SSCR3_I2S_FRM_POL(x) SET_BIT(2, x) 306 #define SSCR3_I2S_TX_SS_FIX_EN BIT(3) 307 #define SSCR3_I2S_RX_SS_FIX_EN BIT(4) 308 #define SSCR3_I2S_TX_EN BIT(9) 309 #define SSCR3_I2S_RX_EN BIT(10) 310 #define SSCR3_CLK_EDGE_SEL BIT(12) 311 #define SSCR3_STRETCH_TX BIT(14) 312 #define SSCR3_STRETCH_RX BIT(15) 313 #define SSCR3_MST_CLK_EN BIT(16) 314 #define SSCR3_SYN_FIX_EN BIT(17) 315 316 /* SSCR4 bits */ 317 #define SSCR4_TOT_FRM_PRD(x) ((x) << 7) 318 319 /* SSCR5 bits */ 320 #define SSCR5_FRM_ASRT_CLOCKS(x) (((x) - 1) << 1) 321 #define SSCR5_FRM_POLARITY(x) SET_BIT(0, x) 322 323 /* SFIFOTT bits */ 324 #define SFIFOTT_TX(x) ((x) - 1) 325 #define SFIFOTT_RX(x) (((x) - 1) << 16) 326 327 /* SFIFOL bits */ 328 #define SFIFOL_TFL(x) ((x) & 0xFFFF) 329 #define SFIFOL_RFL(x) ((x) >> 16) 330 331 #define SSTSA_TSEN BIT(8) 332 #define SSRSA_RSEN BIT(8) 333 334 #define SSCR3_TFL_MASK MASK(5, 0) 335 #define SSCR3_RFL_MASK MASK(13, 8) 336 #define SSCR3_TFL_VAL(scr3_val) (((scr3_val) >> 0) & MASK(5, 0)) 337 #define SSCR3_RFL_VAL(scr3_val) (((scr3_val) >> 8) & MASK(5, 0)) 338 #define SSCR3_TX(x) SET_BITS(21, 16, (x) - 1) 339 #define SSCR3_RX(x) SET_BITS(29, 24, (x) - 1) 340 341 #define SSIOC_TXDPDEB BIT(1) 342 #define SSIOC_SFCR BIT(4) 343 #define SSIOC_SCOE BIT(5) 344 345 #define MAX_SSP_COUNT 8 346 #define SSP_FIFO_DEPTH 16 347 #define SSP_FIFO_WATERMARK 8 348 349 #define SSP_INTEL_QUIRK_TINTE (1 << 0) 350 #define SSP_INTEL_QUIRK_PINTE (1 << 1) 351 #define SSP_INTEL_QUIRK_SMTATF (1 << 2) 352 #define SSP_INTEL_QUIRK_MMRATF (1 << 3) 353 #define SSP_INTEL_QUIRK_PSPSTWFDFD (1 << 4) 354 #define SSP_INTEL_QUIRK_PSPSRWFDFD (1 << 5) 355 #define SSP_INTEL_QUIRK_LBM (1 << 6) 356 #define SSP_INTEL_QUIRK_BT_SIDEBAND (1 << 7) 357 #define SSP_INTEL_QUIRK_RENDER_FEEDBACK (1 << 8) 358 359 #define SSP_INTEL_FRAME_PULSE_WIDTH_MAX 38 360 #define SSP_INTEL_SLOT_PADDING_MAX 31 361 362 /* SSP clocks control settings */ 363 #define SSP_INTEL_MCLK_0_DISABLE BIT(0) 364 #define SSP_INTEL_MCLK_1_DISABLE BIT(1) 365 #define SSP_INTEL_CLKCTRL_MCLK_KA BIT(2) 366 #define SSP_INTEL_CLKCTRL_BCLK_KA BIT(3) 367 #define SSP_INTEL_CLKCTRL_FS_KA BIT(4) 368 #define SSP_INTEL_CLKCTRL_BCLK_IDLE_HIGH BIT(5) 369 370 #endif /* __SSP_MACROS_H */ 371