1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 /** 25 * \file amdgpu.h 26 * 27 * Declare public libdrm_amdgpu API 28 * 29 * This file define API exposed by libdrm_amdgpu library. 30 * User wanted to use libdrm_amdgpu functionality must include 31 * this file. 32 * 33 */ 34 #ifndef _AMDGPU_H_ 35 #define _AMDGPU_H_ 36 37 #include <stdint.h> 38 #include <stdbool.h> 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 struct drm_amdgpu_info_hw_ip; 45 struct drm_amdgpu_bo_list_entry; 46 47 /*--------------------------------------------------------------------------*/ 48 /* --------------------------- Defines ------------------------------------ */ 49 /*--------------------------------------------------------------------------*/ 50 51 /** 52 * Define max. number of Command Buffers (IB) which could be sent to the single 53 * hardware IP to accommodate CE/DE requirements 54 * 55 * \sa amdgpu_cs_ib_info 56 */ 57 #define AMDGPU_CS_MAX_IBS_PER_SUBMIT 4 58 59 /** 60 * Special timeout value meaning that the timeout is infinite. 61 */ 62 #define AMDGPU_TIMEOUT_INFINITE 0xffffffffffffffffull 63 64 /** 65 * Used in amdgpu_cs_query_fence_status(), meaning that the given timeout 66 * is absolute. 67 */ 68 #define AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE (1 << 0) 69 70 /*--------------------------------------------------------------------------*/ 71 /* ----------------------------- Enums ------------------------------------ */ 72 /*--------------------------------------------------------------------------*/ 73 74 /** 75 * Enum describing possible handle types 76 * 77 * \sa amdgpu_bo_import, amdgpu_bo_export 78 * 79 */ 80 enum amdgpu_bo_handle_type { 81 /** GEM flink name (needs DRM authentication, used by DRI2) */ 82 amdgpu_bo_handle_type_gem_flink_name = 0, 83 84 /** KMS handle which is used by all driver ioctls */ 85 amdgpu_bo_handle_type_kms = 1, 86 87 /** DMA-buf fd handle */ 88 amdgpu_bo_handle_type_dma_buf_fd = 2, 89 90 /** Deprecated in favour of and same behaviour as 91 * amdgpu_bo_handle_type_kms, use that instead of this 92 */ 93 amdgpu_bo_handle_type_kms_noimport = 3, 94 }; 95 96 /** Define known types of GPU VM VA ranges */ 97 enum amdgpu_gpu_va_range 98 { 99 /** Allocate from "normal"/general range */ 100 amdgpu_gpu_va_range_general = 0 101 }; 102 103 enum amdgpu_sw_info { 104 amdgpu_sw_info_address32_hi = 0, 105 }; 106 107 /*--------------------------------------------------------------------------*/ 108 /* -------------------------- Datatypes ----------------------------------- */ 109 /*--------------------------------------------------------------------------*/ 110 111 /** 112 * Define opaque pointer to context associated with fd. 113 * This context will be returned as the result of 114 * "initialize" function and should be pass as the first 115 * parameter to any API call 116 */ 117 typedef struct amdgpu_device *amdgpu_device_handle; 118 119 /** 120 * Define GPU Context type as pointer to opaque structure 121 * Example of GPU Context is the "rendering" context associated 122 * with OpenGL context (glCreateContext) 123 */ 124 typedef struct amdgpu_context *amdgpu_context_handle; 125 126 /** 127 * Define handle for amdgpu resources: buffer, GDS, etc. 128 */ 129 typedef struct amdgpu_bo *amdgpu_bo_handle; 130 131 /** 132 * Define handle for list of BOs 133 */ 134 typedef struct amdgpu_bo_list *amdgpu_bo_list_handle; 135 136 /** 137 * Define handle to be used to work with VA allocated ranges 138 */ 139 typedef struct amdgpu_va *amdgpu_va_handle; 140 141 /** 142 * Define handle for semaphore 143 */ 144 typedef struct amdgpu_semaphore *amdgpu_semaphore_handle; 145 146 /*--------------------------------------------------------------------------*/ 147 /* -------------------------- Structures ---------------------------------- */ 148 /*--------------------------------------------------------------------------*/ 149 150 /** 151 * Structure describing memory allocation request 152 * 153 * \sa amdgpu_bo_alloc() 154 * 155 */ 156 struct amdgpu_bo_alloc_request { 157 /** Allocation request. It must be aligned correctly. */ 158 uint64_t alloc_size; 159 160 /** 161 * It may be required to have some specific alignment requirements 162 * for physical back-up storage (e.g. for displayable surface). 163 * If 0 there is no special alignment requirement 164 */ 165 uint64_t phys_alignment; 166 167 /** 168 * UMD should specify where to allocate memory and how it 169 * will be accessed by the CPU. 170 */ 171 uint32_t preferred_heap; 172 173 /** Additional flags passed on allocation */ 174 uint64_t flags; 175 }; 176 177 /** 178 * Special UMD specific information associated with buffer. 179 * 180 * It may be need to pass some buffer charactersitic as part 181 * of buffer sharing. Such information are defined UMD and 182 * opaque for libdrm_amdgpu as well for kernel driver. 183 * 184 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info, 185 * amdgpu_bo_import(), amdgpu_bo_export 186 * 187 */ 188 struct amdgpu_bo_metadata { 189 /** Special flag associated with surface */ 190 uint64_t flags; 191 192 /** 193 * ASIC-specific tiling information (also used by DCE). 194 * The encoding is defined by the AMDGPU_TILING_* definitions. 195 */ 196 uint64_t tiling_info; 197 198 /** Size of metadata associated with the buffer, in bytes. */ 199 uint32_t size_metadata; 200 201 /** UMD specific metadata. Opaque for kernel */ 202 uint32_t umd_metadata[64]; 203 }; 204 205 /** 206 * Structure describing allocated buffer. Client may need 207 * to query such information as part of 'sharing' buffers mechanism 208 * 209 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info(), 210 * amdgpu_bo_import(), amdgpu_bo_export() 211 */ 212 struct amdgpu_bo_info { 213 /** Allocated memory size */ 214 uint64_t alloc_size; 215 216 /** 217 * It may be required to have some specific alignment requirements 218 * for physical back-up storage. 219 */ 220 uint64_t phys_alignment; 221 222 /** Heap where to allocate memory. */ 223 uint32_t preferred_heap; 224 225 /** Additional allocation flags. */ 226 uint64_t alloc_flags; 227 228 /** Metadata associated with buffer if any. */ 229 struct amdgpu_bo_metadata metadata; 230 }; 231 232 /** 233 * Structure with information about "imported" buffer 234 * 235 * \sa amdgpu_bo_import() 236 * 237 */ 238 struct amdgpu_bo_import_result { 239 /** Handle of memory/buffer to use */ 240 amdgpu_bo_handle buf_handle; 241 242 /** Buffer size */ 243 uint64_t alloc_size; 244 }; 245 246 /** 247 * 248 * Structure to describe GDS partitioning information. 249 * \note OA and GWS resources are asscoiated with GDS partition 250 * 251 * \sa amdgpu_gpu_resource_query_gds_info 252 * 253 */ 254 struct amdgpu_gds_resource_info { 255 uint32_t gds_gfx_partition_size; 256 uint32_t compute_partition_size; 257 uint32_t gds_total_size; 258 uint32_t gws_per_gfx_partition; 259 uint32_t gws_per_compute_partition; 260 uint32_t oa_per_gfx_partition; 261 uint32_t oa_per_compute_partition; 262 }; 263 264 /** 265 * Structure describing CS fence 266 * 267 * \sa amdgpu_cs_query_fence_status(), amdgpu_cs_request, amdgpu_cs_submit() 268 * 269 */ 270 struct amdgpu_cs_fence { 271 272 /** In which context IB was sent to execution */ 273 amdgpu_context_handle context; 274 275 /** To which HW IP type the fence belongs */ 276 uint32_t ip_type; 277 278 /** IP instance index if there are several IPs of the same type. */ 279 uint32_t ip_instance; 280 281 /** Ring index of the HW IP */ 282 uint32_t ring; 283 284 /** Specify fence for which we need to check submission status.*/ 285 uint64_t fence; 286 }; 287 288 /** 289 * Structure describing IB 290 * 291 * \sa amdgpu_cs_request, amdgpu_cs_submit() 292 * 293 */ 294 struct amdgpu_cs_ib_info { 295 /** Special flags */ 296 uint64_t flags; 297 298 /** Virtual MC address of the command buffer */ 299 uint64_t ib_mc_address; 300 301 /** 302 * Size of Command Buffer to be submitted. 303 * - The size is in units of dwords (4 bytes). 304 * - Could be 0 305 */ 306 uint32_t size; 307 }; 308 309 /** 310 * Structure describing fence information 311 * 312 * \sa amdgpu_cs_request, amdgpu_cs_query_fence, 313 * amdgpu_cs_submit(), amdgpu_cs_query_fence_status() 314 */ 315 struct amdgpu_cs_fence_info { 316 /** buffer object for the fence */ 317 amdgpu_bo_handle handle; 318 319 /** fence offset in the unit of sizeof(uint64_t) */ 320 uint64_t offset; 321 }; 322 323 /** 324 * Structure describing submission request 325 * 326 * \note We could have several IBs as packet. e.g. CE, CE, DE case for gfx 327 * 328 * \sa amdgpu_cs_submit() 329 */ 330 struct amdgpu_cs_request { 331 /** Specify flags with additional information */ 332 uint64_t flags; 333 334 /** Specify HW IP block type to which to send the IB. */ 335 unsigned ip_type; 336 337 /** IP instance index if there are several IPs of the same type. */ 338 unsigned ip_instance; 339 340 /** 341 * Specify ring index of the IP. We could have several rings 342 * in the same IP. E.g. 0 for SDMA0 and 1 for SDMA1. 343 */ 344 uint32_t ring; 345 346 /** 347 * List handle with resources used by this request. 348 */ 349 amdgpu_bo_list_handle resources; 350 351 /** 352 * Number of dependencies this Command submission needs to 353 * wait for before starting execution. 354 */ 355 uint32_t number_of_dependencies; 356 357 /** 358 * Array of dependencies which need to be met before 359 * execution can start. 360 */ 361 struct amdgpu_cs_fence *dependencies; 362 363 /** Number of IBs to submit in the field ibs. */ 364 uint32_t number_of_ibs; 365 366 /** 367 * IBs to submit. Those IBs will be submit together as single entity 368 */ 369 struct amdgpu_cs_ib_info *ibs; 370 371 /** 372 * The returned sequence number for the command submission 373 */ 374 uint64_t seq_no; 375 376 /** 377 * The fence information 378 */ 379 struct amdgpu_cs_fence_info fence_info; 380 }; 381 382 /** 383 * Structure which provide information about GPU VM MC Address space 384 * alignments requirements 385 * 386 * \sa amdgpu_query_buffer_size_alignment 387 */ 388 struct amdgpu_buffer_size_alignments { 389 /** Size alignment requirement for allocation in 390 * local memory */ 391 uint64_t size_local; 392 393 /** 394 * Size alignment requirement for allocation in remote memory 395 */ 396 uint64_t size_remote; 397 }; 398 399 /** 400 * Structure which provide information about heap 401 * 402 * \sa amdgpu_query_heap_info() 403 * 404 */ 405 struct amdgpu_heap_info { 406 /** Theoretical max. available memory in the given heap */ 407 uint64_t heap_size; 408 409 /** 410 * Number of bytes allocated in the heap. This includes all processes 411 * and private allocations in the kernel. It changes when new buffers 412 * are allocated, freed, and moved. It cannot be larger than 413 * heap_size. 414 */ 415 uint64_t heap_usage; 416 417 /** 418 * Theoretical possible max. size of buffer which 419 * could be allocated in the given heap 420 */ 421 uint64_t max_allocation; 422 }; 423 424 /** 425 * Describe GPU h/w info needed for UMD correct initialization 426 * 427 * \sa amdgpu_query_gpu_info() 428 */ 429 struct amdgpu_gpu_info { 430 /** Asic id */ 431 uint32_t asic_id; 432 /** Chip revision */ 433 uint32_t chip_rev; 434 /** Chip external revision */ 435 uint32_t chip_external_rev; 436 /** Family ID */ 437 uint32_t family_id; 438 /** Special flags */ 439 uint64_t ids_flags; 440 /** max engine clock*/ 441 uint64_t max_engine_clk; 442 /** max memory clock */ 443 uint64_t max_memory_clk; 444 /** number of shader engines */ 445 uint32_t num_shader_engines; 446 /** number of shader arrays per engine */ 447 uint32_t num_shader_arrays_per_engine; 448 /** Number of available good shader pipes */ 449 uint32_t avail_quad_shader_pipes; 450 /** Max. number of shader pipes.(including good and bad pipes */ 451 uint32_t max_quad_shader_pipes; 452 /** Number of parameter cache entries per shader quad pipe */ 453 uint32_t cache_entries_per_quad_pipe; 454 /** Number of available graphics context */ 455 uint32_t num_hw_gfx_contexts; 456 /** Number of render backend pipes */ 457 uint32_t rb_pipes; 458 /** Enabled render backend pipe mask */ 459 uint32_t enabled_rb_pipes_mask; 460 /** Frequency of GPU Counter */ 461 uint32_t gpu_counter_freq; 462 /** CC_RB_BACKEND_DISABLE.BACKEND_DISABLE per SE */ 463 uint32_t backend_disable[4]; 464 /** Value of MC_ARB_RAMCFG register*/ 465 uint32_t mc_arb_ramcfg; 466 /** Value of GB_ADDR_CONFIG */ 467 uint32_t gb_addr_cfg; 468 /** Values of the GB_TILE_MODE0..31 registers */ 469 uint32_t gb_tile_mode[32]; 470 /** Values of GB_MACROTILE_MODE0..15 registers */ 471 uint32_t gb_macro_tile_mode[16]; 472 /** Value of PA_SC_RASTER_CONFIG register per SE */ 473 uint32_t pa_sc_raster_cfg[4]; 474 /** Value of PA_SC_RASTER_CONFIG_1 register per SE */ 475 uint32_t pa_sc_raster_cfg1[4]; 476 /* CU info */ 477 uint32_t cu_active_number; 478 uint32_t cu_ao_mask; 479 uint32_t cu_bitmap[4][4]; 480 /* video memory type info*/ 481 uint32_t vram_type; 482 /* video memory bit width*/ 483 uint32_t vram_bit_width; 484 /** constant engine ram size*/ 485 uint32_t ce_ram_size; 486 /* vce harvesting instance */ 487 uint32_t vce_harvest_config; 488 /* PCI revision ID */ 489 uint32_t pci_rev_id; 490 }; 491 492 493 /*--------------------------------------------------------------------------*/ 494 /*------------------------- Functions --------------------------------------*/ 495 /*--------------------------------------------------------------------------*/ 496 497 /* 498 * Initialization / Cleanup 499 * 500 */ 501 502 /** 503 * 504 * \param fd - \c [in] File descriptor for AMD GPU device 505 * received previously as the result of 506 * e.g. drmOpen() call. 507 * For legacy fd type, the DRI2/DRI3 508 * authentication should be done before 509 * calling this function. 510 * \param major_version - \c [out] Major version of library. It is assumed 511 * that adding new functionality will cause 512 * increase in major version 513 * \param minor_version - \c [out] Minor version of library 514 * \param device_handle - \c [out] Pointer to opaque context which should 515 * be passed as the first parameter on each 516 * API call 517 * 518 * 519 * \return 0 on success\n 520 * <0 - Negative POSIX Error code 521 * 522 * 523 * \sa amdgpu_device_deinitialize() 524 */ 525 int amdgpu_device_initialize(int fd, 526 uint32_t *major_version, 527 uint32_t *minor_version, 528 amdgpu_device_handle *device_handle); 529 530 /** 531 * 532 * When access to such library does not needed any more the special 533 * function must be call giving opportunity to clean up any 534 * resources if needed. 535 * 536 * \param device_handle - \c [in] Context associated with file 537 * descriptor for AMD GPU device 538 * received previously as the 539 * result e.g. of drmOpen() call. 540 * 541 * \return 0 on success\n 542 * <0 - Negative POSIX Error code 543 * 544 * \sa amdgpu_device_initialize() 545 * 546 */ 547 int amdgpu_device_deinitialize(amdgpu_device_handle device_handle); 548 549 /** 550 * 551 * /param device_handle - \c [in] Device handle. 552 * See #amdgpu_device_initialize() 553 * 554 * \return Returns the drm fd used for operations on this 555 * device. This is still owned by the library and hence 556 * should not be closed. Guaranteed to be valid until 557 * #amdgpu_device_deinitialize gets called. 558 * 559 */ 560 int amdgpu_device_get_fd(amdgpu_device_handle device_handle); 561 562 /* 563 * Memory Management 564 * 565 */ 566 567 /** 568 * Allocate memory to be used by UMD for GPU related operations 569 * 570 * \param dev - \c [in] Device handle. 571 * See #amdgpu_device_initialize() 572 * \param alloc_buffer - \c [in] Pointer to the structure describing an 573 * allocation request 574 * \param buf_handle - \c [out] Allocated buffer handle 575 * 576 * \return 0 on success\n 577 * <0 - Negative POSIX Error code 578 * 579 * \sa amdgpu_bo_free() 580 */ 581 int amdgpu_bo_alloc(amdgpu_device_handle dev, 582 struct amdgpu_bo_alloc_request *alloc_buffer, 583 amdgpu_bo_handle *buf_handle); 584 585 /** 586 * Associate opaque data with buffer to be queried by another UMD 587 * 588 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 589 * \param buf_handle - \c [in] Buffer handle 590 * \param info - \c [in] Metadata to associated with buffer 591 * 592 * \return 0 on success\n 593 * <0 - Negative POSIX Error code 594 */ 595 int amdgpu_bo_set_metadata(amdgpu_bo_handle buf_handle, 596 struct amdgpu_bo_metadata *info); 597 598 /** 599 * Query buffer information including metadata previusly associated with 600 * buffer. 601 * 602 * \param dev - \c [in] Device handle. 603 * See #amdgpu_device_initialize() 604 * \param buf_handle - \c [in] Buffer handle 605 * \param info - \c [out] Structure describing buffer 606 * 607 * \return 0 on success\n 608 * <0 - Negative POSIX Error code 609 * 610 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc() 611 */ 612 int amdgpu_bo_query_info(amdgpu_bo_handle buf_handle, 613 struct amdgpu_bo_info *info); 614 615 /** 616 * Allow others to get access to buffer 617 * 618 * \param dev - \c [in] Device handle. 619 * See #amdgpu_device_initialize() 620 * \param buf_handle - \c [in] Buffer handle 621 * \param type - \c [in] Type of handle requested 622 * \param shared_handle - \c [out] Special "shared" handle 623 * 624 * \return 0 on success\n 625 * <0 - Negative POSIX Error code 626 * 627 * \sa amdgpu_bo_import() 628 * 629 */ 630 int amdgpu_bo_export(amdgpu_bo_handle buf_handle, 631 enum amdgpu_bo_handle_type type, 632 uint32_t *shared_handle); 633 634 /** 635 * Request access to "shared" buffer 636 * 637 * \param dev - \c [in] Device handle. 638 * See #amdgpu_device_initialize() 639 * \param type - \c [in] Type of handle requested 640 * \param shared_handle - \c [in] Shared handle received as result "import" 641 * operation 642 * \param output - \c [out] Pointer to structure with information 643 * about imported buffer 644 * 645 * \return 0 on success\n 646 * <0 - Negative POSIX Error code 647 * 648 * \note Buffer must be "imported" only using new "fd" (different from 649 * one used by "exporter"). 650 * 651 * \sa amdgpu_bo_export() 652 * 653 */ 654 int amdgpu_bo_import(amdgpu_device_handle dev, 655 enum amdgpu_bo_handle_type type, 656 uint32_t shared_handle, 657 struct amdgpu_bo_import_result *output); 658 659 /** 660 * Request GPU access to user allocated memory e.g. via "malloc" 661 * 662 * \param dev - [in] Device handle. See #amdgpu_device_initialize() 663 * \param cpu - [in] CPU address of user allocated memory which we 664 * want to map to GPU address space (make GPU accessible) 665 * (This address must be correctly aligned). 666 * \param size - [in] Size of allocation (must be correctly aligned) 667 * \param buf_handle - [out] Buffer handle for the userptr memory 668 * resource on submission and be used in other operations. 669 * 670 * 671 * \return 0 on success\n 672 * <0 - Negative POSIX Error code 673 * 674 * \note 675 * This call doesn't guarantee that such memory will be persistently 676 * "locked" / make non-pageable. The purpose of this call is to provide 677 * opportunity for GPU get access to this resource during submission. 678 * 679 * The maximum amount of memory which could be mapped in this call depends 680 * if overcommit is disabled or not. If overcommit is disabled than the max. 681 * amount of memory to be pinned will be limited by left "free" size in total 682 * amount of memory which could be locked simultaneously ("GART" size). 683 * 684 * Supported (theoretical) max. size of mapping is restricted only by 685 * "GART" size. 686 * 687 * It is responsibility of caller to correctly specify access rights 688 * on VA assignment. 689 */ 690 int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, 691 void *cpu, uint64_t size, 692 amdgpu_bo_handle *buf_handle); 693 694 /** 695 * Validate if the user memory comes from BO 696 * 697 * \param dev - [in] Device handle. See #amdgpu_device_initialize() 698 * \param cpu - [in] CPU address of user allocated memory which we 699 * want to map to GPU address space (make GPU accessible) 700 * (This address must be correctly aligned). 701 * \param size - [in] Size of allocation (must be correctly aligned) 702 * \param buf_handle - [out] Buffer handle for the userptr memory 703 * if the user memory is not from BO, the buf_handle will be NULL. 704 * \param offset_in_bo - [out] offset in this BO for this user memory 705 * 706 * 707 * \return 0 on success\n 708 * <0 - Negative POSIX Error code 709 * 710 */ 711 int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, 712 void *cpu, 713 uint64_t size, 714 amdgpu_bo_handle *buf_handle, 715 uint64_t *offset_in_bo); 716 717 /** 718 * Free previously allocated memory 719 * 720 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 721 * \param buf_handle - \c [in] Buffer handle to free 722 * 723 * \return 0 on success\n 724 * <0 - Negative POSIX Error code 725 * 726 * \note In the case of memory shared between different applications all 727 * resources will be “physically” freed only all such applications 728 * will be terminated 729 * \note If is UMD responsibility to ‘free’ buffer only when there is no 730 * more GPU access 731 * 732 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc() 733 * 734 */ 735 int amdgpu_bo_free(amdgpu_bo_handle buf_handle); 736 737 /** 738 * Increase the reference count of a buffer object 739 * 740 * \param bo - \c [in] Buffer object handle to increase the reference count 741 * 742 * \sa amdgpu_bo_alloc(), amdgpu_bo_free() 743 * 744 */ 745 void amdgpu_bo_inc_ref(amdgpu_bo_handle bo); 746 747 /** 748 * Request CPU access to GPU accessible memory 749 * 750 * \param buf_handle - \c [in] Buffer handle 751 * \param cpu - \c [out] CPU address to be used for access 752 * 753 * \return 0 on success\n 754 * <0 - Negative POSIX Error code 755 * 756 * \sa amdgpu_bo_cpu_unmap() 757 * 758 */ 759 int amdgpu_bo_cpu_map(amdgpu_bo_handle buf_handle, void **cpu); 760 761 /** 762 * Release CPU access to GPU memory 763 * 764 * \param buf_handle - \c [in] Buffer handle 765 * 766 * \return 0 on success\n 767 * <0 - Negative POSIX Error code 768 * 769 * \sa amdgpu_bo_cpu_map() 770 * 771 */ 772 int amdgpu_bo_cpu_unmap(amdgpu_bo_handle buf_handle); 773 774 /** 775 * Wait until a buffer is not used by the device. 776 * 777 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 778 * \param buf_handle - \c [in] Buffer handle. 779 * \param timeout_ns - Timeout in nanoseconds. 780 * \param buffer_busy - 0 if buffer is idle, all GPU access was completed 781 * and no GPU access is scheduled. 782 * 1 GPU access is in fly or scheduled 783 * 784 * \return 0 - on success 785 * <0 - Negative POSIX Error code 786 */ 787 int amdgpu_bo_wait_for_idle(amdgpu_bo_handle buf_handle, 788 uint64_t timeout_ns, 789 bool *buffer_busy); 790 791 /** 792 * Creates a BO list handle for command submission. 793 * 794 * \param dev - \c [in] Device handle. 795 * See #amdgpu_device_initialize() 796 * \param number_of_buffers - \c [in] Number of BOs in the list 797 * \param buffers - \c [in] List of BO handles 798 * \param result - \c [out] Created BO list handle 799 * 800 * \return 0 on success\n 801 * <0 - Negative POSIX Error code 802 * 803 * \sa amdgpu_bo_list_destroy_raw(), amdgpu_cs_submit_raw2() 804 */ 805 int amdgpu_bo_list_create_raw(amdgpu_device_handle dev, 806 uint32_t number_of_buffers, 807 struct drm_amdgpu_bo_list_entry *buffers, 808 uint32_t *result); 809 810 /** 811 * Destroys a BO list handle. 812 * 813 * \param bo_list - \c [in] BO list handle. 814 * 815 * \return 0 on success\n 816 * <0 - Negative POSIX Error code 817 * 818 * \sa amdgpu_bo_list_create_raw(), amdgpu_cs_submit_raw2() 819 */ 820 int amdgpu_bo_list_destroy_raw(amdgpu_device_handle dev, uint32_t bo_list); 821 822 /** 823 * Creates a BO list handle for command submission. 824 * 825 * \param dev - \c [in] Device handle. 826 * See #amdgpu_device_initialize() 827 * \param number_of_resources - \c [in] Number of BOs in the list 828 * \param resources - \c [in] List of BO handles 829 * \param resource_prios - \c [in] Optional priority for each handle 830 * \param result - \c [out] Created BO list handle 831 * 832 * \return 0 on success\n 833 * <0 - Negative POSIX Error code 834 * 835 * \sa amdgpu_bo_list_destroy() 836 */ 837 int amdgpu_bo_list_create(amdgpu_device_handle dev, 838 uint32_t number_of_resources, 839 amdgpu_bo_handle *resources, 840 uint8_t *resource_prios, 841 amdgpu_bo_list_handle *result); 842 843 /** 844 * Destroys a BO list handle. 845 * 846 * \param handle - \c [in] BO list handle. 847 * 848 * \return 0 on success\n 849 * <0 - Negative POSIX Error code 850 * 851 * \sa amdgpu_bo_list_create() 852 */ 853 int amdgpu_bo_list_destroy(amdgpu_bo_list_handle handle); 854 855 /** 856 * Update resources for existing BO list 857 * 858 * \param handle - \c [in] BO list handle 859 * \param number_of_resources - \c [in] Number of BOs in the list 860 * \param resources - \c [in] List of BO handles 861 * \param resource_prios - \c [in] Optional priority for each handle 862 * 863 * \return 0 on success\n 864 * <0 - Negative POSIX Error code 865 * 866 * \sa amdgpu_bo_list_update() 867 */ 868 int amdgpu_bo_list_update(amdgpu_bo_list_handle handle, 869 uint32_t number_of_resources, 870 amdgpu_bo_handle *resources, 871 uint8_t *resource_prios); 872 873 /* 874 * GPU Execution context 875 * 876 */ 877 878 /** 879 * Create GPU execution Context 880 * 881 * For the purpose of GPU Scheduler and GPU Robustness extensions it is 882 * necessary to have information/identify rendering/compute contexts. 883 * It also may be needed to associate some specific requirements with such 884 * contexts. Kernel driver will guarantee that submission from the same 885 * context will always be executed in order (first come, first serve). 886 * 887 * 888 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 889 * \param priority - \c [in] Context creation flags. See AMDGPU_CTX_PRIORITY_* 890 * \param context - \c [out] GPU Context handle 891 * 892 * \return 0 on success\n 893 * <0 - Negative POSIX Error code 894 * 895 * \sa amdgpu_cs_ctx_free() 896 * 897 */ 898 int amdgpu_cs_ctx_create2(amdgpu_device_handle dev, 899 uint32_t priority, 900 amdgpu_context_handle *context); 901 /** 902 * Create GPU execution Context 903 * 904 * Refer to amdgpu_cs_ctx_create2 for full documentation. This call 905 * is missing the priority parameter. 906 * 907 * \sa amdgpu_cs_ctx_create2() 908 * 909 */ 910 int amdgpu_cs_ctx_create(amdgpu_device_handle dev, 911 amdgpu_context_handle *context); 912 913 /** 914 * 915 * Destroy GPU execution context when not needed any more 916 * 917 * \param context - \c [in] GPU Context handle 918 * 919 * \return 0 on success\n 920 * <0 - Negative POSIX Error code 921 * 922 * \sa amdgpu_cs_ctx_create() 923 * 924 */ 925 int amdgpu_cs_ctx_free(amdgpu_context_handle context); 926 927 /** 928 * Override the submission priority for the given context using a master fd. 929 * 930 * \param dev - \c [in] device handle 931 * \param context - \c [in] context handle for context id 932 * \param master_fd - \c [in] The master fd to authorize the override. 933 * \param priority - \c [in] The priority to assign to the context. 934 * 935 * \return 0 on success or a a negative Posix error code on failure. 936 */ 937 int amdgpu_cs_ctx_override_priority(amdgpu_device_handle dev, 938 amdgpu_context_handle context, 939 int master_fd, 940 unsigned priority); 941 942 /** 943 * Set or query the stable power state for GPU profiling. 944 * 945 * \param dev - \c [in] device handle 946 * \param op - \c [in] AMDGPU_CTX_OP_{GET,SET}_STABLE_PSTATE 947 * \param flags - \c [in] AMDGPU_CTX_STABLE_PSTATE_* 948 * \param out_flags - \c [out] output current stable pstate 949 * 950 * \return 0 on success otherwise POSIX Error code. 951 */ 952 int amdgpu_cs_ctx_stable_pstate(amdgpu_context_handle context, 953 uint32_t op, 954 uint32_t flags, 955 uint32_t *out_flags); 956 957 /** 958 * Query reset state for the specific GPU Context 959 * 960 * \param context - \c [in] GPU Context handle 961 * \param state - \c [out] One of AMDGPU_CTX_*_RESET 962 * \param hangs - \c [out] Number of hangs caused by the context. 963 * 964 * \return 0 on success\n 965 * <0 - Negative POSIX Error code 966 * 967 * \sa amdgpu_cs_ctx_create() 968 * 969 */ 970 int amdgpu_cs_query_reset_state(amdgpu_context_handle context, 971 uint32_t *state, uint32_t *hangs); 972 973 /** 974 * Query reset state for the specific GPU Context. 975 * 976 * \param context - \c [in] GPU Context handle 977 * \param flags - \c [out] A combination of AMDGPU_CTX_QUERY2_FLAGS_* 978 * 979 * \return 0 on success\n 980 * <0 - Negative POSIX Error code 981 * 982 * \sa amdgpu_cs_ctx_create() 983 * 984 */ 985 int amdgpu_cs_query_reset_state2(amdgpu_context_handle context, 986 uint64_t *flags); 987 988 /* 989 * Command Buffers Management 990 * 991 */ 992 993 /** 994 * Send request to submit command buffers to hardware. 995 * 996 * Kernel driver could use GPU Scheduler to make decision when physically 997 * sent this request to the hardware. Accordingly this request could be put 998 * in queue and sent for execution later. The only guarantee is that request 999 * from the same GPU context to the same ip:ip_instance:ring will be executed in 1000 * order. 1001 * 1002 * The caller can specify the user fence buffer/location with the fence_info in the 1003 * cs_request.The sequence number is returned via the 'seq_no' parameter 1004 * in ibs_request structure. 1005 * 1006 * 1007 * \param dev - \c [in] Device handle. 1008 * See #amdgpu_device_initialize() 1009 * \param context - \c [in] GPU Context 1010 * \param flags - \c [in] Global submission flags 1011 * \param ibs_request - \c [in/out] Pointer to submission requests. 1012 * We could submit to the several 1013 * engines/rings simulteniously as 1014 * 'atomic' operation 1015 * \param number_of_requests - \c [in] Number of submission requests 1016 * 1017 * \return 0 on success\n 1018 * <0 - Negative POSIX Error code 1019 * 1020 * \note It is required to pass correct resource list with buffer handles 1021 * which will be accessible by command buffers from submission 1022 * This will allow kernel driver to correctly implement "paging". 1023 * Failure to do so will have unpredictable results. 1024 * 1025 * \sa amdgpu_command_buffer_alloc(), amdgpu_command_buffer_free(), 1026 * amdgpu_cs_query_fence_status() 1027 * 1028 */ 1029 int amdgpu_cs_submit(amdgpu_context_handle context, 1030 uint64_t flags, 1031 struct amdgpu_cs_request *ibs_request, 1032 uint32_t number_of_requests); 1033 1034 /** 1035 * Query status of Command Buffer Submission 1036 * 1037 * \param fence - \c [in] Structure describing fence to query 1038 * \param timeout_ns - \c [in] Timeout value to wait 1039 * \param flags - \c [in] Flags for the query 1040 * \param expired - \c [out] If fence expired or not.\n 1041 * 0 – if fence is not expired\n 1042 * !0 - otherwise 1043 * 1044 * \return 0 on success\n 1045 * <0 - Negative POSIX Error code 1046 * 1047 * \note If UMD wants only to check operation status and returned immediately 1048 * then timeout value as 0 must be passed. In this case success will be 1049 * returned in the case if submission was completed or timeout error 1050 * code. 1051 * 1052 * \sa amdgpu_cs_submit() 1053 */ 1054 int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, 1055 uint64_t timeout_ns, 1056 uint64_t flags, 1057 uint32_t *expired); 1058 1059 /** 1060 * Wait for multiple fences 1061 * 1062 * \param fences - \c [in] The fence array to wait 1063 * \param fence_count - \c [in] The fence count 1064 * \param wait_all - \c [in] If true, wait all fences to be signaled, 1065 * otherwise, wait at least one fence 1066 * \param timeout_ns - \c [in] The timeout to wait, in nanoseconds 1067 * \param status - \c [out] '1' for signaled, '0' for timeout 1068 * \param first - \c [out] the index of the first signaled fence from @fences 1069 * 1070 * \return 0 on success 1071 * <0 - Negative POSIX Error code 1072 * 1073 * \note Currently it supports only one amdgpu_device. All fences come from 1074 * the same amdgpu_device with the same fd. 1075 */ 1076 int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, 1077 uint32_t fence_count, 1078 bool wait_all, 1079 uint64_t timeout_ns, 1080 uint32_t *status, uint32_t *first); 1081 1082 /* 1083 * Query / Info API 1084 * 1085 */ 1086 1087 /** 1088 * Query allocation size alignments 1089 * 1090 * UMD should query information about GPU VM MC size alignments requirements 1091 * to be able correctly choose required allocation size and implement 1092 * internal optimization if needed. 1093 * 1094 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1095 * \param info - \c [out] Pointer to structure to get size alignment 1096 * requirements 1097 * 1098 * \return 0 on success\n 1099 * <0 - Negative POSIX Error code 1100 * 1101 */ 1102 int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev, 1103 struct amdgpu_buffer_size_alignments 1104 *info); 1105 1106 /** 1107 * Query firmware versions 1108 * 1109 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1110 * \param fw_type - \c [in] AMDGPU_INFO_FW_* 1111 * \param ip_instance - \c [in] Index of the IP block of the same type. 1112 * \param index - \c [in] Index of the engine. (for SDMA and MEC) 1113 * \param version - \c [out] Pointer to to the "version" return value 1114 * \param feature - \c [out] Pointer to to the "feature" return value 1115 * 1116 * \return 0 on success\n 1117 * <0 - Negative POSIX Error code 1118 * 1119 */ 1120 int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type, 1121 unsigned ip_instance, unsigned index, 1122 uint32_t *version, uint32_t *feature); 1123 1124 /** 1125 * Query the number of HW IP instances of a certain type. 1126 * 1127 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1128 * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* 1129 * \param count - \c [out] Pointer to structure to get information 1130 * 1131 * \return 0 on success\n 1132 * <0 - Negative POSIX Error code 1133 */ 1134 int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type, 1135 uint32_t *count); 1136 1137 /** 1138 * Query engine information 1139 * 1140 * This query allows UMD to query information different engines and their 1141 * capabilities. 1142 * 1143 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1144 * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* 1145 * \param ip_instance - \c [in] Index of the IP block of the same type. 1146 * \param info - \c [out] Pointer to structure to get information 1147 * 1148 * \return 0 on success\n 1149 * <0 - Negative POSIX Error code 1150 */ 1151 int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type, 1152 unsigned ip_instance, 1153 struct drm_amdgpu_info_hw_ip *info); 1154 1155 /** 1156 * Query heap information 1157 * 1158 * This query allows UMD to query potentially available memory resources and 1159 * adjust their logic if necessary. 1160 * 1161 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1162 * \param heap - \c [in] Heap type 1163 * \param info - \c [in] Pointer to structure to get needed information 1164 * 1165 * \return 0 on success\n 1166 * <0 - Negative POSIX Error code 1167 * 1168 */ 1169 int amdgpu_query_heap_info(amdgpu_device_handle dev, uint32_t heap, 1170 uint32_t flags, struct amdgpu_heap_info *info); 1171 1172 /** 1173 * Get the CRTC ID from the mode object ID 1174 * 1175 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1176 * \param id - \c [in] Mode object ID 1177 * \param result - \c [in] Pointer to the CRTC ID 1178 * 1179 * \return 0 on success\n 1180 * <0 - Negative POSIX Error code 1181 * 1182 */ 1183 int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id, 1184 int32_t *result); 1185 1186 /** 1187 * Query GPU H/w Info 1188 * 1189 * Query hardware specific information 1190 * 1191 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1192 * \param heap - \c [in] Heap type 1193 * \param info - \c [in] Pointer to structure to get needed information 1194 * 1195 * \return 0 on success\n 1196 * <0 - Negative POSIX Error code 1197 * 1198 */ 1199 int amdgpu_query_gpu_info(amdgpu_device_handle dev, 1200 struct amdgpu_gpu_info *info); 1201 1202 /** 1203 * Query hardware or driver information. 1204 * 1205 * The return size is query-specific and depends on the "info_id" parameter. 1206 * No more than "size" bytes is returned. 1207 * 1208 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1209 * \param info_id - \c [in] AMDGPU_INFO_* 1210 * \param size - \c [in] Size of the returned value. 1211 * \param value - \c [out] Pointer to the return value. 1212 * 1213 * \return 0 on success\n 1214 * <0 - Negative POSIX error code 1215 * 1216 */ 1217 int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, 1218 unsigned size, void *value); 1219 1220 /** 1221 * Query hardware or driver information. 1222 * 1223 * The return size is query-specific and depends on the "info_id" parameter. 1224 * No more than "size" bytes is returned. 1225 * 1226 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1227 * \param info - \c [in] amdgpu_sw_info_* 1228 * \param value - \c [out] Pointer to the return value. 1229 * 1230 * \return 0 on success\n 1231 * <0 - Negative POSIX error code 1232 * 1233 */ 1234 int amdgpu_query_sw_info(amdgpu_device_handle dev, enum amdgpu_sw_info info, 1235 void *value); 1236 1237 /** 1238 * Query information about GDS 1239 * 1240 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1241 * \param gds_info - \c [out] Pointer to structure to get GDS information 1242 * 1243 * \return 0 on success\n 1244 * <0 - Negative POSIX Error code 1245 * 1246 */ 1247 int amdgpu_query_gds_info(amdgpu_device_handle dev, 1248 struct amdgpu_gds_resource_info *gds_info); 1249 1250 /** 1251 * Query information about sensor. 1252 * 1253 * The return size is query-specific and depends on the "sensor_type" 1254 * parameter. No more than "size" bytes is returned. 1255 * 1256 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1257 * \param sensor_type - \c [in] AMDGPU_INFO_SENSOR_* 1258 * \param size - \c [in] Size of the returned value. 1259 * \param value - \c [out] Pointer to the return value. 1260 * 1261 * \return 0 on success\n 1262 * <0 - Negative POSIX Error code 1263 * 1264 */ 1265 int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type, 1266 unsigned size, void *value); 1267 1268 /** 1269 * Query information about video capabilities 1270 * 1271 * The return sizeof(struct drm_amdgpu_info_video_caps) 1272 * 1273 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1274 * \param caps_type - \c [in] AMDGPU_INFO_VIDEO_CAPS_DECODE(ENCODE) 1275 * \param size - \c [in] Size of the returned value. 1276 * \param value - \c [out] Pointer to the return value. 1277 * 1278 * \return 0 on success\n 1279 * <0 - Negative POSIX Error code 1280 * 1281 */ 1282 int amdgpu_query_video_caps_info(amdgpu_device_handle dev, unsigned cap_type, 1283 unsigned size, void *value); 1284 1285 /** 1286 * Query information about VM faults 1287 * 1288 * The return sizeof(struct drm_amdgpu_info_gpuvm_fault) 1289 * 1290 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1291 * \param size - \c [in] Size of the returned value. 1292 * \param value - \c [out] Pointer to the return value. 1293 * 1294 * \return 0 on success\n 1295 * <0 - Negative POSIX Error code 1296 * 1297 */ 1298 int amdgpu_query_gpuvm_fault_info(amdgpu_device_handle dev, unsigned size, 1299 void *value); 1300 1301 /** 1302 * Read a set of consecutive memory-mapped registers. 1303 * Not all registers are allowed to be read by userspace. 1304 * 1305 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize( 1306 * \param dword_offset - \c [in] Register offset in dwords 1307 * \param count - \c [in] The number of registers to read starting 1308 * from the offset 1309 * \param instance - \c [in] GRBM_GFX_INDEX selector. It may have other 1310 * uses. Set it to 0xffffffff if unsure. 1311 * \param flags - \c [in] Flags with additional information. 1312 * \param values - \c [out] The pointer to return values. 1313 * 1314 * \return 0 on success\n 1315 * <0 - Negative POSIX error code 1316 * 1317 */ 1318 int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset, 1319 unsigned count, uint32_t instance, uint32_t flags, 1320 uint32_t *values); 1321 1322 /** 1323 * Flag to request VA address range in the 32bit address space 1324 */ 1325 #define AMDGPU_VA_RANGE_32_BIT 0x1 1326 #define AMDGPU_VA_RANGE_HIGH 0x2 1327 #define AMDGPU_VA_RANGE_REPLAYABLE 0x4 1328 1329 /** 1330 * Allocate virtual address range 1331 * 1332 * \param dev - [in] Device handle. See #amdgpu_device_initialize() 1333 * \param va_range_type - \c [in] Type of MC va range from which to allocate 1334 * \param size - \c [in] Size of range. Size must be correctly* aligned. 1335 * It is client responsibility to correctly aligned size based on the future 1336 * usage of allocated range. 1337 * \param va_base_alignment - \c [in] Overwrite base address alignment 1338 * requirement for GPU VM MC virtual 1339 * address assignment. Must be multiple of size alignments received as 1340 * 'amdgpu_buffer_size_alignments'. 1341 * If 0 use the default one. 1342 * \param va_base_required - \c [in] Specified required va base address. 1343 * If 0 then library choose available one. 1344 * If !0 value will be passed and those value already "in use" then 1345 * corresponding error status will be returned. 1346 * \param va_base_allocated - \c [out] On return: Allocated VA base to be used 1347 * by client. 1348 * \param va_range_handle - \c [out] On return: Handle assigned to allocation 1349 * \param flags - \c [in] flags for special VA range 1350 * 1351 * \return 0 on success\n 1352 * >0 - AMD specific error code\n 1353 * <0 - Negative POSIX Error code 1354 * 1355 * \notes \n 1356 * It is client responsibility to correctly handle VA assignments and usage. 1357 * Neither kernel driver nor libdrm_amdpgu are able to prevent and 1358 * detect wrong va assignment. 1359 * 1360 * It is client responsibility to correctly handle multi-GPU cases and to pass 1361 * the corresponding arrays of all devices handles where corresponding VA will 1362 * be used. 1363 * 1364 */ 1365 int amdgpu_va_range_alloc(amdgpu_device_handle dev, 1366 enum amdgpu_gpu_va_range va_range_type, 1367 uint64_t size, 1368 uint64_t va_base_alignment, 1369 uint64_t va_base_required, 1370 uint64_t *va_base_allocated, 1371 amdgpu_va_handle *va_range_handle, 1372 uint64_t flags); 1373 1374 /** 1375 * Free previously allocated virtual address range 1376 * 1377 * 1378 * \param va_range_handle - \c [in] Handle assigned to VA allocation 1379 * 1380 * \return 0 on success\n 1381 * >0 - AMD specific error code\n 1382 * <0 - Negative POSIX Error code 1383 * 1384 */ 1385 int amdgpu_va_range_free(amdgpu_va_handle va_range_handle); 1386 1387 /** 1388 * Return the starting address of the allocated virtual address range. 1389 */ 1390 uint64_t amdgpu_va_get_start_addr(amdgpu_va_handle va_handle); 1391 1392 /** 1393 * Query virtual address range 1394 * 1395 * UMD can query GPU VM range supported by each device 1396 * to initialize its own VAM accordingly. 1397 * 1398 * \param dev - [in] Device handle. See #amdgpu_device_initialize() 1399 * \param type - \c [in] Type of virtual address range 1400 * \param offset - \c [out] Start offset of virtual address range 1401 * \param size - \c [out] Size of virtual address range 1402 * 1403 * \return 0 on success\n 1404 * <0 - Negative POSIX Error code 1405 * 1406 */ 1407 1408 int amdgpu_va_range_query(amdgpu_device_handle dev, 1409 enum amdgpu_gpu_va_range type, 1410 uint64_t *start, 1411 uint64_t *end); 1412 1413 /** 1414 * VA mapping/unmapping for the buffer object 1415 * 1416 * \param bo - \c [in] BO handle 1417 * \param offset - \c [in] Start offset to map 1418 * \param size - \c [in] Size to map 1419 * \param addr - \c [in] Start virtual address. 1420 * \param flags - \c [in] Supported flags for mapping/unmapping 1421 * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP 1422 * 1423 * \return 0 on success\n 1424 * <0 - Negative POSIX Error code 1425 * 1426 */ 1427 1428 int amdgpu_bo_va_op(amdgpu_bo_handle bo, 1429 uint64_t offset, 1430 uint64_t size, 1431 uint64_t addr, 1432 uint64_t flags, 1433 uint32_t ops); 1434 1435 /** 1436 * VA mapping/unmapping for a buffer object or PRT region. 1437 * 1438 * This is not a simple drop-in extension for amdgpu_bo_va_op; instead, all 1439 * parameters are treated "raw", i.e. size is not automatically aligned, and 1440 * all flags must be specified explicitly. 1441 * 1442 * \param dev - \c [in] device handle 1443 * \param bo - \c [in] BO handle (may be NULL) 1444 * \param offset - \c [in] Start offset to map 1445 * \param size - \c [in] Size to map 1446 * \param addr - \c [in] Start virtual address. 1447 * \param flags - \c [in] Supported flags for mapping/unmapping 1448 * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP 1449 * 1450 * \return 0 on success\n 1451 * <0 - Negative POSIX Error code 1452 * 1453 */ 1454 1455 int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, 1456 amdgpu_bo_handle bo, 1457 uint64_t offset, 1458 uint64_t size, 1459 uint64_t addr, 1460 uint64_t flags, 1461 uint32_t ops); 1462 1463 /** 1464 * create semaphore 1465 * 1466 * \param sem - \c [out] semaphore handle 1467 * 1468 * \return 0 on success\n 1469 * <0 - Negative POSIX Error code 1470 * 1471 */ 1472 int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem); 1473 1474 /** 1475 * signal semaphore 1476 * 1477 * \param context - \c [in] GPU Context 1478 * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* 1479 * \param ip_instance - \c [in] Index of the IP block of the same type 1480 * \param ring - \c [in] Specify ring index of the IP 1481 * \param sem - \c [in] semaphore handle 1482 * 1483 * \return 0 on success\n 1484 * <0 - Negative POSIX Error code 1485 * 1486 */ 1487 int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx, 1488 uint32_t ip_type, 1489 uint32_t ip_instance, 1490 uint32_t ring, 1491 amdgpu_semaphore_handle sem); 1492 1493 /** 1494 * wait semaphore 1495 * 1496 * \param context - \c [in] GPU Context 1497 * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* 1498 * \param ip_instance - \c [in] Index of the IP block of the same type 1499 * \param ring - \c [in] Specify ring index of the IP 1500 * \param sem - \c [in] semaphore handle 1501 * 1502 * \return 0 on success\n 1503 * <0 - Negative POSIX Error code 1504 * 1505 */ 1506 int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, 1507 uint32_t ip_type, 1508 uint32_t ip_instance, 1509 uint32_t ring, 1510 amdgpu_semaphore_handle sem); 1511 1512 /** 1513 * destroy semaphore 1514 * 1515 * \param sem - \c [in] semaphore handle 1516 * 1517 * \return 0 on success\n 1518 * <0 - Negative POSIX Error code 1519 * 1520 */ 1521 int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem); 1522 1523 /** 1524 * Get the ASIC marketing name 1525 * 1526 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 1527 * 1528 * \return the constant string of the marketing name 1529 * "NULL" means the ASIC is not found 1530 */ 1531 const char *amdgpu_get_marketing_name(amdgpu_device_handle dev); 1532 1533 /** 1534 * Create kernel sync object 1535 * 1536 * \param dev - \c [in] device handle 1537 * \param flags - \c [in] flags that affect creation 1538 * \param syncobj - \c [out] sync object handle 1539 * 1540 * \return 0 on success\n 1541 * <0 - Negative POSIX Error code 1542 * 1543 */ 1544 int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev, 1545 uint32_t flags, 1546 uint32_t *syncobj); 1547 1548 /** 1549 * Create kernel sync object 1550 * 1551 * \param dev - \c [in] device handle 1552 * \param syncobj - \c [out] sync object handle 1553 * 1554 * \return 0 on success\n 1555 * <0 - Negative POSIX Error code 1556 * 1557 */ 1558 int amdgpu_cs_create_syncobj(amdgpu_device_handle dev, 1559 uint32_t *syncobj); 1560 /** 1561 * Destroy kernel sync object 1562 * 1563 * \param dev - \c [in] device handle 1564 * \param syncobj - \c [in] sync object handle 1565 * 1566 * \return 0 on success\n 1567 * <0 - Negative POSIX Error code 1568 * 1569 */ 1570 int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev, 1571 uint32_t syncobj); 1572 1573 /** 1574 * Reset kernel sync objects to unsignalled state. 1575 * 1576 * \param dev - \c [in] device handle 1577 * \param syncobjs - \c [in] array of sync object handles 1578 * \param syncobj_count - \c [in] number of handles in syncobjs 1579 * 1580 * \return 0 on success\n 1581 * <0 - Negative POSIX Error code 1582 * 1583 */ 1584 int amdgpu_cs_syncobj_reset(amdgpu_device_handle dev, 1585 const uint32_t *syncobjs, uint32_t syncobj_count); 1586 1587 /** 1588 * Signal kernel sync objects. 1589 * 1590 * \param dev - \c [in] device handle 1591 * \param syncobjs - \c [in] array of sync object handles 1592 * \param syncobj_count - \c [in] number of handles in syncobjs 1593 * 1594 * \return 0 on success\n 1595 * <0 - Negative POSIX Error code 1596 * 1597 */ 1598 int amdgpu_cs_syncobj_signal(amdgpu_device_handle dev, 1599 const uint32_t *syncobjs, uint32_t syncobj_count); 1600 1601 /** 1602 * Signal kernel timeline sync objects. 1603 * 1604 * \param dev - \c [in] device handle 1605 * \param syncobjs - \c [in] array of sync object handles 1606 * \param points - \c [in] array of timeline points 1607 * \param syncobj_count - \c [in] number of handles in syncobjs 1608 * 1609 * \return 0 on success\n 1610 * <0 - Negative POSIX Error code 1611 * 1612 */ 1613 int amdgpu_cs_syncobj_timeline_signal(amdgpu_device_handle dev, 1614 const uint32_t *syncobjs, 1615 uint64_t *points, 1616 uint32_t syncobj_count); 1617 1618 /** 1619 * Wait for one or all sync objects to signal. 1620 * 1621 * \param dev - \c [in] self-explanatory 1622 * \param handles - \c [in] array of sync object handles 1623 * \param num_handles - \c [in] self-explanatory 1624 * \param timeout_nsec - \c [in] self-explanatory 1625 * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_* 1626 * \param first_signaled - \c [in] self-explanatory 1627 * 1628 * \return 0 on success\n 1629 * -ETIME - Timeout 1630 * <0 - Negative POSIX Error code 1631 * 1632 */ 1633 int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev, 1634 uint32_t *handles, unsigned num_handles, 1635 int64_t timeout_nsec, unsigned flags, 1636 uint32_t *first_signaled); 1637 1638 /** 1639 * Wait for one or all sync objects on their points to signal. 1640 * 1641 * \param dev - \c [in] self-explanatory 1642 * \param handles - \c [in] array of sync object handles 1643 * \param points - \c [in] array of sync points to wait 1644 * \param num_handles - \c [in] self-explanatory 1645 * \param timeout_nsec - \c [in] self-explanatory 1646 * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_* 1647 * \param first_signaled - \c [in] self-explanatory 1648 * 1649 * \return 0 on success\n 1650 * -ETIME - Timeout 1651 * <0 - Negative POSIX Error code 1652 * 1653 */ 1654 int amdgpu_cs_syncobj_timeline_wait(amdgpu_device_handle dev, 1655 uint32_t *handles, uint64_t *points, 1656 unsigned num_handles, 1657 int64_t timeout_nsec, unsigned flags, 1658 uint32_t *first_signaled); 1659 /** 1660 * Query sync objects payloads. 1661 * 1662 * \param dev - \c [in] self-explanatory 1663 * \param handles - \c [in] array of sync object handles 1664 * \param points - \c [out] array of sync points returned, which presents 1665 * syncobj payload. 1666 * \param num_handles - \c [in] self-explanatory 1667 * 1668 * \return 0 on success\n 1669 * -ETIME - Timeout 1670 * <0 - Negative POSIX Error code 1671 * 1672 */ 1673 int amdgpu_cs_syncobj_query(amdgpu_device_handle dev, 1674 uint32_t *handles, uint64_t *points, 1675 unsigned num_handles); 1676 /** 1677 * Query sync objects last signaled or submitted point. 1678 * 1679 * \param dev - \c [in] self-explanatory 1680 * \param handles - \c [in] array of sync object handles 1681 * \param points - \c [out] array of sync points returned, which presents 1682 * syncobj payload. 1683 * \param num_handles - \c [in] self-explanatory 1684 * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_QUERY_FLAGS_* 1685 * 1686 * \return 0 on success\n 1687 * -ETIME - Timeout 1688 * <0 - Negative POSIX Error code 1689 * 1690 */ 1691 int amdgpu_cs_syncobj_query2(amdgpu_device_handle dev, 1692 uint32_t *handles, uint64_t *points, 1693 unsigned num_handles, uint32_t flags); 1694 1695 /** 1696 * Export kernel sync object to shareable fd. 1697 * 1698 * \param dev - \c [in] device handle 1699 * \param syncobj - \c [in] sync object handle 1700 * \param shared_fd - \c [out] shared file descriptor. 1701 * 1702 * \return 0 on success\n 1703 * <0 - Negative POSIX Error code 1704 * 1705 */ 1706 int amdgpu_cs_export_syncobj(amdgpu_device_handle dev, 1707 uint32_t syncobj, 1708 int *shared_fd); 1709 /** 1710 * Import kernel sync object from shareable fd. 1711 * 1712 * \param dev - \c [in] device handle 1713 * \param shared_fd - \c [in] shared file descriptor. 1714 * \param syncobj - \c [out] sync object handle 1715 * 1716 * \return 0 on success\n 1717 * <0 - Negative POSIX Error code 1718 * 1719 */ 1720 int amdgpu_cs_import_syncobj(amdgpu_device_handle dev, 1721 int shared_fd, 1722 uint32_t *syncobj); 1723 1724 /** 1725 * Export kernel sync object to a sync_file. 1726 * 1727 * \param dev - \c [in] device handle 1728 * \param syncobj - \c [in] sync object handle 1729 * \param sync_file_fd - \c [out] sync_file file descriptor. 1730 * 1731 * \return 0 on success\n 1732 * <0 - Negative POSIX Error code 1733 * 1734 */ 1735 int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev, 1736 uint32_t syncobj, 1737 int *sync_file_fd); 1738 1739 /** 1740 * Import kernel sync object from a sync_file. 1741 * 1742 * \param dev - \c [in] device handle 1743 * \param syncobj - \c [in] sync object handle 1744 * \param sync_file_fd - \c [in] sync_file file descriptor. 1745 * 1746 * \return 0 on success\n 1747 * <0 - Negative POSIX Error code 1748 * 1749 */ 1750 int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev, 1751 uint32_t syncobj, 1752 int sync_file_fd); 1753 /** 1754 * Export kernel timeline sync object to a sync_file. 1755 * 1756 * \param dev - \c [in] device handle 1757 * \param syncobj - \c [in] sync object handle 1758 * \param point - \c [in] timeline point 1759 * \param flags - \c [in] flags 1760 * \param sync_file_fd - \c [out] sync_file file descriptor. 1761 * 1762 * \return 0 on success\n 1763 * <0 - Negative POSIX Error code 1764 * 1765 */ 1766 int amdgpu_cs_syncobj_export_sync_file2(amdgpu_device_handle dev, 1767 uint32_t syncobj, 1768 uint64_t point, 1769 uint32_t flags, 1770 int *sync_file_fd); 1771 1772 /** 1773 * Import kernel timeline sync object from a sync_file. 1774 * 1775 * \param dev - \c [in] device handle 1776 * \param syncobj - \c [in] sync object handle 1777 * \param point - \c [in] timeline point 1778 * \param sync_file_fd - \c [in] sync_file file descriptor. 1779 * 1780 * \return 0 on success\n 1781 * <0 - Negative POSIX Error code 1782 * 1783 */ 1784 int amdgpu_cs_syncobj_import_sync_file2(amdgpu_device_handle dev, 1785 uint32_t syncobj, 1786 uint64_t point, 1787 int sync_file_fd); 1788 1789 /** 1790 * transfer between syncbojs. 1791 * 1792 * \param dev - \c [in] device handle 1793 * \param dst_handle - \c [in] sync object handle 1794 * \param dst_point - \c [in] timeline point, 0 presents dst is binary 1795 * \param src_handle - \c [in] sync object handle 1796 * \param src_point - \c [in] timeline point, 0 presents src is binary 1797 * \param flags - \c [in] flags 1798 * 1799 * \return 0 on success\n 1800 * <0 - Negative POSIX Error code 1801 * 1802 */ 1803 int amdgpu_cs_syncobj_transfer(amdgpu_device_handle dev, 1804 uint32_t dst_handle, 1805 uint64_t dst_point, 1806 uint32_t src_handle, 1807 uint64_t src_point, 1808 uint32_t flags); 1809 1810 /** 1811 * Export an amdgpu fence as a handle (syncobj or fd). 1812 * 1813 * \param what AMDGPU_FENCE_TO_HANDLE_GET_{SYNCOBJ, FD} 1814 * \param out_handle returned handle 1815 * 1816 * \return 0 on success\n 1817 * <0 - Negative POSIX Error code 1818 */ 1819 int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev, 1820 struct amdgpu_cs_fence *fence, 1821 uint32_t what, 1822 uint32_t *out_handle); 1823 1824 /** 1825 * Submit raw command submission to kernel 1826 * 1827 * \param dev - \c [in] device handle 1828 * \param context - \c [in] context handle for context id 1829 * \param bo_list_handle - \c [in] request bo list handle (0 for none) 1830 * \param num_chunks - \c [in] number of CS chunks to submit 1831 * \param chunks - \c [in] array of CS chunks 1832 * \param seq_no - \c [out] output sequence number for submission. 1833 * 1834 * \return 0 on success\n 1835 * <0 - Negative POSIX Error code 1836 * 1837 */ 1838 struct drm_amdgpu_cs_chunk; 1839 struct drm_amdgpu_cs_chunk_dep; 1840 struct drm_amdgpu_cs_chunk_data; 1841 1842 int amdgpu_cs_submit_raw(amdgpu_device_handle dev, 1843 amdgpu_context_handle context, 1844 amdgpu_bo_list_handle bo_list_handle, 1845 int num_chunks, 1846 struct drm_amdgpu_cs_chunk *chunks, 1847 uint64_t *seq_no); 1848 1849 /** 1850 * Submit raw command submission to the kernel with a raw BO list handle. 1851 * 1852 * \param dev - \c [in] device handle 1853 * \param context - \c [in] context handle for context id 1854 * \param bo_list_handle - \c [in] raw bo list handle (0 for none) 1855 * \param num_chunks - \c [in] number of CS chunks to submit 1856 * \param chunks - \c [in] array of CS chunks 1857 * \param seq_no - \c [out] output sequence number for submission. 1858 * 1859 * \return 0 on success\n 1860 * <0 - Negative POSIX Error code 1861 * 1862 * \sa amdgpu_bo_list_create_raw(), amdgpu_bo_list_destroy_raw() 1863 */ 1864 int amdgpu_cs_submit_raw2(amdgpu_device_handle dev, 1865 amdgpu_context_handle context, 1866 uint32_t bo_list_handle, 1867 int num_chunks, 1868 struct drm_amdgpu_cs_chunk *chunks, 1869 uint64_t *seq_no); 1870 1871 void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence, 1872 struct drm_amdgpu_cs_chunk_dep *dep); 1873 void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info, 1874 struct drm_amdgpu_cs_chunk_data *data); 1875 1876 /** 1877 * Reserve VMID 1878 * \param context - \c [in] GPU Context 1879 * \param flags - \c [in] TBD 1880 * 1881 * \return 0 on success otherwise POSIX Error code 1882 */ 1883 int amdgpu_vm_reserve_vmid(amdgpu_device_handle dev, uint32_t flags); 1884 1885 /** 1886 * Free reserved VMID 1887 * \param context - \c [in] GPU Context 1888 * \param flags - \c [in] TBD 1889 * 1890 * \return 0 on success otherwise POSIX Error code 1891 */ 1892 int amdgpu_vm_unreserve_vmid(amdgpu_device_handle dev, uint32_t flags); 1893 1894 #ifdef __cplusplus 1895 } 1896 #endif 1897 #endif /* #ifdef _AMDGPU_H_ */ 1898