1 /*
2 * Copyright © 2020 Valve Corporation
3 *
4 * based on amdgpu winsys.
5 * Copyright © 2016 Red Hat.
6 * Copyright © 2016 Bas Nieuwenhuizen
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27 #include "radv_null_winsys_public.h"
28
29 #include "util/u_string.h"
30 #include "radv_null_bo.h"
31 #include "radv_null_cs.h"
32 #include "vk_sync_dummy.h"
33
34 /* Hardcode some GPU info that are needed for the driver or for some tools. */
35 static const struct {
36 uint32_t pci_id;
37 uint32_t num_render_backends;
38 bool has_dedicated_vram;
39 } gpu_info[] = {
40 [CHIP_TAHITI] = {0x6780, 8, true},
41 [CHIP_PITCAIRN] = {0x6800, 8, true},
42 [CHIP_VERDE] = {0x6820, 4, true},
43 [CHIP_OLAND] = {0x6060, 2, true},
44 [CHIP_HAINAN] = {0x6660, 2, true},
45 [CHIP_BONAIRE] = {0x6640, 4, true},
46 [CHIP_KAVERI] = {0x1304, 2, false},
47 [CHIP_KABINI] = {0x9830, 2, false},
48 [CHIP_HAWAII] = {0x67A0, 16, true},
49 [CHIP_TONGA] = {0x6920, 8, true},
50 [CHIP_ICELAND] = {0x6900, 2, true},
51 [CHIP_CARRIZO] = {0x9870, 2, false},
52 [CHIP_FIJI] = {0x7300, 16, true},
53 [CHIP_STONEY] = {0x98E4, 2, false},
54 [CHIP_POLARIS10] = {0x67C0, 8, true},
55 [CHIP_POLARIS11] = {0x67E0, 4, true},
56 [CHIP_POLARIS12] = {0x6980, 4, true},
57 [CHIP_VEGAM] = {0x694C, 4, true},
58 [CHIP_VEGA10] = {0x6860, 16, true},
59 [CHIP_VEGA12] = {0x69A0, 8, true},
60 [CHIP_VEGA20] = {0x66A0, 16, true},
61 [CHIP_RAVEN] = {0x15DD, 2, false},
62 [CHIP_RENOIR] = {0x1636, 2, false},
63 [CHIP_ARCTURUS] = {0x738C, 2, true},
64 [CHIP_NAVI10] = {0x7310, 16, true},
65 [CHIP_NAVI12] = {0x7360, 8, true},
66 [CHIP_NAVI14] = {0x7340, 8, true},
67 [CHIP_NAVI21] = {0x73A0, 16, true},
68 [CHIP_VANGOGH] = {0x163F, 8, false},
69 [CHIP_NAVI22] = {0x73C0, 8, true},
70 [CHIP_NAVI23] = {0x73E0, 8, true},
71 [CHIP_GFX1100] = {0xdead, 8, true}, /* TODO: fill with real info. */
72 };
73
74 static void
radv_null_winsys_query_info(struct radeon_winsys * rws,struct radeon_info * info)75 radv_null_winsys_query_info(struct radeon_winsys *rws, struct radeon_info *info)
76 {
77 const char *family = getenv("RADV_FORCE_FAMILY");
78 unsigned i;
79
80 info->gfx_level = CLASS_UNKNOWN;
81 info->family = CHIP_UNKNOWN;
82
83 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
84 if (!strcasecmp(family, ac_get_family_name(i))) {
85 /* Override family and gfx_level. */
86 info->family = i;
87 info->name = ac_get_family_name(i);
88
89 if (info->family >= CHIP_GFX1100)
90 info->gfx_level = GFX11;
91 else if (i >= CHIP_NAVI21)
92 info->gfx_level = GFX10_3;
93 else if (i >= CHIP_NAVI10)
94 info->gfx_level = GFX10;
95 else if (i >= CHIP_VEGA10)
96 info->gfx_level = GFX9;
97 else if (i >= CHIP_TONGA)
98 info->gfx_level = GFX8;
99 else if (i >= CHIP_BONAIRE)
100 info->gfx_level = GFX7;
101 else
102 info->gfx_level = GFX6;
103 }
104 }
105
106 if (info->family == CHIP_UNKNOWN) {
107 fprintf(stderr, "radv: Unknown family: %s\n", family);
108 abort();
109 }
110
111 info->pci_id = gpu_info[info->family].pci_id;
112 info->max_se = 4;
113 info->num_se = 4;
114 if (info->gfx_level >= GFX10_3)
115 info->max_wave64_per_simd = 16;
116 else if (info->gfx_level >= GFX10)
117 info->max_wave64_per_simd = 20;
118 else if (info->family >= CHIP_POLARIS10 && info->family <= CHIP_VEGAM)
119 info->max_wave64_per_simd = 8;
120 else
121 info->max_wave64_per_simd = 10;
122
123 if (info->gfx_level >= GFX10)
124 info->num_physical_sgprs_per_simd = 128 * info->max_wave64_per_simd * 2;
125 else if (info->gfx_level >= GFX8)
126 info->num_physical_sgprs_per_simd = 800;
127 else
128 info->num_physical_sgprs_per_simd = 512;
129
130 info->num_physical_wave64_vgprs_per_simd = info->gfx_level >= GFX10 ? 512 : 256;
131 info->num_simd_per_compute_unit = info->gfx_level >= GFX10 ? 2 : 4;
132 info->lds_size_per_workgroup = info->gfx_level >= GFX10 ? 128 * 1024 : 64 * 1024;
133 info->lds_encode_granularity = info->gfx_level >= GFX7 ? 128 * 4 : 64 * 4;
134 info->lds_alloc_granularity =
135 info->gfx_level >= GFX10_3 ? 256 * 4 : info->lds_encode_granularity;
136 info->max_render_backends = gpu_info[info->family].num_render_backends;
137
138 info->has_dedicated_vram = gpu_info[info->family].has_dedicated_vram;
139 info->has_packed_math_16bit = info->gfx_level >= GFX9;
140
141 info->has_image_load_dcc_bug =
142 info->family == CHIP_NAVI23 || info->family == CHIP_VANGOGH;
143
144 info->has_accelerated_dot_product =
145 info->family == CHIP_ARCTURUS || info->family == CHIP_ALDEBARAN ||
146 info->family == CHIP_VEGA20 || info->family >= CHIP_NAVI12;
147
148 info->address32_hi = info->gfx_level >= GFX9 ? 0xffff8000u : 0x0;
149
150 info->has_rbplus = info->family == CHIP_STONEY || info->gfx_level >= GFX9;
151 info->rbplus_allowed =
152 info->has_rbplus &&
153 (info->family == CHIP_STONEY || info->family == CHIP_VEGA12 || info->family == CHIP_RAVEN ||
154 info->family == CHIP_RAVEN2 || info->family == CHIP_RENOIR || info->gfx_level >= GFX10_3);
155
156 }
157
158 static const char *
radv_null_winsys_get_chip_name(struct radeon_winsys * rws)159 radv_null_winsys_get_chip_name(struct radeon_winsys *rws)
160 {
161 return "Null hardware";
162 }
163
164 static void
radv_null_winsys_destroy(struct radeon_winsys * rws)165 radv_null_winsys_destroy(struct radeon_winsys *rws)
166 {
167 FREE(rws);
168 }
169
170 static int
radv_null_winsys_get_fd(struct radeon_winsys * rws)171 radv_null_winsys_get_fd(struct radeon_winsys *rws)
172 {
173 return -1;
174 }
175
176 static const struct vk_sync_type *const *
radv_null_winsys_get_sync_types(struct radeon_winsys * rws)177 radv_null_winsys_get_sync_types(struct radeon_winsys *rws)
178 {
179 return radv_null_winsys(rws)->sync_types;
180 }
181
182 struct radeon_winsys *
radv_null_winsys_create()183 radv_null_winsys_create()
184 {
185 struct radv_null_winsys *ws;
186
187 ws = calloc(1, sizeof(struct radv_null_winsys));
188 if (!ws)
189 return NULL;
190
191 ws->base.destroy = radv_null_winsys_destroy;
192 ws->base.query_info = radv_null_winsys_query_info;
193 ws->base.get_fd = radv_null_winsys_get_fd;
194 ws->base.get_sync_types = radv_null_winsys_get_sync_types;
195 ws->base.get_chip_name = radv_null_winsys_get_chip_name;
196 radv_null_bo_init_functions(ws);
197 radv_null_cs_init_functions(ws);
198
199 ws->sync_types[0] = &vk_sync_dummy_type;
200 ws->sync_types[1] = NULL;
201 return &ws->base;
202 }
203