1 /*
2 * Copyright © 2014-2015 Broadcom
3 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include "util/blob.h"
26 #include "util/debug.h"
27 #include "util/disk_cache.h"
28 #include "util/u_memory.h"
29 #include "util/ralloc.h"
30 #include "pipe/p_screen.h"
31
32 #include "compiler/nir/nir.h"
33 #include "compiler/nir/nir_control_flow.h"
34 #include "compiler/nir/nir_builder.h"
35 #include "compiler/nir/nir_serialize.h"
36 #include "compiler/shader_enums.h"
37
38 #include "tgsi_to_nir.h"
39 #include "tgsi/tgsi_parse.h"
40 #include "tgsi/tgsi_dump.h"
41 #include "tgsi/tgsi_info.h"
42 #include "tgsi/tgsi_scan.h"
43 #include "tgsi/tgsi_from_mesa.h"
44
45 #define SWIZ(X, Y, Z, W) (unsigned[4]){ \
46 TGSI_SWIZZLE_##X, \
47 TGSI_SWIZZLE_##Y, \
48 TGSI_SWIZZLE_##Z, \
49 TGSI_SWIZZLE_##W, \
50 }
51
52 struct ttn_reg_info {
53 /** nir register containing this TGSI index. */
54 nir_register *reg;
55 nir_variable *var;
56 /** Offset (in vec4s) from the start of var for this TGSI index. */
57 int offset;
58 };
59
60 struct ttn_compile {
61 union tgsi_full_token *token;
62 nir_builder build;
63 struct tgsi_shader_info *scan;
64
65 struct ttn_reg_info *output_regs;
66 struct ttn_reg_info *temp_regs;
67 nir_ssa_def **imm_defs;
68
69 unsigned num_samp_types;
70 nir_alu_type *samp_types;
71
72 nir_register *addr_reg;
73
74 nir_variable **inputs;
75 nir_variable **outputs;
76 nir_variable *samplers[PIPE_MAX_SAMPLERS];
77 nir_variable *images[PIPE_MAX_SHADER_IMAGES];
78 nir_variable *ssbo[PIPE_MAX_SHADER_BUFFERS];
79 uint32_t ubo_sizes[PIPE_MAX_CONSTANT_BUFFERS];
80
81 unsigned num_samplers;
82 unsigned num_images;
83 unsigned num_msaa_images;
84
85 nir_variable *input_var_face;
86 nir_variable *input_var_position;
87 nir_variable *input_var_point;
88
89 /* How many TGSI_FILE_IMMEDIATE vec4s have been parsed so far. */
90 unsigned next_imm;
91
92 bool cap_face_is_sysval;
93 bool cap_position_is_sysval;
94 bool cap_point_is_sysval;
95 bool cap_samplers_as_deref;
96 bool cap_integers;
97 };
98
99 #define ttn_swizzle(b, src, x, y, z, w) \
100 nir_swizzle(b, src, SWIZ(x, y, z, w), 4)
101 #define ttn_channel(b, src, swiz) \
102 nir_channel(b, src, TGSI_SWIZZLE_##swiz)
103
104 static gl_varying_slot
tgsi_varying_semantic_to_slot(unsigned semantic,unsigned index)105 tgsi_varying_semantic_to_slot(unsigned semantic, unsigned index)
106 {
107 switch (semantic) {
108 case TGSI_SEMANTIC_POSITION:
109 return VARYING_SLOT_POS;
110 case TGSI_SEMANTIC_COLOR:
111 if (index == 0)
112 return VARYING_SLOT_COL0;
113 else
114 return VARYING_SLOT_COL1;
115 case TGSI_SEMANTIC_BCOLOR:
116 if (index == 0)
117 return VARYING_SLOT_BFC0;
118 else
119 return VARYING_SLOT_BFC1;
120 case TGSI_SEMANTIC_FOG:
121 return VARYING_SLOT_FOGC;
122 case TGSI_SEMANTIC_PSIZE:
123 return VARYING_SLOT_PSIZ;
124 case TGSI_SEMANTIC_GENERIC:
125 assert(index < 32);
126 return VARYING_SLOT_VAR0 + index;
127 case TGSI_SEMANTIC_FACE:
128 return VARYING_SLOT_FACE;
129 case TGSI_SEMANTIC_EDGEFLAG:
130 return VARYING_SLOT_EDGE;
131 case TGSI_SEMANTIC_PRIMID:
132 return VARYING_SLOT_PRIMITIVE_ID;
133 case TGSI_SEMANTIC_CLIPDIST:
134 if (index == 0)
135 return VARYING_SLOT_CLIP_DIST0;
136 else
137 return VARYING_SLOT_CLIP_DIST1;
138 case TGSI_SEMANTIC_CLIPVERTEX:
139 return VARYING_SLOT_CLIP_VERTEX;
140 case TGSI_SEMANTIC_TEXCOORD:
141 assert(index < 8);
142 return VARYING_SLOT_TEX0 + index;
143 case TGSI_SEMANTIC_PCOORD:
144 return VARYING_SLOT_PNTC;
145 case TGSI_SEMANTIC_VIEWPORT_INDEX:
146 return VARYING_SLOT_VIEWPORT;
147 case TGSI_SEMANTIC_LAYER:
148 return VARYING_SLOT_LAYER;
149 case TGSI_SEMANTIC_TESSINNER:
150 return VARYING_SLOT_TESS_LEVEL_INNER;
151 case TGSI_SEMANTIC_TESSOUTER:
152 return VARYING_SLOT_TESS_LEVEL_OUTER;
153 default:
154 fprintf(stderr, "Bad TGSI semantic: %d/%d\n", semantic, index);
155 abort();
156 }
157 }
158
159 static enum gl_frag_depth_layout
ttn_get_depth_layout(unsigned tgsi_fs_depth_layout)160 ttn_get_depth_layout(unsigned tgsi_fs_depth_layout)
161 {
162 switch (tgsi_fs_depth_layout) {
163 case TGSI_FS_DEPTH_LAYOUT_NONE:
164 return FRAG_DEPTH_LAYOUT_NONE;
165 case TGSI_FS_DEPTH_LAYOUT_ANY:
166 return FRAG_DEPTH_LAYOUT_ANY;
167 case TGSI_FS_DEPTH_LAYOUT_GREATER:
168 return FRAG_DEPTH_LAYOUT_GREATER;
169 case TGSI_FS_DEPTH_LAYOUT_LESS:
170 return FRAG_DEPTH_LAYOUT_LESS;
171 case TGSI_FS_DEPTH_LAYOUT_UNCHANGED:
172 return FRAG_DEPTH_LAYOUT_UNCHANGED;
173 default:
174 unreachable("bad TGSI FS depth layout");
175 }
176 }
177
178 static nir_ssa_def *
ttn_src_for_dest(nir_builder * b,nir_alu_dest * dest)179 ttn_src_for_dest(nir_builder *b, nir_alu_dest *dest)
180 {
181 nir_alu_src src;
182 memset(&src, 0, sizeof(src));
183
184 if (dest->dest.is_ssa)
185 src.src = nir_src_for_ssa(&dest->dest.ssa);
186 else {
187 assert(!dest->dest.reg.indirect);
188 src.src = nir_src_for_reg(dest->dest.reg.reg);
189 src.src.reg.base_offset = dest->dest.reg.base_offset;
190 }
191
192 for (int i = 0; i < 4; i++)
193 src.swizzle[i] = i;
194
195 return nir_mov_alu(b, src, 4);
196 }
197
198 static enum glsl_interp_mode
ttn_translate_interp_mode(unsigned tgsi_interp)199 ttn_translate_interp_mode(unsigned tgsi_interp)
200 {
201 switch (tgsi_interp) {
202 case TGSI_INTERPOLATE_CONSTANT:
203 return INTERP_MODE_FLAT;
204 case TGSI_INTERPOLATE_LINEAR:
205 return INTERP_MODE_NOPERSPECTIVE;
206 case TGSI_INTERPOLATE_PERSPECTIVE:
207 return INTERP_MODE_SMOOTH;
208 case TGSI_INTERPOLATE_COLOR:
209 return INTERP_MODE_NONE;
210 default:
211 unreachable("bad TGSI interpolation mode");
212 }
213 }
214
215 static void
ttn_emit_declaration(struct ttn_compile * c)216 ttn_emit_declaration(struct ttn_compile *c)
217 {
218 nir_builder *b = &c->build;
219 struct tgsi_full_declaration *decl = &c->token->FullDeclaration;
220 unsigned array_size = decl->Range.Last - decl->Range.First + 1;
221 unsigned file = decl->Declaration.File;
222 unsigned i;
223
224 if (file == TGSI_FILE_TEMPORARY) {
225 if (decl->Declaration.Array) {
226 /* for arrays, we create variables instead of registers: */
227 nir_variable *var =
228 nir_variable_create(b->shader, nir_var_shader_temp,
229 glsl_array_type(glsl_vec4_type(), array_size, 0),
230 ralloc_asprintf(b->shader, "arr_%d",
231 decl->Array.ArrayID));
232
233 for (i = 0; i < array_size; i++) {
234 /* point all the matching slots to the same var,
235 * with appropriate offset set, mostly just so
236 * we know what to do when tgsi does a non-indirect
237 * access
238 */
239 c->temp_regs[decl->Range.First + i].reg = NULL;
240 c->temp_regs[decl->Range.First + i].var = var;
241 c->temp_regs[decl->Range.First + i].offset = i;
242 }
243 } else {
244 for (i = 0; i < array_size; i++) {
245 nir_register *reg = nir_local_reg_create(b->impl);
246 reg->num_components = 4;
247 c->temp_regs[decl->Range.First + i].reg = reg;
248 c->temp_regs[decl->Range.First + i].var = NULL;
249 c->temp_regs[decl->Range.First + i].offset = 0;
250 }
251 }
252 } else if (file == TGSI_FILE_ADDRESS) {
253 c->addr_reg = nir_local_reg_create(b->impl);
254 c->addr_reg->num_components = 4;
255 } else if (file == TGSI_FILE_SYSTEM_VALUE) {
256 /* Nothing to record for system values. */
257 } else if (file == TGSI_FILE_BUFFER) {
258 /* Nothing to record for buffers. */
259 } else if (file == TGSI_FILE_IMAGE) {
260 /* Nothing to record for images. */
261 } else if (file == TGSI_FILE_SAMPLER) {
262 /* Nothing to record for samplers. */
263 } else if (file == TGSI_FILE_SAMPLER_VIEW) {
264 struct tgsi_declaration_sampler_view *sview = &decl->SamplerView;
265 nir_alu_type type;
266
267 assert((sview->ReturnTypeX == sview->ReturnTypeY) &&
268 (sview->ReturnTypeX == sview->ReturnTypeZ) &&
269 (sview->ReturnTypeX == sview->ReturnTypeW));
270
271 switch (sview->ReturnTypeX) {
272 case TGSI_RETURN_TYPE_SINT:
273 type = nir_type_int32;
274 break;
275 case TGSI_RETURN_TYPE_UINT:
276 type = nir_type_uint32;
277 break;
278 case TGSI_RETURN_TYPE_FLOAT:
279 default:
280 type = nir_type_float32;
281 break;
282 }
283
284 for (i = 0; i < array_size; i++) {
285 c->samp_types[decl->Range.First + i] = type;
286 }
287 } else {
288 bool is_array = (array_size > 1);
289
290 assert(file == TGSI_FILE_INPUT ||
291 file == TGSI_FILE_OUTPUT ||
292 file == TGSI_FILE_CONSTANT);
293
294 /* nothing to do for UBOs: */
295 if ((file == TGSI_FILE_CONSTANT) && decl->Declaration.Dimension &&
296 decl->Dim.Index2D != 0) {
297 b->shader->info.num_ubos =
298 MAX2(b->shader->info.num_ubos, decl->Dim.Index2D);
299 c->ubo_sizes[decl->Dim.Index2D] =
300 MAX2(c->ubo_sizes[decl->Dim.Index2D], decl->Range.Last * 16);
301 return;
302 }
303
304 if ((file == TGSI_FILE_INPUT) || (file == TGSI_FILE_OUTPUT)) {
305 is_array = (is_array && decl->Declaration.Array &&
306 (decl->Array.ArrayID != 0));
307 }
308
309 for (i = 0; i < array_size; i++) {
310 unsigned idx = decl->Range.First + i;
311 nir_variable *var = rzalloc(b->shader, nir_variable);
312
313 var->data.driver_location = idx;
314
315 var->type = glsl_vec4_type();
316 if (is_array)
317 var->type = glsl_array_type(var->type, array_size, 0);
318
319 switch (file) {
320 case TGSI_FILE_INPUT:
321 var->data.read_only = true;
322 var->data.mode = nir_var_shader_in;
323 var->name = ralloc_asprintf(var, "in_%d", idx);
324
325 if (c->scan->processor == PIPE_SHADER_FRAGMENT) {
326 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
327 var->type = glsl_bool_type();
328 if (c->cap_face_is_sysval) {
329 var->data.mode = nir_var_system_value;
330 var->data.location = SYSTEM_VALUE_FRONT_FACE;
331 } else {
332 var->data.location = VARYING_SLOT_FACE;
333 }
334 c->input_var_face = var;
335 } else if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
336 if (c->cap_position_is_sysval) {
337 var->data.mode = nir_var_system_value;
338 var->data.location = SYSTEM_VALUE_FRAG_COORD;
339 } else {
340 var->data.location = VARYING_SLOT_POS;
341 }
342 c->input_var_position = var;
343 } else if (decl->Semantic.Name == TGSI_SEMANTIC_PCOORD) {
344 if (c->cap_point_is_sysval) {
345 var->data.mode = nir_var_system_value;
346 var->data.location = SYSTEM_VALUE_POINT_COORD;
347 } else {
348 var->data.location = VARYING_SLOT_PNTC;
349 }
350 c->input_var_point = var;
351 } else {
352 var->data.location =
353 tgsi_varying_semantic_to_slot(decl->Semantic.Name,
354 decl->Semantic.Index);
355 }
356 } else {
357 assert(!decl->Declaration.Semantic);
358 var->data.location = VERT_ATTRIB_GENERIC0 + idx;
359 }
360 var->data.index = 0;
361 var->data.interpolation =
362 ttn_translate_interp_mode(decl->Interp.Interpolate);
363
364 c->inputs[idx] = var;
365
366 for (int i = 0; i < array_size; i++)
367 b->shader->info.inputs_read |= 1ull << (var->data.location + i);
368
369 break;
370 case TGSI_FILE_OUTPUT: {
371 int semantic_name = decl->Semantic.Name;
372 int semantic_index = decl->Semantic.Index;
373 /* Since we can't load from outputs in the IR, we make temporaries
374 * for the outputs and emit stores to the real outputs at the end of
375 * the shader.
376 */
377 nir_register *reg = nir_local_reg_create(b->impl);
378 reg->num_components = 4;
379 if (is_array)
380 reg->num_array_elems = array_size;
381
382 var->data.mode = nir_var_shader_out;
383 var->name = ralloc_asprintf(var, "out_%d", idx);
384 var->data.index = 0;
385 var->data.interpolation =
386 ttn_translate_interp_mode(decl->Interp.Interpolate);
387 var->data.patch = semantic_name == TGSI_SEMANTIC_TESSINNER ||
388 semantic_name == TGSI_SEMANTIC_TESSOUTER ||
389 semantic_name == TGSI_SEMANTIC_PATCH;
390
391 if (c->scan->processor == PIPE_SHADER_FRAGMENT) {
392 switch (semantic_name) {
393 case TGSI_SEMANTIC_COLOR: {
394 /* TODO tgsi loses some information, so we cannot
395 * actually differentiate here between DSB and MRT
396 * at this point. But so far no drivers using tgsi-
397 * to-nir support dual source blend:
398 */
399 bool dual_src_blend = false;
400 if (dual_src_blend && (semantic_index == 1)) {
401 var->data.location = FRAG_RESULT_DATA0;
402 var->data.index = 1;
403 } else {
404 if (c->scan->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
405 var->data.location = FRAG_RESULT_COLOR;
406 else
407 var->data.location = FRAG_RESULT_DATA0 + semantic_index;
408 }
409 break;
410 }
411 case TGSI_SEMANTIC_POSITION:
412 var->data.location = FRAG_RESULT_DEPTH;
413 var->type = glsl_float_type();
414 break;
415 case TGSI_SEMANTIC_STENCIL:
416 var->data.location = FRAG_RESULT_STENCIL;
417 var->type = glsl_int_type();
418 break;
419 case TGSI_SEMANTIC_SAMPLEMASK:
420 var->data.location = FRAG_RESULT_SAMPLE_MASK;
421 var->type = glsl_int_type();
422 break;
423
424 default:
425 fprintf(stderr, "Bad TGSI semantic: %d/%d\n",
426 decl->Semantic.Name, decl->Semantic.Index);
427 abort();
428 }
429 } else {
430 var->data.location =
431 tgsi_varying_semantic_to_slot(semantic_name, semantic_index);
432 if (var->data.location == VARYING_SLOT_FOGC ||
433 var->data.location == VARYING_SLOT_PSIZ) {
434 var->type = glsl_float_type();
435 } else if (var->data.location == VARYING_SLOT_LAYER) {
436 var->type = glsl_int_type();
437 }
438 }
439
440 if (is_array) {
441 unsigned j;
442 for (j = 0; j < array_size; j++) {
443 c->output_regs[idx + j].offset = i + j;
444 c->output_regs[idx + j].reg = reg;
445 }
446 } else {
447 c->output_regs[idx].offset = i;
448 c->output_regs[idx].reg = reg;
449 }
450
451 c->outputs[idx] = var;
452
453 for (int i = 0; i < array_size; i++)
454 b->shader->info.outputs_written |= 1ull << (var->data.location + i);
455 }
456 break;
457 case TGSI_FILE_CONSTANT:
458 var->data.mode = nir_var_uniform;
459 var->name = ralloc_asprintf(var, "uniform_%d", idx);
460 var->data.location = idx;
461 break;
462 default:
463 unreachable("bad declaration file");
464 return;
465 }
466
467 nir_shader_add_variable(b->shader, var);
468
469 if (is_array)
470 break;
471 }
472
473 }
474 }
475
476 static void
ttn_emit_immediate(struct ttn_compile * c)477 ttn_emit_immediate(struct ttn_compile *c)
478 {
479 nir_builder *b = &c->build;
480 struct tgsi_full_immediate *tgsi_imm = &c->token->FullImmediate;
481 nir_load_const_instr *load_const;
482 int i;
483
484 load_const = nir_load_const_instr_create(b->shader, 4, 32);
485 c->imm_defs[c->next_imm] = &load_const->def;
486 c->next_imm++;
487
488 for (i = 0; i < load_const->def.num_components; i++)
489 load_const->value[i].u32 = tgsi_imm->u[i].Uint;
490
491 nir_builder_instr_insert(b, &load_const->instr);
492 }
493
494 static nir_ssa_def *
495 ttn_src_for_indirect(struct ttn_compile *c, struct tgsi_ind_register *indirect);
496
497 /* generate either a constant or indirect deref chain for accessing an
498 * array variable.
499 */
500 static nir_deref_instr *
ttn_array_deref(struct ttn_compile * c,nir_variable * var,unsigned offset,struct tgsi_ind_register * indirect)501 ttn_array_deref(struct ttn_compile *c, nir_variable *var, unsigned offset,
502 struct tgsi_ind_register *indirect)
503 {
504 nir_deref_instr *deref = nir_build_deref_var(&c->build, var);
505 nir_ssa_def *index = nir_imm_int(&c->build, offset);
506 if (indirect)
507 index = nir_iadd(&c->build, index, ttn_src_for_indirect(c, indirect));
508 return nir_build_deref_array(&c->build, deref, index);
509 }
510
511 /* Special case: Turn the frontface varying into a load of the
512 * frontface variable, and create the vector as required by TGSI.
513 */
514 static nir_ssa_def *
ttn_emulate_tgsi_front_face(struct ttn_compile * c)515 ttn_emulate_tgsi_front_face(struct ttn_compile *c)
516 {
517 nir_ssa_def *tgsi_frontface[4];
518
519 if (c->cap_face_is_sysval) {
520 /* When it's a system value, it should be an integer vector: (F, 0, 0, 1)
521 * F is 0xffffffff if front-facing, 0 if not.
522 */
523
524 nir_ssa_def *frontface = nir_load_front_face(&c->build, 1);
525
526 tgsi_frontface[0] = nir_bcsel(&c->build,
527 frontface,
528 nir_imm_int(&c->build, 0xffffffff),
529 nir_imm_int(&c->build, 0));
530 tgsi_frontface[1] = nir_imm_int(&c->build, 0);
531 tgsi_frontface[2] = nir_imm_int(&c->build, 0);
532 tgsi_frontface[3] = nir_imm_int(&c->build, 1);
533 } else {
534 /* When it's an input, it should be a float vector: (F, 0.0, 0.0, 1.0)
535 * F is positive if front-facing, negative if not.
536 */
537
538 assert(c->input_var_face);
539 nir_ssa_def *frontface = nir_load_var(&c->build, c->input_var_face);
540
541 tgsi_frontface[0] = nir_bcsel(&c->build,
542 frontface,
543 nir_imm_float(&c->build, 1.0),
544 nir_imm_float(&c->build, -1.0));
545 tgsi_frontface[1] = nir_imm_float(&c->build, 0.0);
546 tgsi_frontface[2] = nir_imm_float(&c->build, 0.0);
547 tgsi_frontface[3] = nir_imm_float(&c->build, 1.0);
548 }
549
550 return nir_vec(&c->build, tgsi_frontface, 4);
551 }
552
553 static nir_src
ttn_src_for_file_and_index(struct ttn_compile * c,unsigned file,unsigned index,struct tgsi_ind_register * indirect,struct tgsi_dimension * dim,struct tgsi_ind_register * dimind,bool src_is_float)554 ttn_src_for_file_and_index(struct ttn_compile *c, unsigned file, unsigned index,
555 struct tgsi_ind_register *indirect,
556 struct tgsi_dimension *dim,
557 struct tgsi_ind_register *dimind,
558 bool src_is_float)
559 {
560 nir_builder *b = &c->build;
561 nir_src src;
562
563 memset(&src, 0, sizeof(src));
564
565 switch (file) {
566 case TGSI_FILE_TEMPORARY:
567 if (c->temp_regs[index].var) {
568 unsigned offset = c->temp_regs[index].offset;
569 nir_variable *var = c->temp_regs[index].var;
570 nir_ssa_def *load = nir_load_deref(&c->build,
571 ttn_array_deref(c, var, offset, indirect));
572
573 src = nir_src_for_ssa(load);
574 } else {
575 assert(!indirect);
576 src.reg.reg = c->temp_regs[index].reg;
577 }
578 assert(!dim);
579 break;
580
581 case TGSI_FILE_ADDRESS:
582 src.reg.reg = c->addr_reg;
583 assert(!dim);
584 break;
585
586 case TGSI_FILE_IMMEDIATE:
587 src = nir_src_for_ssa(c->imm_defs[index]);
588 assert(!indirect);
589 assert(!dim);
590 break;
591
592 case TGSI_FILE_SYSTEM_VALUE: {
593 nir_ssa_def *load;
594
595 assert(!indirect);
596 assert(!dim);
597
598 switch (c->scan->system_value_semantic_name[index]) {
599 case TGSI_SEMANTIC_VERTEXID_NOBASE:
600 load = nir_load_vertex_id_zero_base(b);
601 break;
602 case TGSI_SEMANTIC_VERTEXID:
603 load = nir_load_vertex_id(b);
604 break;
605 case TGSI_SEMANTIC_BASEVERTEX:
606 load = nir_load_base_vertex(b);
607 break;
608 case TGSI_SEMANTIC_INSTANCEID:
609 load = nir_load_instance_id(b);
610 break;
611 case TGSI_SEMANTIC_FACE:
612 assert(c->cap_face_is_sysval);
613 load = ttn_emulate_tgsi_front_face(c);
614 break;
615 case TGSI_SEMANTIC_POSITION:
616 assert(c->cap_position_is_sysval);
617 load = nir_load_frag_coord(b);
618 break;
619 case TGSI_SEMANTIC_PCOORD:
620 assert(c->cap_point_is_sysval);
621 load = nir_load_point_coord(b);
622 break;
623 case TGSI_SEMANTIC_THREAD_ID:
624 load = nir_load_local_invocation_id(b);
625 break;
626 case TGSI_SEMANTIC_BLOCK_ID:
627 load = nir_load_workgroup_id(b, 32);
628 break;
629 case TGSI_SEMANTIC_BLOCK_SIZE:
630 load = nir_load_workgroup_size(b);
631 break;
632 case TGSI_SEMANTIC_CS_USER_DATA_AMD:
633 load = nir_load_user_data_amd(b);
634 break;
635 case TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL:
636 load = nir_load_tess_level_inner_default(b);
637 break;
638 case TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL:
639 load = nir_load_tess_level_outer_default(b);
640 break;
641 case TGSI_SEMANTIC_SAMPLEID:
642 load = nir_load_sample_id(b);
643 break;
644 default:
645 unreachable("bad system value");
646 }
647
648 if (load->num_components == 2)
649 load = nir_swizzle(b, load, SWIZ(X, Y, Y, Y), 4);
650 else if (load->num_components == 3)
651 load = nir_swizzle(b, load, SWIZ(X, Y, Z, Z), 4);
652
653 src = nir_src_for_ssa(load);
654 break;
655 }
656
657 case TGSI_FILE_INPUT:
658 if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
659 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_FACE) {
660 assert(!c->cap_face_is_sysval && c->input_var_face);
661 return nir_src_for_ssa(ttn_emulate_tgsi_front_face(c));
662 } else if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
663 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_POSITION) {
664 assert(!c->cap_position_is_sysval && c->input_var_position);
665 return nir_src_for_ssa(nir_load_var(&c->build, c->input_var_position));
666 } else if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
667 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_PCOORD) {
668 assert(!c->cap_point_is_sysval && c->input_var_point);
669 return nir_src_for_ssa(nir_load_var(&c->build, c->input_var_point));
670 } else {
671 /* Indirection on input arrays isn't supported by TTN. */
672 assert(!dim);
673 nir_deref_instr *deref = nir_build_deref_var(&c->build,
674 c->inputs[index]);
675 return nir_src_for_ssa(nir_load_deref(&c->build, deref));
676 }
677 break;
678
679 case TGSI_FILE_OUTPUT:
680 if (c->scan->processor == PIPE_SHADER_FRAGMENT) {
681 c->outputs[index]->data.fb_fetch_output = 1;
682 nir_deref_instr *deref = nir_build_deref_var(&c->build,
683 c->outputs[index]);
684 return nir_src_for_ssa(nir_load_deref(&c->build, deref));
685 }
686 unreachable("unsupported output read");
687 break;
688
689 case TGSI_FILE_CONSTANT: {
690 nir_intrinsic_instr *load;
691 nir_intrinsic_op op;
692 unsigned srcn = 0;
693
694 if (dim && (dim->Index > 0 || dim->Indirect)) {
695 op = nir_intrinsic_load_ubo;
696 } else {
697 op = nir_intrinsic_load_uniform;
698 }
699
700 load = nir_intrinsic_instr_create(b->shader, op);
701 if (op == nir_intrinsic_load_uniform) {
702 nir_intrinsic_set_dest_type(load, src_is_float ? nir_type_float :
703 nir_type_int);
704 }
705
706 load->num_components = 4;
707 if (dim && (dim->Index > 0 || dim->Indirect)) {
708 if (dimind) {
709 load->src[srcn] =
710 ttn_src_for_file_and_index(c, dimind->File, dimind->Index,
711 NULL, NULL, NULL, false);
712 } else {
713 /* UBOs start at index 1 in TGSI: */
714 load->src[srcn] =
715 nir_src_for_ssa(nir_imm_int(b, dim->Index - 1));
716 }
717 srcn++;
718 }
719
720 nir_ssa_def *offset;
721 if (op == nir_intrinsic_load_ubo) {
722 /* UBO loads don't have a base offset. */
723 offset = nir_imm_int(b, index);
724 if (indirect) {
725 offset = nir_iadd(b, offset, ttn_src_for_indirect(c, indirect));
726 }
727 /* UBO offsets are in bytes, but TGSI gives them to us in vec4's */
728 offset = nir_ishl(b, offset, nir_imm_int(b, 4));
729 nir_intrinsic_set_align(load, 16, 0);
730
731 /* Set a very conservative base/range of the access: 16 bytes if not
732 * indirect at all, offset to the end of the UBO if the offset is
733 * indirect, and totally unknown if the block number is indirect.
734 */
735 uint32_t base = index * 16;
736 nir_intrinsic_set_range_base(load, base);
737 if (dimind)
738 nir_intrinsic_set_range(load, ~0);
739 else if (indirect)
740 nir_intrinsic_set_range(load, c->ubo_sizes[dim->Index] - base);
741 else
742 nir_intrinsic_set_range(load, base + 16);
743 } else {
744 nir_intrinsic_set_base(load, index);
745 if (indirect) {
746 offset = ttn_src_for_indirect(c, indirect);
747 nir_intrinsic_set_range(load, c->build.shader->num_uniforms * 16 - index);
748 } else {
749 offset = nir_imm_int(b, 0);
750 nir_intrinsic_set_range(load, 1);
751 }
752 }
753 load->src[srcn++] = nir_src_for_ssa(offset);
754
755 nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
756 nir_builder_instr_insert(b, &load->instr);
757
758 src = nir_src_for_ssa(&load->dest.ssa);
759 break;
760 }
761
762 default:
763 unreachable("bad src file");
764 }
765
766
767 return src;
768 }
769
770 static nir_ssa_def *
ttn_src_for_indirect(struct ttn_compile * c,struct tgsi_ind_register * indirect)771 ttn_src_for_indirect(struct ttn_compile *c, struct tgsi_ind_register *indirect)
772 {
773 nir_builder *b = &c->build;
774 nir_alu_src src;
775 memset(&src, 0, sizeof(src));
776 for (int i = 0; i < 4; i++)
777 src.swizzle[i] = indirect->Swizzle;
778 src.src = ttn_src_for_file_and_index(c,
779 indirect->File,
780 indirect->Index,
781 NULL, NULL, NULL,
782 false);
783 return nir_mov_alu(b, src, 1);
784 }
785
786 static nir_alu_dest
ttn_get_dest(struct ttn_compile * c,struct tgsi_full_dst_register * tgsi_fdst)787 ttn_get_dest(struct ttn_compile *c, struct tgsi_full_dst_register *tgsi_fdst)
788 {
789 struct tgsi_dst_register *tgsi_dst = &tgsi_fdst->Register;
790 nir_alu_dest dest;
791 unsigned index = tgsi_dst->Index;
792
793 memset(&dest, 0, sizeof(dest));
794
795 if (tgsi_dst->File == TGSI_FILE_TEMPORARY) {
796 if (c->temp_regs[index].var) {
797 nir_register *reg;
798
799 /* this works, because TGSI will give us a base offset
800 * (in case of indirect index) that points back into
801 * the array. Access can be direct or indirect, we
802 * don't really care. Just create a one-shot dst reg
803 * that will get store_var'd back into the array var
804 * at the end of ttn_emit_instruction()
805 */
806 reg = nir_local_reg_create(c->build.impl);
807 reg->num_components = 4;
808 dest.dest.reg.reg = reg;
809 dest.dest.reg.base_offset = 0;
810 } else {
811 assert(!tgsi_dst->Indirect);
812 dest.dest.reg.reg = c->temp_regs[index].reg;
813 dest.dest.reg.base_offset = c->temp_regs[index].offset;
814 }
815 } else if (tgsi_dst->File == TGSI_FILE_OUTPUT) {
816 dest.dest.reg.reg = c->output_regs[index].reg;
817 dest.dest.reg.base_offset = c->output_regs[index].offset;
818 } else if (tgsi_dst->File == TGSI_FILE_ADDRESS) {
819 assert(index == 0);
820 dest.dest.reg.reg = c->addr_reg;
821 }
822
823 dest.write_mask = tgsi_dst->WriteMask;
824 dest.saturate = false;
825
826 if (tgsi_dst->Indirect && (tgsi_dst->File != TGSI_FILE_TEMPORARY)) {
827 nir_src *indirect = malloc(sizeof(nir_src));
828 *indirect = nir_src_for_ssa(ttn_src_for_indirect(c, &tgsi_fdst->Indirect));
829 dest.dest.reg.indirect = indirect;
830 }
831
832 return dest;
833 }
834
835 static nir_variable *
ttn_get_var(struct ttn_compile * c,struct tgsi_full_dst_register * tgsi_fdst)836 ttn_get_var(struct ttn_compile *c, struct tgsi_full_dst_register *tgsi_fdst)
837 {
838 struct tgsi_dst_register *tgsi_dst = &tgsi_fdst->Register;
839 unsigned index = tgsi_dst->Index;
840
841 if (tgsi_dst->File == TGSI_FILE_TEMPORARY) {
842 /* we should not have an indirect when there is no var! */
843 if (!c->temp_regs[index].var)
844 assert(!tgsi_dst->Indirect);
845 return c->temp_regs[index].var;
846 }
847
848 return NULL;
849 }
850
851 static nir_ssa_def *
ttn_get_src(struct ttn_compile * c,struct tgsi_full_src_register * tgsi_fsrc,int src_idx)852 ttn_get_src(struct ttn_compile *c, struct tgsi_full_src_register *tgsi_fsrc,
853 int src_idx)
854 {
855 nir_builder *b = &c->build;
856 struct tgsi_src_register *tgsi_src = &tgsi_fsrc->Register;
857 enum tgsi_opcode opcode = c->token->FullInstruction.Instruction.Opcode;
858 unsigned tgsi_src_type = tgsi_opcode_infer_src_type(opcode, src_idx);
859 bool src_is_float = (tgsi_src_type == TGSI_TYPE_FLOAT ||
860 tgsi_src_type == TGSI_TYPE_DOUBLE ||
861 tgsi_src_type == TGSI_TYPE_UNTYPED);
862 nir_alu_src src;
863
864 memset(&src, 0, sizeof(src));
865
866 if (tgsi_src->File == TGSI_FILE_NULL) {
867 return nir_imm_float(b, 0.0);
868 } else if (tgsi_src->File == TGSI_FILE_SAMPLER ||
869 tgsi_src->File == TGSI_FILE_IMAGE ||
870 tgsi_src->File == TGSI_FILE_BUFFER) {
871 /* Only the index of the resource gets used in texturing, and it will
872 * handle looking that up on its own instead of using the nir_alu_src.
873 */
874 assert(!tgsi_src->Indirect);
875 return NULL;
876 } else {
877 struct tgsi_ind_register *ind = NULL;
878 struct tgsi_dimension *dim = NULL;
879 struct tgsi_ind_register *dimind = NULL;
880 if (tgsi_src->Indirect)
881 ind = &tgsi_fsrc->Indirect;
882 if (tgsi_src->Dimension) {
883 dim = &tgsi_fsrc->Dimension;
884 if (dim->Indirect)
885 dimind = &tgsi_fsrc->DimIndirect;
886 }
887 src.src = ttn_src_for_file_and_index(c,
888 tgsi_src->File,
889 tgsi_src->Index,
890 ind, dim, dimind,
891 src_is_float);
892 }
893
894 src.swizzle[0] = tgsi_src->SwizzleX;
895 src.swizzle[1] = tgsi_src->SwizzleY;
896 src.swizzle[2] = tgsi_src->SwizzleZ;
897 src.swizzle[3] = tgsi_src->SwizzleW;
898
899 nir_ssa_def *def = nir_mov_alu(b, src, 4);
900
901 if (tgsi_type_is_64bit(tgsi_src_type))
902 def = nir_bitcast_vector(b, def, 64);
903
904 if (tgsi_src->Absolute) {
905 assert(src_is_float);
906 def = nir_fabs(b, def);
907 }
908
909 if (tgsi_src->Negate) {
910 if (src_is_float)
911 def = nir_fneg(b, def);
912 else
913 def = nir_ineg(b, def);
914 }
915
916 return def;
917 }
918
919 static void
ttn_move_dest_masked(nir_builder * b,nir_alu_dest dest,nir_ssa_def * def,unsigned write_mask)920 ttn_move_dest_masked(nir_builder *b, nir_alu_dest dest,
921 nir_ssa_def *def, unsigned write_mask)
922 {
923 if (!(dest.write_mask & write_mask))
924 return;
925
926 nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_mov);
927 mov->dest = dest;
928 mov->dest.write_mask &= write_mask;
929 mov->src[0].src = nir_src_for_ssa(def);
930 for (unsigned i = def->num_components; i < 4; i++)
931 mov->src[0].swizzle[i] = def->num_components - 1;
932 nir_builder_instr_insert(b, &mov->instr);
933 }
934
935 static void
ttn_move_dest(nir_builder * b,nir_alu_dest dest,nir_ssa_def * def)936 ttn_move_dest(nir_builder *b, nir_alu_dest dest, nir_ssa_def *def)
937 {
938 ttn_move_dest_masked(b, dest, def, TGSI_WRITEMASK_XYZW);
939 }
940
941 static void
ttn_alu(nir_builder * b,nir_op op,nir_alu_dest dest,unsigned dest_bitsize,nir_ssa_def ** src)942 ttn_alu(nir_builder *b, nir_op op, nir_alu_dest dest, unsigned dest_bitsize,
943 nir_ssa_def **src)
944 {
945 nir_ssa_def *def = nir_build_alu_src_arr(b, op, src);
946 if (def->bit_size == 1)
947 def = nir_ineg(b, nir_b2i(b, def, dest_bitsize));
948 assert(def->bit_size == dest_bitsize);
949 if (dest_bitsize == 64) {
950 if (def->num_components > 2) {
951 /* 32 -> 64 bit conversion ops are supposed to only convert the first
952 * two components, and we need to truncate here to avoid creating a
953 * vec8 after bitcasting the destination.
954 */
955 def = nir_channels(b, def, 0x3);
956 }
957 def = nir_bitcast_vector(b, def, 32);
958 }
959 ttn_move_dest(b, dest, def);
960 }
961
962 static void
ttn_arl(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)963 ttn_arl(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
964 {
965 ttn_move_dest(b, dest, nir_f2i32(b, nir_ffloor(b, src[0])));
966 }
967
968 /* EXP - Approximate Exponential Base 2
969 * dst.x = 2^{\lfloor src.x\rfloor}
970 * dst.y = src.x - \lfloor src.x\rfloor
971 * dst.z = 2^{src.x}
972 * dst.w = 1.0
973 */
974 static void
ttn_exp(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)975 ttn_exp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
976 {
977 nir_ssa_def *srcx = ttn_channel(b, src[0], X);
978
979 ttn_move_dest_masked(b, dest, nir_fexp2(b, nir_ffloor(b, srcx)),
980 TGSI_WRITEMASK_X);
981 ttn_move_dest_masked(b, dest, nir_fsub(b, srcx, nir_ffloor(b, srcx)),
982 TGSI_WRITEMASK_Y);
983 ttn_move_dest_masked(b, dest, nir_fexp2(b, srcx), TGSI_WRITEMASK_Z);
984 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_W);
985 }
986
987 /* LOG - Approximate Logarithm Base 2
988 * dst.x = \lfloor\log_2{|src.x|}\rfloor
989 * dst.y = \frac{|src.x|}{2^{\lfloor\log_2{|src.x|}\rfloor}}
990 * dst.z = \log_2{|src.x|}
991 * dst.w = 1.0
992 */
993 static void
ttn_log(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)994 ttn_log(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
995 {
996 nir_ssa_def *abs_srcx = nir_fabs(b, ttn_channel(b, src[0], X));
997 nir_ssa_def *log2 = nir_flog2(b, abs_srcx);
998
999 ttn_move_dest_masked(b, dest, nir_ffloor(b, log2), TGSI_WRITEMASK_X);
1000 ttn_move_dest_masked(b, dest,
1001 nir_fdiv(b, abs_srcx, nir_fexp2(b, nir_ffloor(b, log2))),
1002 TGSI_WRITEMASK_Y);
1003 ttn_move_dest_masked(b, dest, nir_flog2(b, abs_srcx), TGSI_WRITEMASK_Z);
1004 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_W);
1005 }
1006
1007 /* DST - Distance Vector
1008 * dst.x = 1.0
1009 * dst.y = src0.y \times src1.y
1010 * dst.z = src0.z
1011 * dst.w = src1.w
1012 */
1013 static void
ttn_dst(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1014 ttn_dst(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1015 {
1016 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_X);
1017 ttn_move_dest_masked(b, dest, nir_fmul(b, src[0], src[1]), TGSI_WRITEMASK_Y);
1018 ttn_move_dest_masked(b, dest, nir_mov(b, src[0]), TGSI_WRITEMASK_Z);
1019 ttn_move_dest_masked(b, dest, nir_mov(b, src[1]), TGSI_WRITEMASK_W);
1020 }
1021
1022 /* LIT - Light Coefficients
1023 * dst.x = 1.0
1024 * dst.y = max(src.x, 0.0)
1025 * dst.z = (src.x > 0.0) ? max(src.y, 0.0)^{clamp(src.w, -128.0, 128.0))} : 0
1026 * dst.w = 1.0
1027 */
1028 static void
ttn_lit(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1029 ttn_lit(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1030 {
1031 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_XW);
1032
1033 ttn_move_dest_masked(b, dest, nir_fmax(b, ttn_channel(b, src[0], X),
1034 nir_imm_float(b, 0.0)), TGSI_WRITEMASK_Y);
1035
1036 if (dest.write_mask & TGSI_WRITEMASK_Z) {
1037 nir_ssa_def *src0_y = ttn_channel(b, src[0], Y);
1038 nir_ssa_def *wclamp = nir_fmax(b, nir_fmin(b, ttn_channel(b, src[0], W),
1039 nir_imm_float(b, 128.0)),
1040 nir_imm_float(b, -128.0));
1041 nir_ssa_def *pow = nir_fpow(b, nir_fmax(b, src0_y, nir_imm_float(b, 0.0)),
1042 wclamp);
1043
1044 ttn_move_dest_masked(b, dest,
1045 nir_bcsel(b,
1046 nir_flt(b,
1047 ttn_channel(b, src[0], X),
1048 nir_imm_float(b, 0.0)),
1049 nir_imm_float(b, 0.0),
1050 pow),
1051 TGSI_WRITEMASK_Z);
1052 }
1053 }
1054
1055 static void
ttn_sle(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1056 ttn_sle(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1057 {
1058 ttn_move_dest(b, dest, nir_sge(b, src[1], src[0]));
1059 }
1060
1061 static void
ttn_sgt(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1062 ttn_sgt(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1063 {
1064 ttn_move_dest(b, dest, nir_slt(b, src[1], src[0]));
1065 }
1066
1067 static void
ttn_dp2(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1068 ttn_dp2(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1069 {
1070 ttn_move_dest(b, dest, nir_fdot2(b, src[0], src[1]));
1071 }
1072
1073 static void
ttn_dp3(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1074 ttn_dp3(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1075 {
1076 ttn_move_dest(b, dest, nir_fdot3(b, src[0], src[1]));
1077 }
1078
1079 static void
ttn_dp4(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1080 ttn_dp4(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1081 {
1082 ttn_move_dest(b, dest, nir_fdot4(b, src[0], src[1]));
1083 }
1084
1085 static void
ttn_umad(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1086 ttn_umad(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1087 {
1088 ttn_move_dest(b, dest, nir_iadd(b, nir_imul(b, src[0], src[1]), src[2]));
1089 }
1090
1091 static void
ttn_arr(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1092 ttn_arr(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1093 {
1094 ttn_move_dest(b, dest, nir_f2i32(b, nir_fround_even(b, src[0])));
1095 }
1096
1097 static void
ttn_cmp(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1098 ttn_cmp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1099 {
1100 ttn_move_dest(b, dest, nir_bcsel(b,
1101 nir_flt(b, src[0], nir_imm_float(b, 0.0)),
1102 src[1], src[2]));
1103 }
1104
1105 static void
ttn_ucmp(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1106 ttn_ucmp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1107 {
1108 ttn_move_dest(b, dest, nir_bcsel(b,
1109 nir_ine(b, src[0], nir_imm_int(b, 0)),
1110 src[1], src[2]));
1111 }
1112
1113 static void
ttn_barrier(nir_builder * b)1114 ttn_barrier(nir_builder *b)
1115 {
1116 nir_control_barrier(b);
1117 }
1118
1119 static void
ttn_kill(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1120 ttn_kill(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1121 {
1122 nir_discard(b);
1123 b->shader->info.fs.uses_discard = true;
1124 }
1125
1126 static void
ttn_kill_if(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1127 ttn_kill_if(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1128 {
1129 /* flt must be exact, because NaN shouldn't discard. (apps rely on this) */
1130 b->exact = true;
1131 nir_ssa_def *cmp = nir_bany(b, nir_flt(b, src[0], nir_imm_float(b, 0.0)));
1132 b->exact = false;
1133
1134 nir_discard_if(b, cmp);
1135 b->shader->info.fs.uses_discard = true;
1136 }
1137
1138 static void
get_texture_info(unsigned texture,enum glsl_sampler_dim * dim,bool * is_shadow,bool * is_array)1139 get_texture_info(unsigned texture,
1140 enum glsl_sampler_dim *dim,
1141 bool *is_shadow,
1142 bool *is_array)
1143 {
1144 assert(is_array);
1145 *is_array = false;
1146
1147 if (is_shadow)
1148 *is_shadow = false;
1149
1150 switch (texture) {
1151 case TGSI_TEXTURE_BUFFER:
1152 *dim = GLSL_SAMPLER_DIM_BUF;
1153 break;
1154 case TGSI_TEXTURE_1D:
1155 *dim = GLSL_SAMPLER_DIM_1D;
1156 break;
1157 case TGSI_TEXTURE_1D_ARRAY:
1158 *dim = GLSL_SAMPLER_DIM_1D;
1159 *is_array = true;
1160 break;
1161 case TGSI_TEXTURE_SHADOW1D:
1162 *dim = GLSL_SAMPLER_DIM_1D;
1163 *is_shadow = true;
1164 break;
1165 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1166 *dim = GLSL_SAMPLER_DIM_1D;
1167 *is_shadow = true;
1168 *is_array = true;
1169 break;
1170 case TGSI_TEXTURE_2D:
1171 *dim = GLSL_SAMPLER_DIM_2D;
1172 break;
1173 case TGSI_TEXTURE_2D_ARRAY:
1174 *dim = GLSL_SAMPLER_DIM_2D;
1175 *is_array = true;
1176 break;
1177 case TGSI_TEXTURE_2D_MSAA:
1178 *dim = GLSL_SAMPLER_DIM_MS;
1179 break;
1180 case TGSI_TEXTURE_2D_ARRAY_MSAA:
1181 *dim = GLSL_SAMPLER_DIM_MS;
1182 *is_array = true;
1183 break;
1184 case TGSI_TEXTURE_SHADOW2D:
1185 *dim = GLSL_SAMPLER_DIM_2D;
1186 *is_shadow = true;
1187 break;
1188 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1189 *dim = GLSL_SAMPLER_DIM_2D;
1190 *is_shadow = true;
1191 *is_array = true;
1192 break;
1193 case TGSI_TEXTURE_3D:
1194 *dim = GLSL_SAMPLER_DIM_3D;
1195 break;
1196 case TGSI_TEXTURE_CUBE:
1197 *dim = GLSL_SAMPLER_DIM_CUBE;
1198 break;
1199 case TGSI_TEXTURE_CUBE_ARRAY:
1200 *dim = GLSL_SAMPLER_DIM_CUBE;
1201 *is_array = true;
1202 break;
1203 case TGSI_TEXTURE_SHADOWCUBE:
1204 *dim = GLSL_SAMPLER_DIM_CUBE;
1205 *is_shadow = true;
1206 break;
1207 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1208 *dim = GLSL_SAMPLER_DIM_CUBE;
1209 *is_shadow = true;
1210 *is_array = true;
1211 break;
1212 case TGSI_TEXTURE_RECT:
1213 *dim = GLSL_SAMPLER_DIM_RECT;
1214 break;
1215 case TGSI_TEXTURE_SHADOWRECT:
1216 *dim = GLSL_SAMPLER_DIM_RECT;
1217 *is_shadow = true;
1218 break;
1219 default:
1220 fprintf(stderr, "Unknown TGSI texture target %d\n", texture);
1221 abort();
1222 }
1223 }
1224
1225 static enum glsl_base_type
base_type_for_alu_type(nir_alu_type type)1226 base_type_for_alu_type(nir_alu_type type)
1227 {
1228 type = nir_alu_type_get_base_type(type);
1229
1230 switch (type) {
1231 case nir_type_float:
1232 return GLSL_TYPE_FLOAT;
1233 case nir_type_int:
1234 return GLSL_TYPE_INT;
1235 case nir_type_uint:
1236 return GLSL_TYPE_UINT;
1237 default:
1238 unreachable("invalid type");
1239 }
1240 }
1241
1242 static nir_variable *
get_sampler_var(struct ttn_compile * c,int binding,enum glsl_sampler_dim dim,bool is_shadow,bool is_array,enum glsl_base_type base_type,nir_texop op)1243 get_sampler_var(struct ttn_compile *c, int binding,
1244 enum glsl_sampler_dim dim,
1245 bool is_shadow,
1246 bool is_array,
1247 enum glsl_base_type base_type,
1248 nir_texop op)
1249 {
1250 nir_variable *var = c->samplers[binding];
1251 if (!var) {
1252 const struct glsl_type *type =
1253 glsl_sampler_type(dim, is_shadow, is_array, base_type);
1254 var = nir_variable_create(c->build.shader, nir_var_uniform, type,
1255 "sampler");
1256 var->data.binding = binding;
1257 var->data.explicit_binding = true;
1258
1259 c->samplers[binding] = var;
1260 c->num_samplers = MAX2(c->num_samplers, binding + 1);
1261
1262 /* Record textures used */
1263 BITSET_SET(c->build.shader->info.textures_used, binding);
1264 if (op == nir_texop_txf || op == nir_texop_txf_ms)
1265 BITSET_SET(c->build.shader->info.textures_used_by_txf, binding);
1266 BITSET_SET(c->build.shader->info.samplers_used, binding);
1267 }
1268
1269 return var;
1270 }
1271
1272 static nir_variable *
get_image_var(struct ttn_compile * c,int binding,enum glsl_sampler_dim dim,bool is_array,enum glsl_base_type base_type,enum gl_access_qualifier access,enum pipe_format format)1273 get_image_var(struct ttn_compile *c, int binding,
1274 enum glsl_sampler_dim dim,
1275 bool is_array,
1276 enum glsl_base_type base_type,
1277 enum gl_access_qualifier access,
1278 enum pipe_format format)
1279 {
1280 nir_variable *var = c->images[binding];
1281
1282 if (!var) {
1283 const struct glsl_type *type = glsl_image_type(dim, is_array, base_type);
1284
1285 var = nir_variable_create(c->build.shader, nir_var_image, type, "image");
1286 var->data.binding = binding;
1287 var->data.explicit_binding = true;
1288 var->data.access = access;
1289 var->data.image.format = format;
1290
1291 c->images[binding] = var;
1292 c->num_images = MAX2(c->num_images, binding + 1);
1293 if (dim == GLSL_SAMPLER_DIM_MS)
1294 c->num_msaa_images = c->num_images;
1295 }
1296
1297 return var;
1298 }
1299
1300 static void
add_ssbo_var(struct ttn_compile * c,int binding)1301 add_ssbo_var(struct ttn_compile *c, int binding)
1302 {
1303 nir_variable *var = c->ssbo[binding];
1304
1305 if (!var) {
1306 /* A length of 0 is used to denote unsized arrays */
1307 const struct glsl_type *type = glsl_array_type(glsl_uint_type(), 0, 0);
1308
1309 struct glsl_struct_field field = {
1310 .type = type,
1311 .name = "data",
1312 .location = -1,
1313 };
1314
1315 var = nir_variable_create(c->build.shader, nir_var_mem_ssbo, type, "ssbo");
1316 var->data.binding = binding;
1317 var->interface_type =
1318 glsl_interface_type(&field, 1, GLSL_INTERFACE_PACKING_STD430,
1319 false, "data");
1320 c->ssbo[binding] = var;
1321 }
1322 }
1323
1324 static void
ttn_tex(struct ttn_compile * c,nir_alu_dest dest,nir_ssa_def ** src)1325 ttn_tex(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1326 {
1327 nir_builder *b = &c->build;
1328 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1329 nir_tex_instr *instr;
1330 nir_texop op;
1331 unsigned num_srcs, samp = 1, sview, i;
1332
1333 switch (tgsi_inst->Instruction.Opcode) {
1334 case TGSI_OPCODE_TEX:
1335 op = nir_texop_tex;
1336 num_srcs = 1;
1337 break;
1338 case TGSI_OPCODE_TEX2:
1339 op = nir_texop_tex;
1340 num_srcs = 1;
1341 samp = 2;
1342 break;
1343 case TGSI_OPCODE_TXP:
1344 op = nir_texop_tex;
1345 num_srcs = 2;
1346 break;
1347 case TGSI_OPCODE_TXB:
1348 op = nir_texop_txb;
1349 num_srcs = 2;
1350 break;
1351 case TGSI_OPCODE_TXB2:
1352 op = nir_texop_txb;
1353 num_srcs = 2;
1354 samp = 2;
1355 break;
1356 case TGSI_OPCODE_TXL:
1357 case TGSI_OPCODE_TEX_LZ:
1358 op = nir_texop_txl;
1359 num_srcs = 2;
1360 break;
1361 case TGSI_OPCODE_TXL2:
1362 op = nir_texop_txl;
1363 num_srcs = 2;
1364 samp = 2;
1365 break;
1366 case TGSI_OPCODE_TXF:
1367 case TGSI_OPCODE_TXF_LZ:
1368 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
1369 tgsi_inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1370 op = nir_texop_txf_ms;
1371 } else {
1372 op = nir_texop_txf;
1373 }
1374 num_srcs = 2;
1375 break;
1376 case TGSI_OPCODE_TXD:
1377 op = nir_texop_txd;
1378 num_srcs = 3;
1379 samp = 3;
1380 break;
1381 case TGSI_OPCODE_LODQ:
1382 op = nir_texop_lod;
1383 num_srcs = 1;
1384 break;
1385
1386 default:
1387 fprintf(stderr, "unknown TGSI tex op %d\n", tgsi_inst->Instruction.Opcode);
1388 abort();
1389 }
1390
1391 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
1392 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1393 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
1394 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1395 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
1396 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
1397 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1398 num_srcs++;
1399 }
1400
1401 /* Deref sources */
1402 num_srcs += 2;
1403
1404 num_srcs += tgsi_inst->Texture.NumOffsets;
1405
1406 instr = nir_tex_instr_create(b->shader, num_srcs);
1407 instr->op = op;
1408
1409 get_texture_info(tgsi_inst->Texture.Texture,
1410 &instr->sampler_dim, &instr->is_shadow, &instr->is_array);
1411
1412 instr->coord_components =
1413 glsl_get_sampler_dim_coordinate_components(instr->sampler_dim);
1414
1415 if (instr->is_array)
1416 instr->coord_components++;
1417
1418 assert(tgsi_inst->Src[samp].Register.File == TGSI_FILE_SAMPLER);
1419
1420 /* TODO if we supported any opc's which take an explicit SVIEW
1421 * src, we would use that here instead. But for the "legacy"
1422 * texture opc's the SVIEW index is same as SAMP index:
1423 */
1424 sview = tgsi_inst->Src[samp].Register.Index;
1425
1426 if (op == nir_texop_lod) {
1427 instr->dest_type = nir_type_float32;
1428 } else if (sview < c->num_samp_types) {
1429 instr->dest_type = c->samp_types[sview];
1430 } else {
1431 instr->dest_type = nir_type_float32;
1432 }
1433
1434 nir_variable *var =
1435 get_sampler_var(c, sview, instr->sampler_dim,
1436 instr->is_shadow,
1437 instr->is_array,
1438 base_type_for_alu_type(instr->dest_type),
1439 op);
1440
1441 nir_deref_instr *deref = nir_build_deref_var(b, var);
1442
1443 unsigned src_number = 0;
1444
1445 instr->src[src_number].src = nir_src_for_ssa(&deref->dest.ssa);
1446 instr->src[src_number].src_type = nir_tex_src_texture_deref;
1447 src_number++;
1448 instr->src[src_number].src = nir_src_for_ssa(&deref->dest.ssa);
1449 instr->src[src_number].src_type = nir_tex_src_sampler_deref;
1450 src_number++;
1451
1452 instr->src[src_number].src =
1453 nir_src_for_ssa(nir_swizzle(b, src[0], SWIZ(X, Y, Z, W),
1454 instr->coord_components));
1455 instr->src[src_number].src_type = nir_tex_src_coord;
1456 src_number++;
1457
1458 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1459 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1460 instr->src[src_number].src_type = nir_tex_src_projector;
1461 src_number++;
1462 }
1463
1464 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB) {
1465 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1466 instr->src[src_number].src_type = nir_tex_src_bias;
1467 src_number++;
1468 }
1469
1470 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB2) {
1471 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1472 instr->src[src_number].src_type = nir_tex_src_bias;
1473 src_number++;
1474 }
1475
1476 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
1477 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TEX_LZ) {
1478 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TEX_LZ)
1479 instr->src[src_number].src = nir_src_for_ssa(nir_imm_int(b, 0));
1480 else
1481 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1482 instr->src[src_number].src_type = nir_tex_src_lod;
1483 src_number++;
1484 }
1485
1486 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
1487 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1488 instr->src[src_number].src_type = nir_tex_src_lod;
1489 src_number++;
1490 }
1491
1492 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF ||
1493 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF_LZ) {
1494 if (op == nir_texop_txf_ms) {
1495 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1496 instr->src[src_number].src_type = nir_tex_src_ms_index;
1497 } else {
1498 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF_LZ)
1499 instr->src[src_number].src = nir_src_for_ssa(nir_imm_int(b, 0));
1500 else
1501 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1502 instr->src[src_number].src_type = nir_tex_src_lod;
1503 }
1504 src_number++;
1505 }
1506
1507 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
1508 instr->src[src_number].src_type = nir_tex_src_ddx;
1509 instr->src[src_number].src =
1510 nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W),
1511 nir_tex_instr_src_size(instr, src_number)));
1512 src_number++;
1513 instr->src[src_number].src_type = nir_tex_src_ddy;
1514 instr->src[src_number].src =
1515 nir_src_for_ssa(nir_swizzle(b, src[2], SWIZ(X, Y, Z, W),
1516 nir_tex_instr_src_size(instr, src_number)));
1517 src_number++;
1518 }
1519
1520 if (instr->is_shadow) {
1521 if (instr->coord_components == 4)
1522 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1523 else if (instr->coord_components == 3)
1524 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1525 else
1526 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], Z));
1527
1528 instr->src[src_number].src_type = nir_tex_src_comparator;
1529 src_number++;
1530 }
1531
1532 for (i = 0; i < tgsi_inst->Texture.NumOffsets; i++) {
1533 struct tgsi_texture_offset *tex_offset = &tgsi_inst->TexOffsets[i];
1534 /* since TexOffset ins't using tgsi_full_src_register we get to
1535 * do some extra gymnastics:
1536 */
1537 nir_alu_src src;
1538
1539 memset(&src, 0, sizeof(src));
1540
1541 src.src = ttn_src_for_file_and_index(c,
1542 tex_offset->File,
1543 tex_offset->Index,
1544 NULL, NULL, NULL,
1545 true);
1546
1547 src.swizzle[0] = tex_offset->SwizzleX;
1548 src.swizzle[1] = tex_offset->SwizzleY;
1549 src.swizzle[2] = tex_offset->SwizzleZ;
1550 src.swizzle[3] = TGSI_SWIZZLE_W;
1551
1552 instr->src[src_number].src_type = nir_tex_src_offset;
1553 instr->src[src_number].src = nir_src_for_ssa(
1554 nir_mov_alu(b, src, nir_tex_instr_src_size(instr, src_number)));
1555 src_number++;
1556 }
1557
1558 assert(src_number == num_srcs);
1559 assert(src_number == instr->num_srcs);
1560
1561 nir_ssa_dest_init(&instr->instr, &instr->dest,
1562 nir_tex_instr_dest_size(instr),
1563 32, NULL);
1564 nir_builder_instr_insert(b, &instr->instr);
1565
1566 /* Resolve the writemask on the texture op. */
1567 ttn_move_dest(b, dest, &instr->dest.ssa);
1568 }
1569
1570 /* TGSI_OPCODE_TXQ is actually two distinct operations:
1571 *
1572 * dst.x = texture\_width(unit, lod)
1573 * dst.y = texture\_height(unit, lod)
1574 * dst.z = texture\_depth(unit, lod)
1575 * dst.w = texture\_levels(unit)
1576 *
1577 * dst.xyz map to NIR txs opcode, and dst.w maps to query_levels
1578 */
1579 static void
ttn_txq(struct ttn_compile * c,nir_alu_dest dest,nir_ssa_def ** src)1580 ttn_txq(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1581 {
1582 nir_builder *b = &c->build;
1583 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1584 nir_tex_instr *txs, *qlv;
1585
1586 txs = nir_tex_instr_create(b->shader, 2);
1587 txs->op = nir_texop_txs;
1588 txs->dest_type = nir_type_uint32;
1589 get_texture_info(tgsi_inst->Texture.Texture,
1590 &txs->sampler_dim, &txs->is_shadow, &txs->is_array);
1591
1592 qlv = nir_tex_instr_create(b->shader, 1);
1593 qlv->op = nir_texop_query_levels;
1594 qlv->dest_type = nir_type_uint32;
1595 get_texture_info(tgsi_inst->Texture.Texture,
1596 &qlv->sampler_dim, &qlv->is_shadow, &qlv->is_array);
1597
1598 assert(tgsi_inst->Src[1].Register.File == TGSI_FILE_SAMPLER);
1599 int tex_index = tgsi_inst->Src[1].Register.Index;
1600
1601 nir_variable *var =
1602 get_sampler_var(c, tex_index, txs->sampler_dim,
1603 txs->is_shadow,
1604 txs->is_array,
1605 base_type_for_alu_type(txs->dest_type),
1606 nir_texop_txs);
1607
1608 nir_deref_instr *deref = nir_build_deref_var(b, var);
1609
1610 txs->src[0].src = nir_src_for_ssa(&deref->dest.ssa);
1611 txs->src[0].src_type = nir_tex_src_texture_deref;
1612
1613 qlv->src[0].src = nir_src_for_ssa(&deref->dest.ssa);
1614 qlv->src[0].src_type = nir_tex_src_texture_deref;
1615
1616 /* lod: */
1617 txs->src[1].src = nir_src_for_ssa(ttn_channel(b, src[0], X));
1618 txs->src[1].src_type = nir_tex_src_lod;
1619
1620 nir_ssa_dest_init(&txs->instr, &txs->dest,
1621 nir_tex_instr_dest_size(txs), 32, NULL);
1622 nir_builder_instr_insert(b, &txs->instr);
1623
1624 nir_ssa_dest_init(&qlv->instr, &qlv->dest, 1, 32, NULL);
1625 nir_builder_instr_insert(b, &qlv->instr);
1626
1627 ttn_move_dest_masked(b, dest, &txs->dest.ssa, TGSI_WRITEMASK_XYZ);
1628 ttn_move_dest_masked(b, dest, &qlv->dest.ssa, TGSI_WRITEMASK_W);
1629 }
1630
1631 static enum glsl_base_type
get_image_base_type(struct tgsi_full_instruction * tgsi_inst)1632 get_image_base_type(struct tgsi_full_instruction *tgsi_inst)
1633 {
1634 const struct util_format_description *desc =
1635 util_format_description(tgsi_inst->Memory.Format);
1636
1637 if (desc->channel[0].pure_integer) {
1638 if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED)
1639 return GLSL_TYPE_INT;
1640 else
1641 return GLSL_TYPE_UINT;
1642 }
1643 return GLSL_TYPE_FLOAT;
1644 }
1645
1646 static enum gl_access_qualifier
get_mem_qualifier(struct tgsi_full_instruction * tgsi_inst)1647 get_mem_qualifier(struct tgsi_full_instruction *tgsi_inst)
1648 {
1649 enum gl_access_qualifier access = 0;
1650
1651 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_COHERENT)
1652 access |= ACCESS_COHERENT;
1653 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT)
1654 access |= ACCESS_RESTRICT;
1655 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
1656 access |= ACCESS_VOLATILE;
1657 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_STREAM_CACHE_POLICY)
1658 access |= ACCESS_STREAM_CACHE_POLICY;
1659
1660 return access;
1661 }
1662
1663 static void
ttn_mem(struct ttn_compile * c,nir_alu_dest dest,nir_ssa_def ** src)1664 ttn_mem(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1665 {
1666 nir_builder *b = &c->build;
1667 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1668 nir_intrinsic_instr *instr = NULL;
1669 unsigned resource_index, addr_src_index, file;
1670
1671 switch (tgsi_inst->Instruction.Opcode) {
1672 case TGSI_OPCODE_LOAD:
1673 assert(!tgsi_inst->Src[0].Register.Indirect);
1674 resource_index = tgsi_inst->Src[0].Register.Index;
1675 file = tgsi_inst->Src[0].Register.File;
1676 addr_src_index = 1;
1677 break;
1678 case TGSI_OPCODE_STORE:
1679 assert(!tgsi_inst->Dst[0].Register.Indirect);
1680 resource_index = tgsi_inst->Dst[0].Register.Index;
1681 file = tgsi_inst->Dst[0].Register.File;
1682 addr_src_index = 0;
1683 break;
1684 default:
1685 unreachable("unexpected memory opcode");
1686 }
1687
1688 if (file == TGSI_FILE_BUFFER) {
1689 nir_intrinsic_op op;
1690
1691 switch (tgsi_inst->Instruction.Opcode) {
1692 case TGSI_OPCODE_LOAD:
1693 op = nir_intrinsic_load_ssbo;
1694 break;
1695 case TGSI_OPCODE_STORE:
1696 op = nir_intrinsic_store_ssbo;
1697 break;
1698 default:
1699 unreachable("unexpected buffer opcode");
1700 }
1701
1702 add_ssbo_var(c, resource_index);
1703
1704 instr = nir_intrinsic_instr_create(b->shader, op);
1705 instr->num_components = util_last_bit(tgsi_inst->Dst[0].Register.WriteMask);
1706 nir_intrinsic_set_access(instr, get_mem_qualifier(tgsi_inst));
1707 nir_intrinsic_set_align(instr, 4, 0);
1708
1709 unsigned i = 0;
1710 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE)
1711 instr->src[i++] = nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W),
1712 instr->num_components));
1713 instr->src[i++] = nir_src_for_ssa(nir_imm_int(b, resource_index));
1714 instr->src[i++] = nir_src_for_ssa(ttn_channel(b, src[addr_src_index], X));
1715
1716 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE)
1717 nir_intrinsic_set_write_mask(instr, tgsi_inst->Dst[0].Register.WriteMask);
1718
1719 } else if (file == TGSI_FILE_IMAGE) {
1720 nir_intrinsic_op op;
1721
1722 switch (tgsi_inst->Instruction.Opcode) {
1723 case TGSI_OPCODE_LOAD:
1724 op = nir_intrinsic_image_deref_load;
1725 break;
1726 case TGSI_OPCODE_STORE:
1727 op = nir_intrinsic_image_deref_store;
1728 break;
1729 default:
1730 unreachable("unexpected file opcode");
1731 }
1732
1733 instr = nir_intrinsic_instr_create(b->shader, op);
1734
1735 /* Set the image variable dereference. */
1736 enum glsl_sampler_dim dim;
1737 bool is_array;
1738 get_texture_info(tgsi_inst->Memory.Texture, &dim, NULL, &is_array);
1739
1740 enum glsl_base_type base_type = get_image_base_type(tgsi_inst);
1741 enum gl_access_qualifier access = get_mem_qualifier(tgsi_inst);
1742
1743 nir_variable *image =
1744 get_image_var(c, resource_index,
1745 dim, is_array, base_type, access,
1746 tgsi_inst->Memory.Format);
1747 nir_deref_instr *image_deref = nir_build_deref_var(b, image);
1748 const struct glsl_type *type = image_deref->type;
1749
1750 nir_intrinsic_set_access(instr, image_deref->var->data.access);
1751
1752 instr->src[0] = nir_src_for_ssa(&image_deref->dest.ssa);
1753 instr->src[1] = nir_src_for_ssa(src[addr_src_index]);
1754
1755 /* Set the sample argument, which is undefined for single-sample images. */
1756 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_MS) {
1757 instr->src[2] = nir_src_for_ssa(ttn_channel(b, src[addr_src_index], W));
1758 } else {
1759 instr->src[2] = nir_src_for_ssa(nir_ssa_undef(b, 1, 32));
1760 }
1761
1762 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_LOAD) {
1763 instr->src[3] = nir_src_for_ssa(nir_imm_int(b, 0)); /* LOD */
1764 }
1765
1766 unsigned num_components = util_last_bit(tgsi_inst->Dst[0].Register.WriteMask);
1767
1768 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE) {
1769 instr->src[3] = nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W),
1770 num_components));
1771 instr->src[4] = nir_src_for_ssa(nir_imm_int(b, 0)); /* LOD */
1772 }
1773
1774 instr->num_components = num_components;
1775 } else {
1776 unreachable("unexpected file");
1777 }
1778
1779
1780 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_LOAD) {
1781 nir_ssa_dest_init(&instr->instr, &instr->dest, instr->num_components,
1782 32, NULL);
1783 nir_builder_instr_insert(b, &instr->instr);
1784 ttn_move_dest(b, dest, &instr->dest.ssa);
1785 } else {
1786 nir_builder_instr_insert(b, &instr->instr);
1787 }
1788 }
1789
1790 static const nir_op op_trans[TGSI_OPCODE_LAST] = {
1791 [TGSI_OPCODE_ARL] = 0,
1792 [TGSI_OPCODE_MOV] = nir_op_mov,
1793 [TGSI_OPCODE_FBFETCH] = nir_op_mov,
1794 [TGSI_OPCODE_LIT] = 0,
1795 [TGSI_OPCODE_RCP] = nir_op_frcp,
1796 [TGSI_OPCODE_RSQ] = nir_op_frsq,
1797 [TGSI_OPCODE_EXP] = 0,
1798 [TGSI_OPCODE_LOG] = 0,
1799 [TGSI_OPCODE_MUL] = nir_op_fmul,
1800 [TGSI_OPCODE_ADD] = nir_op_fadd,
1801 [TGSI_OPCODE_DP3] = 0,
1802 [TGSI_OPCODE_DP4] = 0,
1803 [TGSI_OPCODE_DST] = 0,
1804 [TGSI_OPCODE_MIN] = nir_op_fmin,
1805 [TGSI_OPCODE_MAX] = nir_op_fmax,
1806 [TGSI_OPCODE_SLT] = nir_op_slt,
1807 [TGSI_OPCODE_SGE] = nir_op_sge,
1808 [TGSI_OPCODE_MAD] = nir_op_ffma,
1809 [TGSI_OPCODE_TEX_LZ] = 0,
1810 [TGSI_OPCODE_LRP] = 0,
1811 [TGSI_OPCODE_SQRT] = nir_op_fsqrt,
1812 [TGSI_OPCODE_FRC] = nir_op_ffract,
1813 [TGSI_OPCODE_TXF_LZ] = 0,
1814 [TGSI_OPCODE_FLR] = nir_op_ffloor,
1815 [TGSI_OPCODE_ROUND] = nir_op_fround_even,
1816 [TGSI_OPCODE_EX2] = nir_op_fexp2,
1817 [TGSI_OPCODE_LG2] = nir_op_flog2,
1818 [TGSI_OPCODE_POW] = nir_op_fpow,
1819 [TGSI_OPCODE_COS] = nir_op_fcos,
1820 [TGSI_OPCODE_DDX] = nir_op_fddx,
1821 [TGSI_OPCODE_DDY] = nir_op_fddy,
1822 [TGSI_OPCODE_KILL] = 0,
1823 [TGSI_OPCODE_PK2H] = 0, /* XXX */
1824 [TGSI_OPCODE_PK2US] = 0, /* XXX */
1825 [TGSI_OPCODE_PK4B] = 0, /* XXX */
1826 [TGSI_OPCODE_PK4UB] = 0, /* XXX */
1827 [TGSI_OPCODE_SEQ] = nir_op_seq,
1828 [TGSI_OPCODE_SGT] = 0,
1829 [TGSI_OPCODE_SIN] = nir_op_fsin,
1830 [TGSI_OPCODE_SNE] = nir_op_sne,
1831 [TGSI_OPCODE_SLE] = 0,
1832 [TGSI_OPCODE_TEX] = 0,
1833 [TGSI_OPCODE_TXD] = 0,
1834 [TGSI_OPCODE_TXP] = 0,
1835 [TGSI_OPCODE_UP2H] = 0, /* XXX */
1836 [TGSI_OPCODE_UP2US] = 0, /* XXX */
1837 [TGSI_OPCODE_UP4B] = 0, /* XXX */
1838 [TGSI_OPCODE_UP4UB] = 0, /* XXX */
1839 [TGSI_OPCODE_ARR] = 0,
1840
1841 /* No function calls, yet. */
1842 [TGSI_OPCODE_CAL] = 0, /* XXX */
1843 [TGSI_OPCODE_RET] = 0, /* XXX */
1844
1845 [TGSI_OPCODE_SSG] = nir_op_fsign,
1846 [TGSI_OPCODE_CMP] = 0,
1847 [TGSI_OPCODE_TXB] = 0,
1848 [TGSI_OPCODE_DIV] = nir_op_fdiv,
1849 [TGSI_OPCODE_DP2] = 0,
1850 [TGSI_OPCODE_TXL] = 0,
1851
1852 [TGSI_OPCODE_BRK] = 0,
1853 [TGSI_OPCODE_IF] = 0,
1854 [TGSI_OPCODE_UIF] = 0,
1855 [TGSI_OPCODE_ELSE] = 0,
1856 [TGSI_OPCODE_ENDIF] = 0,
1857
1858 [TGSI_OPCODE_DDX_FINE] = nir_op_fddx_fine,
1859 [TGSI_OPCODE_DDY_FINE] = nir_op_fddy_fine,
1860
1861 [TGSI_OPCODE_CEIL] = nir_op_fceil,
1862 [TGSI_OPCODE_I2F] = nir_op_i2f32,
1863 [TGSI_OPCODE_NOT] = nir_op_inot,
1864 [TGSI_OPCODE_TRUNC] = nir_op_ftrunc,
1865 [TGSI_OPCODE_SHL] = nir_op_ishl,
1866 [TGSI_OPCODE_AND] = nir_op_iand,
1867 [TGSI_OPCODE_OR] = nir_op_ior,
1868 [TGSI_OPCODE_MOD] = nir_op_umod,
1869 [TGSI_OPCODE_XOR] = nir_op_ixor,
1870 [TGSI_OPCODE_TXF] = 0,
1871 [TGSI_OPCODE_TXQ] = 0,
1872
1873 [TGSI_OPCODE_CONT] = 0,
1874
1875 [TGSI_OPCODE_EMIT] = 0, /* XXX */
1876 [TGSI_OPCODE_ENDPRIM] = 0, /* XXX */
1877
1878 [TGSI_OPCODE_BGNLOOP] = 0,
1879 [TGSI_OPCODE_BGNSUB] = 0, /* XXX: no function calls */
1880 [TGSI_OPCODE_ENDLOOP] = 0,
1881 [TGSI_OPCODE_ENDSUB] = 0, /* XXX: no function calls */
1882
1883 [TGSI_OPCODE_NOP] = 0,
1884 [TGSI_OPCODE_FSEQ] = nir_op_feq,
1885 [TGSI_OPCODE_FSGE] = nir_op_fge,
1886 [TGSI_OPCODE_FSLT] = nir_op_flt,
1887 [TGSI_OPCODE_FSNE] = nir_op_fneu,
1888
1889 [TGSI_OPCODE_KILL_IF] = 0,
1890
1891 [TGSI_OPCODE_END] = 0,
1892
1893 [TGSI_OPCODE_F2I] = nir_op_f2i32,
1894 [TGSI_OPCODE_IDIV] = nir_op_idiv,
1895 [TGSI_OPCODE_IMAX] = nir_op_imax,
1896 [TGSI_OPCODE_IMIN] = nir_op_imin,
1897 [TGSI_OPCODE_INEG] = nir_op_ineg,
1898 [TGSI_OPCODE_ISGE] = nir_op_ige,
1899 [TGSI_OPCODE_ISHR] = nir_op_ishr,
1900 [TGSI_OPCODE_ISLT] = nir_op_ilt,
1901 [TGSI_OPCODE_F2U] = nir_op_f2u32,
1902 [TGSI_OPCODE_U2F] = nir_op_u2f32,
1903 [TGSI_OPCODE_UADD] = nir_op_iadd,
1904 [TGSI_OPCODE_UDIV] = nir_op_udiv,
1905 [TGSI_OPCODE_UMAD] = 0,
1906 [TGSI_OPCODE_UMAX] = nir_op_umax,
1907 [TGSI_OPCODE_UMIN] = nir_op_umin,
1908 [TGSI_OPCODE_UMOD] = nir_op_umod,
1909 [TGSI_OPCODE_UMUL] = nir_op_imul,
1910 [TGSI_OPCODE_USEQ] = nir_op_ieq,
1911 [TGSI_OPCODE_USGE] = nir_op_uge,
1912 [TGSI_OPCODE_USHR] = nir_op_ushr,
1913 [TGSI_OPCODE_USLT] = nir_op_ult,
1914 [TGSI_OPCODE_USNE] = nir_op_ine,
1915
1916 [TGSI_OPCODE_SWITCH] = 0, /* not emitted by glsl_to_tgsi.cpp */
1917 [TGSI_OPCODE_CASE] = 0, /* not emitted by glsl_to_tgsi.cpp */
1918 [TGSI_OPCODE_DEFAULT] = 0, /* not emitted by glsl_to_tgsi.cpp */
1919 [TGSI_OPCODE_ENDSWITCH] = 0, /* not emitted by glsl_to_tgsi.cpp */
1920
1921 /* XXX: SAMPLE opcodes */
1922
1923 [TGSI_OPCODE_UARL] = nir_op_mov,
1924 [TGSI_OPCODE_UCMP] = 0,
1925 [TGSI_OPCODE_IABS] = nir_op_iabs,
1926 [TGSI_OPCODE_ISSG] = nir_op_isign,
1927
1928 [TGSI_OPCODE_LOAD] = 0,
1929 [TGSI_OPCODE_STORE] = 0,
1930
1931 /* XXX: atomics */
1932
1933 [TGSI_OPCODE_TEX2] = 0,
1934 [TGSI_OPCODE_TXB2] = 0,
1935 [TGSI_OPCODE_TXL2] = 0,
1936
1937 [TGSI_OPCODE_IMUL_HI] = nir_op_imul_high,
1938 [TGSI_OPCODE_UMUL_HI] = nir_op_umul_high,
1939
1940 [TGSI_OPCODE_TG4] = 0,
1941 [TGSI_OPCODE_LODQ] = 0,
1942
1943 [TGSI_OPCODE_IBFE] = nir_op_ibitfield_extract,
1944 [TGSI_OPCODE_UBFE] = nir_op_ubitfield_extract,
1945 [TGSI_OPCODE_BFI] = nir_op_bitfield_insert,
1946 [TGSI_OPCODE_BREV] = nir_op_bitfield_reverse,
1947 [TGSI_OPCODE_POPC] = nir_op_bit_count,
1948 [TGSI_OPCODE_LSB] = nir_op_find_lsb,
1949 [TGSI_OPCODE_IMSB] = nir_op_ifind_msb,
1950 [TGSI_OPCODE_UMSB] = nir_op_ufind_msb,
1951
1952 [TGSI_OPCODE_INTERP_CENTROID] = 0, /* XXX */
1953 [TGSI_OPCODE_INTERP_SAMPLE] = 0, /* XXX */
1954 [TGSI_OPCODE_INTERP_OFFSET] = 0, /* XXX */
1955
1956 [TGSI_OPCODE_F2D] = nir_op_f2f64,
1957 [TGSI_OPCODE_D2F] = nir_op_f2f32,
1958 [TGSI_OPCODE_DMUL] = nir_op_fmul,
1959 [TGSI_OPCODE_D2U] = nir_op_f2u32,
1960 [TGSI_OPCODE_U2D] = nir_op_u2f64,
1961
1962 [TGSI_OPCODE_U64ADD] = nir_op_iadd,
1963 [TGSI_OPCODE_U64MUL] = nir_op_imul,
1964 [TGSI_OPCODE_U64DIV] = nir_op_udiv,
1965 [TGSI_OPCODE_U64SNE] = nir_op_ine,
1966 [TGSI_OPCODE_I64NEG] = nir_op_ineg,
1967 [TGSI_OPCODE_I64ABS] = nir_op_iabs,
1968 };
1969
1970 static void
ttn_emit_instruction(struct ttn_compile * c)1971 ttn_emit_instruction(struct ttn_compile *c)
1972 {
1973 nir_builder *b = &c->build;
1974 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1975 unsigned i;
1976 unsigned tgsi_op = tgsi_inst->Instruction.Opcode;
1977 struct tgsi_full_dst_register *tgsi_dst = &tgsi_inst->Dst[0];
1978
1979 if (tgsi_op == TGSI_OPCODE_END)
1980 return;
1981
1982 nir_ssa_def *src[TGSI_FULL_MAX_SRC_REGISTERS];
1983 for (i = 0; i < tgsi_inst->Instruction.NumSrcRegs; i++) {
1984 src[i] = ttn_get_src(c, &tgsi_inst->Src[i], i);
1985 }
1986 nir_alu_dest dest = ttn_get_dest(c, tgsi_dst);
1987
1988 unsigned tgsi_dst_type = tgsi_opcode_infer_dst_type(tgsi_op, 0);
1989
1990 /* The destination bitsize of the NIR opcode (not TGSI, where it's always
1991 * 32 bits). This needs to be passed into ttn_alu() because it can't be
1992 * inferred for comparison opcodes.
1993 */
1994 unsigned dst_bitsize = tgsi_type_is_64bit(tgsi_dst_type) ? 64 : 32;
1995
1996 switch (tgsi_op) {
1997 case TGSI_OPCODE_RSQ:
1998 ttn_move_dest(b, dest, nir_frsq(b, ttn_channel(b, src[0], X)));
1999 break;
2000
2001 case TGSI_OPCODE_SQRT:
2002 ttn_move_dest(b, dest, nir_fsqrt(b, ttn_channel(b, src[0], X)));
2003 break;
2004
2005 case TGSI_OPCODE_RCP:
2006 ttn_move_dest(b, dest, nir_frcp(b, ttn_channel(b, src[0], X)));
2007 break;
2008
2009 case TGSI_OPCODE_EX2:
2010 ttn_move_dest(b, dest, nir_fexp2(b, ttn_channel(b, src[0], X)));
2011 break;
2012
2013 case TGSI_OPCODE_LG2:
2014 ttn_move_dest(b, dest, nir_flog2(b, ttn_channel(b, src[0], X)));
2015 break;
2016
2017 case TGSI_OPCODE_POW:
2018 ttn_move_dest(b, dest, nir_fpow(b,
2019 ttn_channel(b, src[0], X),
2020 ttn_channel(b, src[1], X)));
2021 break;
2022
2023 case TGSI_OPCODE_COS:
2024 ttn_move_dest(b, dest, nir_fcos(b, ttn_channel(b, src[0], X)));
2025 break;
2026
2027 case TGSI_OPCODE_SIN:
2028 ttn_move_dest(b, dest, nir_fsin(b, ttn_channel(b, src[0], X)));
2029 break;
2030
2031 case TGSI_OPCODE_ARL:
2032 ttn_arl(b, op_trans[tgsi_op], dest, src);
2033 break;
2034
2035 case TGSI_OPCODE_EXP:
2036 ttn_exp(b, op_trans[tgsi_op], dest, src);
2037 break;
2038
2039 case TGSI_OPCODE_LOG:
2040 ttn_log(b, op_trans[tgsi_op], dest, src);
2041 break;
2042
2043 case TGSI_OPCODE_DST:
2044 ttn_dst(b, op_trans[tgsi_op], dest, src);
2045 break;
2046
2047 case TGSI_OPCODE_LIT:
2048 ttn_lit(b, op_trans[tgsi_op], dest, src);
2049 break;
2050
2051 case TGSI_OPCODE_DP2:
2052 ttn_dp2(b, op_trans[tgsi_op], dest, src);
2053 break;
2054
2055 case TGSI_OPCODE_DP3:
2056 ttn_dp3(b, op_trans[tgsi_op], dest, src);
2057 break;
2058
2059 case TGSI_OPCODE_DP4:
2060 ttn_dp4(b, op_trans[tgsi_op], dest, src);
2061 break;
2062
2063 case TGSI_OPCODE_UMAD:
2064 ttn_umad(b, op_trans[tgsi_op], dest, src);
2065 break;
2066
2067 case TGSI_OPCODE_LRP:
2068 ttn_move_dest(b, dest, nir_flrp(b, src[2], src[1], src[0]));
2069 break;
2070
2071 case TGSI_OPCODE_KILL:
2072 ttn_kill(b, op_trans[tgsi_op], dest, src);
2073 break;
2074
2075 case TGSI_OPCODE_ARR:
2076 ttn_arr(b, op_trans[tgsi_op], dest, src);
2077 break;
2078
2079 case TGSI_OPCODE_CMP:
2080 ttn_cmp(b, op_trans[tgsi_op], dest, src);
2081 break;
2082
2083 case TGSI_OPCODE_UCMP:
2084 ttn_ucmp(b, op_trans[tgsi_op], dest, src);
2085 break;
2086
2087 case TGSI_OPCODE_SGT:
2088 ttn_sgt(b, op_trans[tgsi_op], dest, src);
2089 break;
2090
2091 case TGSI_OPCODE_SLE:
2092 ttn_sle(b, op_trans[tgsi_op], dest, src);
2093 break;
2094
2095 case TGSI_OPCODE_KILL_IF:
2096 ttn_kill_if(b, op_trans[tgsi_op], dest, src);
2097 break;
2098
2099 case TGSI_OPCODE_TEX:
2100 case TGSI_OPCODE_TEX_LZ:
2101 case TGSI_OPCODE_TXP:
2102 case TGSI_OPCODE_TXL:
2103 case TGSI_OPCODE_TXB:
2104 case TGSI_OPCODE_TXD:
2105 case TGSI_OPCODE_TEX2:
2106 case TGSI_OPCODE_TXL2:
2107 case TGSI_OPCODE_TXB2:
2108 case TGSI_OPCODE_TXF:
2109 case TGSI_OPCODE_TXF_LZ:
2110 case TGSI_OPCODE_TG4:
2111 case TGSI_OPCODE_LODQ:
2112 ttn_tex(c, dest, src);
2113 break;
2114
2115 case TGSI_OPCODE_TXQ:
2116 ttn_txq(c, dest, src);
2117 break;
2118
2119 case TGSI_OPCODE_LOAD:
2120 case TGSI_OPCODE_STORE:
2121 ttn_mem(c, dest, src);
2122 break;
2123
2124 case TGSI_OPCODE_NOP:
2125 break;
2126
2127 case TGSI_OPCODE_IF:
2128 nir_push_if(b, nir_fneu(b, nir_channel(b, src[0], 0), nir_imm_float(b, 0.0)));
2129 break;
2130
2131 case TGSI_OPCODE_UIF:
2132 nir_push_if(b, nir_ine(b, nir_channel(b, src[0], 0), nir_imm_int(b, 0)));
2133 break;
2134
2135 case TGSI_OPCODE_ELSE:
2136 nir_push_else(&c->build, NULL);
2137 break;
2138
2139 case TGSI_OPCODE_ENDIF:
2140 nir_pop_if(&c->build, NULL);
2141 break;
2142
2143 case TGSI_OPCODE_BGNLOOP:
2144 nir_push_loop(&c->build);
2145 break;
2146
2147 case TGSI_OPCODE_BRK:
2148 nir_jump(b, nir_jump_break);
2149 break;
2150
2151 case TGSI_OPCODE_CONT:
2152 nir_jump(b, nir_jump_continue);
2153 break;
2154
2155 case TGSI_OPCODE_ENDLOOP:
2156 nir_pop_loop(&c->build, NULL);
2157 break;
2158
2159 case TGSI_OPCODE_BARRIER:
2160 ttn_barrier(b);
2161 break;
2162
2163 default:
2164 if (op_trans[tgsi_op] != 0 || tgsi_op == TGSI_OPCODE_MOV) {
2165 ttn_alu(b, op_trans[tgsi_op], dest, dst_bitsize, src);
2166 } else {
2167 fprintf(stderr, "unknown TGSI opcode: %s\n",
2168 tgsi_get_opcode_name(tgsi_op));
2169 abort();
2170 }
2171 break;
2172 }
2173
2174 if (tgsi_inst->Instruction.Saturate) {
2175 assert(!dest.dest.is_ssa);
2176 ttn_move_dest(b, dest, nir_fsat(b, ttn_src_for_dest(b, &dest)));
2177 }
2178
2179 /* if the dst has a matching var, append store_var to move
2180 * output from reg to var
2181 */
2182 nir_variable *var = ttn_get_var(c, tgsi_dst);
2183 if (var) {
2184 unsigned index = tgsi_dst->Register.Index;
2185 unsigned offset = c->temp_regs[index].offset;
2186 struct tgsi_ind_register *indirect = tgsi_dst->Register.Indirect ?
2187 &tgsi_dst->Indirect : NULL;
2188 nir_src val = nir_src_for_reg(dest.dest.reg.reg);
2189 nir_store_deref(b, ttn_array_deref(c, var, offset, indirect),
2190 nir_ssa_for_src(b, val, 4), dest.write_mask);
2191 }
2192 }
2193
2194 /**
2195 * Puts a NIR intrinsic to store of each TGSI_FILE_OUTPUT value to the output
2196 * variables at the end of the shader.
2197 *
2198 * We don't generate these incrementally as the TGSI_FILE_OUTPUT values are
2199 * written, because there's no output load intrinsic, which means we couldn't
2200 * handle writemasks.
2201 */
2202 static void
ttn_add_output_stores(struct ttn_compile * c)2203 ttn_add_output_stores(struct ttn_compile *c)
2204 {
2205 nir_builder *b = &c->build;
2206
2207 for (int i = 0; i < c->build.shader->num_outputs; i++) {
2208 nir_variable *var = c->outputs[i];
2209 if (!var)
2210 continue;
2211
2212 nir_src src = nir_src_for_reg(c->output_regs[i].reg);
2213 src.reg.base_offset = c->output_regs[i].offset;
2214
2215 nir_ssa_def *store_value = nir_ssa_for_src(b, src, 4);
2216 if (c->build.shader->info.stage == MESA_SHADER_FRAGMENT) {
2217 /* TGSI uses TGSI_SEMANTIC_POSITION.z for the depth output
2218 * and TGSI_SEMANTIC_STENCIL.y for the stencil output,
2219 * while NIR uses a single-component output.
2220 */
2221 if (var->data.location == FRAG_RESULT_DEPTH)
2222 store_value = nir_channel(b, store_value, 2);
2223 else if (var->data.location == FRAG_RESULT_STENCIL)
2224 store_value = nir_channel(b, store_value, 1);
2225 else if (var->data.location == FRAG_RESULT_SAMPLE_MASK)
2226 store_value = nir_channel(b, store_value, 0);
2227 } else {
2228 /* FOGC, LAYER, and PSIZ are scalar values */
2229 if (var->data.location == VARYING_SLOT_FOGC ||
2230 var->data.location == VARYING_SLOT_LAYER ||
2231 var->data.location == VARYING_SLOT_PSIZ) {
2232 store_value = nir_channel(b, store_value, 0);
2233 }
2234 }
2235
2236 nir_store_deref(b, nir_build_deref_var(b, var), store_value,
2237 (1 << store_value->num_components) - 1);
2238 }
2239 }
2240
2241 /**
2242 * Parses the given TGSI tokens.
2243 */
2244 static void
ttn_parse_tgsi(struct ttn_compile * c,const void * tgsi_tokens)2245 ttn_parse_tgsi(struct ttn_compile *c, const void *tgsi_tokens)
2246 {
2247 struct tgsi_parse_context parser;
2248 ASSERTED int ret;
2249
2250 ret = tgsi_parse_init(&parser, tgsi_tokens);
2251 assert(ret == TGSI_PARSE_OK);
2252
2253 while (!tgsi_parse_end_of_tokens(&parser)) {
2254 tgsi_parse_token(&parser);
2255 c->token = &parser.FullToken;
2256
2257 switch (parser.FullToken.Token.Type) {
2258 case TGSI_TOKEN_TYPE_DECLARATION:
2259 ttn_emit_declaration(c);
2260 break;
2261
2262 case TGSI_TOKEN_TYPE_INSTRUCTION:
2263 ttn_emit_instruction(c);
2264 break;
2265
2266 case TGSI_TOKEN_TYPE_IMMEDIATE:
2267 ttn_emit_immediate(c);
2268 break;
2269 }
2270 }
2271
2272 tgsi_parse_free(&parser);
2273 }
2274
2275 static void
ttn_read_pipe_caps(struct ttn_compile * c,struct pipe_screen * screen)2276 ttn_read_pipe_caps(struct ttn_compile *c,
2277 struct pipe_screen *screen)
2278 {
2279 c->cap_samplers_as_deref = screen->get_param(screen, PIPE_CAP_NIR_SAMPLERS_AS_DEREF);
2280 c->cap_face_is_sysval = screen->get_param(screen, PIPE_CAP_FS_FACE_IS_INTEGER_SYSVAL);
2281 c->cap_position_is_sysval = screen->get_param(screen, PIPE_CAP_FS_POSITION_IS_SYSVAL);
2282 c->cap_point_is_sysval = screen->get_param(screen, PIPE_CAP_FS_POINT_IS_SYSVAL);
2283 c->cap_integers = screen->get_shader_param(screen, c->scan->processor, PIPE_SHADER_CAP_INTEGERS);
2284 }
2285
2286 #define BITSET_SET32(bitset, u32_mask) do { \
2287 STATIC_ASSERT(sizeof((bitset)[0]) >= sizeof(u32_mask)); \
2288 BITSET_ZERO(bitset); \
2289 (bitset)[0] = (u32_mask); \
2290 } while (0)
2291
2292 /**
2293 * Initializes a TGSI-to-NIR compiler.
2294 */
2295 static struct ttn_compile *
ttn_compile_init(const void * tgsi_tokens,const nir_shader_compiler_options * options,struct pipe_screen * screen)2296 ttn_compile_init(const void *tgsi_tokens,
2297 const nir_shader_compiler_options *options,
2298 struct pipe_screen *screen)
2299 {
2300 struct ttn_compile *c;
2301 struct nir_shader *s;
2302 struct tgsi_shader_info scan;
2303
2304 assert(options || screen);
2305 c = rzalloc(NULL, struct ttn_compile);
2306
2307 tgsi_scan_shader(tgsi_tokens, &scan);
2308 c->scan = &scan;
2309
2310 if (!options) {
2311 options =
2312 screen->get_compiler_options(screen, PIPE_SHADER_IR_NIR, scan.processor);
2313 }
2314
2315 c->build = nir_builder_init_simple_shader(tgsi_processor_to_shader_stage(scan.processor),
2316 options, "TTN");
2317
2318 s = c->build.shader;
2319
2320 if (screen) {
2321 ttn_read_pipe_caps(c, screen);
2322 } else {
2323 /* TTN used to be hard coded to always make FACE a sysval,
2324 * so it makes sense to preserve that behavior so users don't break. */
2325 c->cap_face_is_sysval = true;
2326 }
2327
2328 s->info.subgroup_size = SUBGROUP_SIZE_UNIFORM;
2329
2330 if (s->info.stage == MESA_SHADER_FRAGMENT)
2331 s->info.fs.untyped_color_outputs = true;
2332
2333 s->num_inputs = scan.file_max[TGSI_FILE_INPUT] + 1;
2334 s->num_uniforms = scan.const_file_max[0] + 1;
2335 s->num_outputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
2336 s->info.num_ssbos = util_last_bit(scan.shader_buffers_declared);
2337 s->info.num_ubos = util_last_bit(scan.const_buffers_declared >> 1);
2338 s->info.num_images = util_last_bit(scan.images_declared);
2339 BITSET_SET32(s->info.images_used, scan.images_declared);
2340 BITSET_SET32(s->info.image_buffers, scan.images_buffers);
2341 BITSET_SET32(s->info.msaa_images, scan.msaa_images_declared);
2342 s->info.num_textures = util_last_bit(scan.samplers_declared);
2343 BITSET_SET32(s->info.textures_used, scan.samplers_declared);
2344 BITSET_ZERO(s->info.textures_used_by_txf); /* No scan information yet */
2345 BITSET_SET32(s->info.samplers_used, scan.samplers_declared);
2346 s->info.internal = false;
2347
2348 /* Default for TGSI is separate, this is assumed throughout the tree */
2349 s->info.separate_shader = true;
2350
2351 for (unsigned i = 0; i < TGSI_PROPERTY_COUNT; i++) {
2352 unsigned value = scan.properties[i];
2353
2354 switch (i) {
2355 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
2356 break; /* handled in ttn_emit_declaration */
2357 case TGSI_PROPERTY_FS_COORD_ORIGIN:
2358 if (s->info.stage == MESA_SHADER_FRAGMENT)
2359 s->info.fs.origin_upper_left = value == TGSI_FS_COORD_ORIGIN_UPPER_LEFT;
2360 break;
2361 case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
2362 if (s->info.stage == MESA_SHADER_FRAGMENT)
2363 s->info.fs.pixel_center_integer = value == TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
2364 break;
2365 case TGSI_PROPERTY_FS_DEPTH_LAYOUT:
2366 if (s->info.stage == MESA_SHADER_FRAGMENT)
2367 s->info.fs.depth_layout = ttn_get_depth_layout(value);
2368 break;
2369 case TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION:
2370 if (s->info.stage == MESA_SHADER_VERTEX)
2371 s->info.vs.window_space_position = value;
2372 break;
2373 case TGSI_PROPERTY_NEXT_SHADER:
2374 s->info.next_stage = tgsi_processor_to_shader_stage(value);
2375 break;
2376 case TGSI_PROPERTY_VS_BLIT_SGPRS_AMD:
2377 if (s->info.stage == MESA_SHADER_VERTEX)
2378 s->info.vs.blit_sgprs_amd = value;
2379 break;
2380 case TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH:
2381 if (s->info.stage == MESA_SHADER_COMPUTE)
2382 s->info.workgroup_size[0] = value;
2383 break;
2384 case TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT:
2385 if (s->info.stage == MESA_SHADER_COMPUTE)
2386 s->info.workgroup_size[1] = value;
2387 break;
2388 case TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH:
2389 if (s->info.stage == MESA_SHADER_COMPUTE)
2390 s->info.workgroup_size[2] = value;
2391 break;
2392 case TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD:
2393 if (s->info.stage == MESA_SHADER_COMPUTE)
2394 s->info.cs.user_data_components_amd = value;
2395 break;
2396 case TGSI_PROPERTY_NUM_CLIPDIST_ENABLED:
2397 s->info.clip_distance_array_size = value;
2398 break;
2399 case TGSI_PROPERTY_LEGACY_MATH_RULES:
2400 s->info.use_legacy_math_rules = value;
2401 break;
2402 default:
2403 if (value) {
2404 fprintf(stderr, "tgsi_to_nir: unhandled TGSI property %u = %u\n",
2405 i, value);
2406 unreachable("unhandled TGSI property");
2407 }
2408 }
2409 }
2410
2411 if (s->info.stage == MESA_SHADER_COMPUTE &&
2412 (!s->info.workgroup_size[0] ||
2413 !s->info.workgroup_size[1] ||
2414 !s->info.workgroup_size[2]))
2415 s->info.workgroup_size_variable = true;
2416
2417 c->inputs = rzalloc_array(c, struct nir_variable *, s->num_inputs);
2418 c->outputs = rzalloc_array(c, struct nir_variable *, s->num_outputs);
2419
2420 c->output_regs = rzalloc_array(c, struct ttn_reg_info,
2421 scan.file_max[TGSI_FILE_OUTPUT] + 1);
2422 c->temp_regs = rzalloc_array(c, struct ttn_reg_info,
2423 scan.file_max[TGSI_FILE_TEMPORARY] + 1);
2424 c->imm_defs = rzalloc_array(c, nir_ssa_def *,
2425 scan.file_max[TGSI_FILE_IMMEDIATE] + 1);
2426
2427 c->num_samp_types = scan.file_max[TGSI_FILE_SAMPLER_VIEW] + 1;
2428 c->samp_types = rzalloc_array(c, nir_alu_type, c->num_samp_types);
2429
2430 ttn_parse_tgsi(c, tgsi_tokens);
2431 ttn_add_output_stores(c);
2432
2433 nir_validate_shader(c->build.shader, "TTN: after parsing TGSI and creating the NIR shader");
2434
2435 return c;
2436 }
2437
2438 static void
ttn_optimize_nir(nir_shader * nir)2439 ttn_optimize_nir(nir_shader *nir)
2440 {
2441 bool progress;
2442
2443 do {
2444 progress = false;
2445
2446 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2447
2448 /* Linking deals with unused inputs/outputs, but here we can remove
2449 * things local to the shader in the hopes that we can cleanup other
2450 * things. This pass will also remove variables with only stores, so we
2451 * might be able to make progress after it.
2452 */
2453 NIR_PASS(progress, nir, nir_remove_dead_variables,
2454 nir_var_function_temp | nir_var_shader_temp |
2455 nir_var_mem_shared,
2456 NULL);
2457
2458 NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
2459 NIR_PASS(progress, nir, nir_opt_dead_write_vars);
2460
2461 if (nir->options->lower_to_scalar) {
2462 NIR_PASS_V(nir, nir_lower_alu_to_scalar,
2463 nir->options->lower_to_scalar_filter, NULL);
2464 NIR_PASS_V(nir, nir_lower_phis_to_scalar, false);
2465 }
2466
2467 NIR_PASS_V(nir, nir_lower_alu);
2468 NIR_PASS_V(nir, nir_lower_pack);
2469 NIR_PASS(progress, nir, nir_copy_prop);
2470 NIR_PASS(progress, nir, nir_opt_remove_phis);
2471 NIR_PASS(progress, nir, nir_opt_dce);
2472 if (nir_opt_trivial_continues(nir)) {
2473 progress = true;
2474 NIR_PASS(progress, nir, nir_copy_prop);
2475 NIR_PASS(progress, nir, nir_opt_dce);
2476 }
2477 NIR_PASS(progress, nir, nir_opt_if, nir_opt_if_optimize_phi_true_false);
2478 NIR_PASS(progress, nir, nir_opt_dead_cf);
2479 NIR_PASS(progress, nir, nir_opt_cse);
2480 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
2481
2482 NIR_PASS(progress, nir, nir_opt_phi_precision);
2483 NIR_PASS(progress, nir, nir_opt_algebraic);
2484 NIR_PASS(progress, nir, nir_opt_constant_folding);
2485
2486 if (!nir->info.flrp_lowered) {
2487 unsigned lower_flrp =
2488 (nir->options->lower_flrp16 ? 16 : 0) |
2489 (nir->options->lower_flrp32 ? 32 : 0) |
2490 (nir->options->lower_flrp64 ? 64 : 0);
2491
2492 if (lower_flrp) {
2493 bool lower_flrp_progress = false;
2494
2495 NIR_PASS(lower_flrp_progress, nir, nir_lower_flrp,
2496 lower_flrp,
2497 false /* always_precise */);
2498 if (lower_flrp_progress) {
2499 NIR_PASS(progress, nir,
2500 nir_opt_constant_folding);
2501 progress = true;
2502 }
2503 }
2504
2505 /* Nothing should rematerialize any flrps, so we only need to do this
2506 * lowering once.
2507 */
2508 nir->info.flrp_lowered = true;
2509 }
2510
2511 NIR_PASS(progress, nir, nir_opt_undef);
2512 NIR_PASS(progress, nir, nir_opt_conditional_discard);
2513 if (nir->options->max_unroll_iterations) {
2514 NIR_PASS(progress, nir, nir_opt_loop_unroll);
2515 }
2516 } while (progress);
2517 }
2518
2519 /**
2520 * Finalizes the NIR in a similar way as st_glsl_to_nir does.
2521 *
2522 * Drivers expect that these passes are already performed,
2523 * so we have to do it here too.
2524 */
2525 static void
ttn_finalize_nir(struct ttn_compile * c,struct pipe_screen * screen)2526 ttn_finalize_nir(struct ttn_compile *c, struct pipe_screen *screen)
2527 {
2528 struct nir_shader *nir = c->build.shader;
2529
2530 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2531 NIR_PASS_V(nir, nir_lower_regs_to_ssa);
2532
2533 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2534 NIR_PASS_V(nir, nir_split_var_copies);
2535 NIR_PASS_V(nir, nir_lower_var_copies);
2536 NIR_PASS_V(nir, nir_lower_system_values);
2537 NIR_PASS_V(nir, nir_lower_compute_system_values, NULL);
2538
2539 if (!screen->get_param(screen, PIPE_CAP_TEXRECT)) {
2540 const struct nir_lower_tex_options opts = { .lower_rect = true, };
2541 NIR_PASS_V(nir, nir_lower_tex, &opts);
2542 }
2543
2544 if (nir->options->lower_uniforms_to_ubo)
2545 NIR_PASS_V(nir, nir_lower_uniforms_to_ubo, false, !c->cap_integers);
2546
2547 if (!c->cap_samplers_as_deref)
2548 NIR_PASS_V(nir, nir_lower_samplers);
2549
2550 if (screen->finalize_nir) {
2551 char *msg = screen->finalize_nir(screen, nir);
2552 free(msg);
2553 } else {
2554 ttn_optimize_nir(nir);
2555 nir_shader_gather_info(nir, c->build.impl);
2556 }
2557
2558 nir->info.num_images = c->num_images;
2559 nir->info.num_textures = c->num_samplers;
2560
2561 nir_validate_shader(nir, "TTN: after all optimizations");
2562 }
2563
save_nir_to_disk_cache(struct disk_cache * cache,uint8_t key[CACHE_KEY_SIZE],const nir_shader * s)2564 static void save_nir_to_disk_cache(struct disk_cache *cache,
2565 uint8_t key[CACHE_KEY_SIZE],
2566 const nir_shader *s)
2567 {
2568 struct blob blob = {0};
2569
2570 blob_init(&blob);
2571 /* Because we cannot fully trust disk_cache_put
2572 * (EGL_ANDROID_blob_cache) we add the shader size,
2573 * which we'll check after disk_cache_get().
2574 */
2575 if (blob_reserve_uint32(&blob) != 0) {
2576 blob_finish(&blob);
2577 return;
2578 }
2579
2580 nir_serialize(&blob, s, true);
2581 *(uint32_t *)blob.data = blob.size;
2582
2583 disk_cache_put(cache, key, blob.data, blob.size, NULL);
2584 blob_finish(&blob);
2585 }
2586
2587 static nir_shader *
load_nir_from_disk_cache(struct disk_cache * cache,struct pipe_screen * screen,uint8_t key[CACHE_KEY_SIZE],unsigned processor)2588 load_nir_from_disk_cache(struct disk_cache *cache,
2589 struct pipe_screen *screen,
2590 uint8_t key[CACHE_KEY_SIZE],
2591 unsigned processor)
2592 {
2593 const nir_shader_compiler_options *options =
2594 screen->get_compiler_options(screen, PIPE_SHADER_IR_NIR, processor);
2595 struct blob_reader blob_reader;
2596 size_t size;
2597 nir_shader *s;
2598
2599 uint32_t *buffer = (uint32_t *)disk_cache_get(cache, key, &size);
2600 if (!buffer)
2601 return NULL;
2602
2603 /* Match found. No need to check crc32 or other things.
2604 * disk_cache_get is supposed to do that for us.
2605 * However we do still check if the first element is indeed the size,
2606 * as we cannot fully trust disk_cache_get (EGL_ANDROID_blob_cache) */
2607 if (buffer[0] != size) {
2608 return NULL;
2609 }
2610
2611 size -= 4;
2612 blob_reader_init(&blob_reader, buffer + 1, size);
2613 s = nir_deserialize(NULL, options, &blob_reader);
2614 free(buffer); /* buffer was malloc-ed */
2615 return s;
2616 }
2617
2618 struct nir_shader *
tgsi_to_nir(const void * tgsi_tokens,struct pipe_screen * screen,bool allow_disk_cache)2619 tgsi_to_nir(const void *tgsi_tokens,
2620 struct pipe_screen *screen,
2621 bool allow_disk_cache)
2622 {
2623 struct disk_cache *cache = NULL;
2624 struct ttn_compile *c;
2625 struct nir_shader *s = NULL;
2626 uint8_t key[CACHE_KEY_SIZE];
2627 unsigned processor;
2628
2629 if (allow_disk_cache)
2630 cache = screen->get_disk_shader_cache(screen);
2631
2632 /* Look first in the cache */
2633 if (cache) {
2634 disk_cache_compute_key(cache,
2635 tgsi_tokens,
2636 tgsi_num_tokens(tgsi_tokens) * sizeof(struct tgsi_token),
2637 key);
2638 processor = tgsi_get_processor_type(tgsi_tokens);
2639 s = load_nir_from_disk_cache(cache, screen, key, processor);
2640 }
2641
2642 if (s)
2643 return s;
2644
2645 #ifndef NDEBUG
2646 nir_process_debug_variable();
2647 #endif
2648
2649 if (NIR_DEBUG(TGSI)) {
2650 fprintf(stderr, "TGSI before translation to NIR:\n");
2651 tgsi_dump(tgsi_tokens, 0);
2652 }
2653
2654 /* Not in the cache */
2655
2656 c = ttn_compile_init(tgsi_tokens, NULL, screen);
2657 s = c->build.shader;
2658 ttn_finalize_nir(c, screen);
2659 ralloc_free(c);
2660
2661 if (NIR_DEBUG(TGSI)) {
2662 mesa_logi("NIR after translation from TGSI:\n");
2663 nir_log_shaderi(s);
2664 }
2665
2666 if (cache)
2667 save_nir_to_disk_cache(cache, key, s);
2668
2669 return s;
2670 }
2671
2672 struct nir_shader *
tgsi_to_nir_noscreen(const void * tgsi_tokens,const nir_shader_compiler_options * options)2673 tgsi_to_nir_noscreen(const void *tgsi_tokens,
2674 const nir_shader_compiler_options *options)
2675 {
2676 struct ttn_compile *c;
2677 struct nir_shader *s;
2678
2679 c = ttn_compile_init(tgsi_tokens, options, NULL);
2680 s = c->build.shader;
2681 ralloc_free(c);
2682
2683 return s;
2684 }
2685
2686