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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/bus/
Dallwinner,sun8i-a23-rsb.yaml18 const: 0
46 "^.*@[0-9a-fA-F]+$":
67 reg = <0x01f03400 0x400>;
68 interrupts = <0 39 4>;
73 #size-cells = <0>;
76 reg = <0x3e3>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/bus/
Dallwinner,sun8i-a23-rsb.yaml18 const: 0
44 "^.*@[0-9a-fA-F]+$":
64 reg = <0x01f03400 0x400>;
65 interrupts = <0 39 4>;
70 #size-cells = <0>;
73 reg = <0x3e3>;
/kernel/linux/linux-5.10/sound/drivers/opl4/
Dopl4_synth.c41 #define MIDI_CTL_RELEASE_TIME 0x48
42 #define MIDI_CTL_ATTACK_TIME 0x49
43 #define MIDI_CTL_DECAY_TIME 0x4b
44 #define MIDI_CTL_VIBRATO_RATE 0x4c
45 #define MIDI_CTL_VIBRATO_DEPTH 0x4d
46 #define MIDI_CTL_VIBRATO_DELAY 0x4e
52 static const s16 snd_opl4_pitch_map[0x600] = {
53 0x000,0x000,0x001,0x001,0x002,0x002,0x003,0x003,
54 0x004,0x004,0x005,0x005,0x006,0x006,0x006,0x007,
55 0x007,0x008,0x008,0x009,0x009,0x00a,0x00a,0x00b,
[all …]
/kernel/linux/linux-6.6/sound/drivers/opl4/
Dopl4_synth.c41 #define MIDI_CTL_RELEASE_TIME 0x48
42 #define MIDI_CTL_ATTACK_TIME 0x49
43 #define MIDI_CTL_DECAY_TIME 0x4b
44 #define MIDI_CTL_VIBRATO_RATE 0x4c
45 #define MIDI_CTL_VIBRATO_DEPTH 0x4d
46 #define MIDI_CTL_VIBRATO_DELAY 0x4e
52 static const s16 snd_opl4_pitch_map[0x600] = {
53 0x000,0x000,0x001,0x001,0x002,0x002,0x003,0x003,
54 0x004,0x004,0x005,0x005,0x006,0x006,0x006,0x007,
55 0x007,0x008,0x008,0x009,0x009,0x00a,0x00a,0x00b,
[all …]
/kernel/linux/linux-5.10/drivers/net/ieee802154/
Dadf7242.c33 #define REG_EXT_CTRL 0x100 /* RW External LNA/PA and internal PA control */
34 #define REG_TX_FSK_TEST 0x101 /* RW TX FSK test mode configuration */
35 #define REG_CCA1 0x105 /* RW RSSI threshold for CCA */
36 #define REG_CCA2 0x106 /* RW CCA mode configuration */
37 #define REG_BUFFERCFG 0x107 /* RW RX_BUFFER overwrite control */
38 #define REG_PKT_CFG 0x108 /* RW FCS evaluation configuration */
39 #define REG_DELAYCFG0 0x109 /* RW RC_RX command to SFD or sync word delay */
40 #define REG_DELAYCFG1 0x10A /* RW RC_TX command to TX state */
41 #define REG_DELAYCFG2 0x10B /* RW Mac delay extension */
42 #define REG_SYNC_WORD0 0x10C /* RW sync word bits [7:0] of [23:0] */
[all …]
/kernel/linux/linux-6.6/drivers/net/ieee802154/
Dadf7242.c33 #define REG_EXT_CTRL 0x100 /* RW External LNA/PA and internal PA control */
34 #define REG_TX_FSK_TEST 0x101 /* RW TX FSK test mode configuration */
35 #define REG_CCA1 0x105 /* RW RSSI threshold for CCA */
36 #define REG_CCA2 0x106 /* RW CCA mode configuration */
37 #define REG_BUFFERCFG 0x107 /* RW RX_BUFFER overwrite control */
38 #define REG_PKT_CFG 0x108 /* RW FCS evaluation configuration */
39 #define REG_DELAYCFG0 0x109 /* RW RC_RX command to SFD or sync word delay */
40 #define REG_DELAYCFG1 0x10A /* RW RC_TX command to TX state */
41 #define REG_DELAYCFG2 0x10B /* RW Mac delay extension */
42 #define REG_SYNC_WORD0 0x10C /* RW sync word bits [7:0] of [23:0] */
[all …]
/kernel/linux/linux-6.6/arch/loongarch/include/asm/
Dloongarch.h23 #define REG_ZERO 0x0
24 #define REG_RA 0x1
25 #define REG_TP 0x2
26 #define REG_SP 0x3
27 #define REG_A0 0x4 /* Reused as V0 for return value */
28 #define REG_A1 0x5 /* Reused as V1 for return value */
29 #define REG_A2 0x6
30 #define REG_A3 0x7
31 #define REG_A4 0x8
32 #define REG_A5 0x9
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_d.h27 #define mmPIPE0_PG_CONFIG 0x1760
28 #define mmPIPE0_PG_ENABLE 0x1761
29 #define mmPIPE0_PG_STATUS 0x1762
30 #define mmPIPE1_PG_CONFIG 0x1764
31 #define mmPIPE1_PG_ENABLE 0x1765
32 #define mmPIPE1_PG_STATUS 0x1766
33 #define mmPIPE2_PG_CONFIG 0x1768
34 #define mmPIPE2_PG_ENABLE 0x1769
35 #define mmPIPE2_PG_STATUS 0x176a
36 #define mmPIPE3_PG_CONFIG 0x176c
[all …]
Ddce_11_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmDCFEV0_PG_CONFIG 0x2db
[all …]
Ddce_10_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]
Ddce_11_2_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_d.h27 #define mmPIPE0_PG_CONFIG 0x1760
28 #define mmPIPE0_PG_ENABLE 0x1761
29 #define mmPIPE0_PG_STATUS 0x1762
30 #define mmPIPE1_PG_CONFIG 0x1764
31 #define mmPIPE1_PG_ENABLE 0x1765
32 #define mmPIPE1_PG_STATUS 0x1766
33 #define mmPIPE2_PG_CONFIG 0x1768
34 #define mmPIPE2_PG_ENABLE 0x1769
35 #define mmPIPE2_PG_STATUS 0x176a
36 #define mmPIPE3_PG_CONFIG 0x176c
[all …]
Ddce_11_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmDCFEV0_PG_CONFIG 0x2db
[all …]
Ddce_10_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]
Ddce_11_2_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]
/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/
D0020_linux_drivers_gpu.patch127 @@ -0,0 +1,868 @@
175 + if ((native == true) && ((msg->size == 0) || (msg->buffer == NULL))) {
190 + for (i = 0; i < msg->size; ++i) {
207 + if (ret < 0)
217 + u8 i2c_status = 0u;
218 + u16 respSize = 0u;
225 + if (ret < 0) {
232 + if (ret < 0) {
240 + case 0u:
259 + u8 i2c_status = 0u;
[all …]