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/kernel/linux/linux-6.6/arch/arm/mach-imx/
Dmach-imx6q.c29 0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW); in ksz9021rn_phy_fixup()
30 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000); in ksz9021rn_phy_fixup()
34 0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW); in ksz9021rn_phy_fixup()
35 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0); in ksz9021rn_phy_fixup()
40 return 0; in ksz9021rn_phy_fixup()
54 if (dev->devfn != 0) in ventana_pciesw_early_fixup()
57 pci_read_config_dword(dev, 0x62c, &dw); in ventana_pciesw_early_fixup()
58 dw |= 0xaaa8; // GPIO1-7 outputs in ventana_pciesw_early_fixup()
59 pci_write_config_dword(dev, 0x62c, dw); in ventana_pciesw_early_fixup()
61 pci_read_config_dword(dev, 0x644, &dw); in ventana_pciesw_early_fixup()
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-imx/
Dmach-imx6q.c29 0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW); in ksz9021rn_phy_fixup()
30 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000); in ksz9021rn_phy_fixup()
34 0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW); in ksz9021rn_phy_fixup()
35 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0); in ksz9021rn_phy_fixup()
40 return 0; in ksz9021rn_phy_fixup()
45 phy_write(dev, 0x0d, device); in mmd_write_reg()
46 phy_write(dev, 0x0e, reg); in mmd_write_reg()
47 phy_write(dev, 0x0d, (1 << 14) | device); in mmd_write_reg()
48 phy_write(dev, 0x0e, val); in mmd_write_reg()
57 mmd_write_reg(dev, 2, 4, 0); in ksz9031rn_phy_fixup()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/can/
Dbosch,c_can.yaml55 register offset to the RAMINIT register and the CAN instance number (0
103 reg = <0xffc00000 0x1000>;
104 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
109 can@0 {
111 reg = <0x0 0x2000>;
114 syscon-raminit = <&scm_conf 0x644 1>;
/kernel/linux/linux-6.6/drivers/video/fbdev/
Dplatinumfb.h54 * F = 14.3MHz * c0 / (c1 & 0x1f) / (1 << (c1 >> 5))
55 * Newer ones use the values in clocksel[0], for which the formula
57 * F = 15MHz * c0 / ((c1 & 0x1f) + 2) / (1 << (c1 >> 5))
69 #define DIV2 0x20
70 #define DIV4 0x40
71 #define DIV8 0x60
72 #define DIV16 0x80
76 0x5c00,
78 { 0xffc, 4, 0, 0, 0, 0, 0x428, 0,
79 0, 0xb3, 0xd3, 0x12, 0x1a5, 0x23, 0x28, 0x2d,
[all …]
/kernel/linux/linux-5.10/drivers/video/fbdev/
Dplatinumfb.h54 * F = 14.3MHz * c0 / (c1 & 0x1f) / (1 << (c1 >> 5))
55 * Newer ones use the values in clocksel[0], for which the formula
57 * F = 15MHz * c0 / ((c1 & 0x1f) + 2) / (1 << (c1 >> 5))
69 #define DIV2 0x20
70 #define DIV4 0x40
71 #define DIV8 0x60
72 #define DIV16 0x80
76 0x5c00,
78 { 0xffc, 4, 0, 0, 0, 0, 0x428, 0,
79 0, 0xb3, 0xd3, 0x12, 0x1a5, 0x23, 0x28, 0x2d,
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/
Ddra72x-mmc-iodelay.dtsi37 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
38 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
39 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
40 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
41 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
42 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
48 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
49 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
50 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
51 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
Ddra76x-mmc-iodelay.dtsi32 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
33 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
34 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
35 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
36 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
37 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
43 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
44 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
45 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
46 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
Ddra74x-mmc-iodelay.dtsi35 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
36 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
37 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
38 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
39 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
40 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
46 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
47 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
48 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
49 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Ddra72x-mmc-iodelay.dtsi45 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
46 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
47 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
48 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
49 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
50 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
56 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
57 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
58 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
59 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
Ddra76x-mmc-iodelay.dtsi32 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
33 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
34 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
35 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
36 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
37 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
43 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
44 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
45 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
46 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
Ddra74x-mmc-iodelay.dtsi43 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
44 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
45 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
46 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
47 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
48 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
54 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
55 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
56 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
57 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/imx/
Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Drv730d.h26 #define CG_SPLL_FUNC_CNTL 0x600
27 #define SPLL_RESET (1 << 0)
32 #define SPLL_REF_DIV_MASK (0x3f << 4)
34 #define SPLL_HILEN_MASK (0xf << 12)
36 #define SPLL_LOLEN_MASK (0xf << 16)
37 #define CG_SPLL_FUNC_CNTL_2 0x604
38 #define SCLK_MUX_SEL(x) ((x) << 0)
39 #define SCLK_MUX_SEL_MASK (0x1ff << 0)
40 #define CG_SPLL_FUNC_CNTL_3 0x608
41 #define SPLL_FB_DIV(x) ((x) << 0)
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
Drv730d.h26 #define CG_SPLL_FUNC_CNTL 0x600
27 #define SPLL_RESET (1 << 0)
32 #define SPLL_REF_DIV_MASK (0x3f << 4)
34 #define SPLL_HILEN_MASK (0xf << 12)
36 #define SPLL_LOLEN_MASK (0xf << 16)
37 #define CG_SPLL_FUNC_CNTL_2 0x604
38 #define SCLK_MUX_SEL(x) ((x) << 0)
39 #define SCLK_MUX_SEL_MASK (0x1ff << 0)
40 #define CG_SPLL_FUNC_CNTL_3 0x608
41 #define SPLL_FB_DIV(x) ((x) << 0)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dgp100.c40 nvkm_wr32(device, 0x418010 + zoff, gr->zbc_color[zbc].ds[0]); in gp100_gr_zbc_clear_color()
41 nvkm_wr32(device, 0x41804c + zoff, gr->zbc_color[zbc].ds[1]); in gp100_gr_zbc_clear_color()
42 nvkm_wr32(device, 0x418088 + zoff, gr->zbc_color[zbc].ds[2]); in gp100_gr_zbc_clear_color()
43 nvkm_wr32(device, 0x4180c4 + zoff, gr->zbc_color[zbc].ds[3]); in gp100_gr_zbc_clear_color()
46 nvkm_mask(device, 0x418100 + ((znum / 4) * 4), in gp100_gr_zbc_clear_color()
47 0x0000007f << ((znum % 4) * 7), in gp100_gr_zbc_clear_color()
59 nvkm_wr32(device, 0x418110 + zoff, gr->zbc_depth[zbc].ds); in gp100_gr_zbc_clear_depth()
60 nvkm_mask(device, 0x41814c + ((znum / 4) * 4), in gp100_gr_zbc_clear_depth()
61 0x0000007f << ((znum % 4) * 7), in gp100_gr_zbc_clear_depth()
75 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); in gp100_gr_init_shader_exceptions()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/sw/
Dgf100.c47 nvkm_wr32(device, 0x001718, 0x80000000 | inst); in gf100_sw_chan_vblsem_release()
49 nvkm_wr32(device, 0x06000c, upper_32_bits(chan->vblank.offset)); in gf100_sw_chan_vblsem_release()
50 nvkm_wr32(device, 0x060010, lower_32_bits(chan->vblank.offset)); in gf100_sw_chan_vblsem_release()
51 nvkm_wr32(device, 0x060014, chan->vblank.value); in gf100_sw_chan_vblsem_release()
63 case 0x0400: in gf100_sw_chan_mthd()
64 chan->vblank.offset &= 0x00ffffffffULL; in gf100_sw_chan_mthd()
67 case 0x0404: in gf100_sw_chan_mthd()
68 chan->vblank.offset &= 0xff00000000ULL; in gf100_sw_chan_mthd()
71 case 0x0408: in gf100_sw_chan_mthd()
74 case 0x040c: in gf100_sw_chan_mthd()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/sw/
Dgf100.c47 nvkm_wr32(device, 0x001718, 0x80000000 | inst); in gf100_sw_chan_vblsem_release()
49 nvkm_wr32(device, 0x06000c, upper_32_bits(chan->vblank.offset)); in gf100_sw_chan_vblsem_release()
50 nvkm_wr32(device, 0x060010, lower_32_bits(chan->vblank.offset)); in gf100_sw_chan_vblsem_release()
51 nvkm_wr32(device, 0x060014, chan->vblank.value); in gf100_sw_chan_vblsem_release()
63 case 0x0400: in gf100_sw_chan_mthd()
64 chan->vblank.offset &= 0x00ffffffffULL; in gf100_sw_chan_mthd()
67 case 0x0404: in gf100_sw_chan_mthd()
68 chan->vblank.offset &= 0xff00000000ULL; in gf100_sw_chan_mthd()
71 case 0x0408: in gf100_sw_chan_mthd()
74 case 0x040c: in gf100_sw_chan_mthd()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dgp100.c40 nvkm_wr32(device, 0x418010 + zoff, gr->zbc_color[zbc].ds[0]); in gp100_gr_zbc_clear_color()
41 nvkm_wr32(device, 0x41804c + zoff, gr->zbc_color[zbc].ds[1]); in gp100_gr_zbc_clear_color()
42 nvkm_wr32(device, 0x418088 + zoff, gr->zbc_color[zbc].ds[2]); in gp100_gr_zbc_clear_color()
43 nvkm_wr32(device, 0x4180c4 + zoff, gr->zbc_color[zbc].ds[3]); in gp100_gr_zbc_clear_color()
46 nvkm_mask(device, 0x418100 + ((znum / 4) * 4), in gp100_gr_zbc_clear_color()
47 0x0000007f << ((znum % 4) * 7), in gp100_gr_zbc_clear_color()
59 nvkm_wr32(device, 0x418110 + zoff, gr->zbc_depth[zbc].ds); in gp100_gr_zbc_clear_depth()
60 nvkm_mask(device, 0x41814c + ((znum / 4) * 4), in gp100_gr_zbc_clear_depth()
61 0x0000007f << ((znum % 4) * 7), in gp100_gr_zbc_clear_depth()
75 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); in gp100_gr_init_shader_exceptions()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/
Dnouveau_drv.h21 * - added support for software methods 0x600,0x644,0x6ac on nvc0
24 * bounds access to local memory to be silently ignored / return 0).
27 * 1.2.0:
34 * 1.3.0:
85 NVDRM_NOTIFY_NVIF = 0,
90 NVDRM_CHAN = 0xcccc0000, /* |= client chid */
91 NVDRM_NVSW = 0x55550000,
245 return !(mmu->type[drm->ttm.type_host[0]].type & NVIF_MEM_UNCACHED); in nouveau_drm_use_coherent_gpu_mapping()
262 } while(0)
272 } while(0)
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/
Dnouveau_drv.h14 #define DRIVER_PATCHLEVEL 0
21 * - added support for software methods 0x600,0x644,0x6ac on nvc0
24 * bounds access to local memory to be silently ignored / return 0).
27 * 1.2.0:
34 * 1.3.0:
83 NVDRM_CHAN = 0xcccc0000, /* |= client chid */
84 NVDRM_NVSW = 0x55550000,
253 int chan_nr; /* 0 if per-runlist CHIDs. */
317 return !(mmu->type[drm->ttm.type_host[0]].type & NVIF_MEM_UNCACHED); in nouveau_drm_use_coherent_gpu_mapping()
334 } while(0)
[all …]

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