| /kernel/linux/linux-6.6/drivers/pinctrl/mediatek/ |
| D | pinctrl-mt8365.c | 18 /* 0E4E8SR 4/8/12/16 */
20 /* 0E2E4SR 2/4/6/8 */
23 MTK_DRV_GRP(2, 16, 0, 2, 2)
28 MTK_PIN_DRV_GRP(0, 0x710, 0, 2),
29 MTK_PIN_DRV_GRP(1, 0x710, 0, 2),
30 MTK_PIN_DRV_GRP(2, 0x710, 0, 2),
31 MTK_PIN_DRV_GRP(3, 0x710, 0, 2),
32 MTK_PIN_DRV_GRP(4, 0x710, 4, 2),
33 MTK_PIN_DRV_GRP(5, 0x710, 4, 2),
34 MTK_PIN_DRV_GRP(6, 0x710, 4, 2),
[all …]
|
| /kernel/linux/linux-6.6/Documentation/userspace-api/media/v4l/ |
| D | pipeline.dot | 6 …scaler [label="{<scaler_0> 0} | Host\nScaler | {<scaler_1> 1} ", shape=Mrecord, style=filled, fill…
7 …frontend [label="{<frontend_0> 0} | Host\nFrontend | {<frontend_1> 1}", shape=Mrecord, style=fille…
8 sensor [label="Sensor | {<sensor_0> 0}", shape=Mrecord, style=filled, fillcolor=aquamarine]
9 io [label="{<io_0> 0} | V4L I/O", shape=Mrecord, style=filled, fillcolor=aquamarine]
13 scaler:scaler_1 -> io:io_0 [color=blue, label="HQ: 1280x720\nHS: 1280x720"]
|
| /kernel/linux/linux-5.10/Documentation/userspace-api/media/v4l/ |
| D | pipeline.dot | 6 …scaler [label="{<scaler_0> 0} | Host\nScaler | {<scaler_1> 1} ", shape=Mrecord, style=filled, fill…
7 …frontend [label="{<frontend_0> 0} | Host\nFrontend | {<frontend_1> 1}", shape=Mrecord, style=fille…
8 sensor [label="Sensor | {<sensor_0> 0}", shape=Mrecord, style=filled, fillcolor=aquamarine]
9 io [label="{<io_0> 0} | V4L I/O", shape=Mrecord, style=filled, fillcolor=aquamarine]
13 scaler:scaler_1 -> io:io_0 [color=blue, label="HQ: 1280x720\nHS: 1280x720"]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/panel/ |
| D | sony,tulip-truly-nt35521.yaml | 7 title: Sony Tulip Truly NT35521 5.24" 1280x720 MIPI-DSI Panel
13 The Sony Tulip Truly NT35521 is a 5.24" 1280x720 MIPI-DSI panel, which
55 #size-cells = <0>;
57 panel@0 {
59 reg = <0>;
|
| /kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh4/ |
| D | setup-sh4-202.c | 23 DEFINE_RES_MEM(0xffe80000, 0x100),
24 DEFINE_RES_IRQ(evt2irq(0x700)),
25 DEFINE_RES_IRQ(evt2irq(0x720)),
26 DEFINE_RES_IRQ(evt2irq(0x760)),
27 DEFINE_RES_IRQ(evt2irq(0x740)),
32 .id = 0,
45 DEFINE_RES_MEM(0xffd80000, 0x30),
46 DEFINE_RES_IRQ(evt2irq(0x400)),
47 DEFINE_RES_IRQ(evt2irq(0x420)),
48 DEFINE_RES_IRQ(evt2irq(0x440)),
[all …]
|
| /kernel/linux/linux-6.6/arch/sh/kernel/cpu/sh4/ |
| D | setup-sh4-202.c | 23 DEFINE_RES_MEM(0xffe80000, 0x100),
24 DEFINE_RES_IRQ(evt2irq(0x700)),
25 DEFINE_RES_IRQ(evt2irq(0x720)),
26 DEFINE_RES_IRQ(evt2irq(0x760)),
27 DEFINE_RES_IRQ(evt2irq(0x740)),
32 .id = 0,
45 DEFINE_RES_MEM(0xffd80000, 0x30),
46 DEFINE_RES_IRQ(evt2irq(0x400)),
47 DEFINE_RES_IRQ(evt2irq(0x420)),
48 DEFINE_RES_IRQ(evt2irq(0x440)),
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/ |
| D | drm_edid.c | 63 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
97 #define LEVEL_DMT 0
110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
[all …]
|
| /kernel/linux/linux-5.10/include/dt-bindings/clock/ |
| D | am4.h | 8 #define AM4_CLKCTRL_OFFSET 0x20
14 #define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120)
15 #define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
16 #define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228)
17 #define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230)
18 #define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328)
19 #define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338)
20 #define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340)
21 #define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348)
22 #define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350)
[all …]
|
| /kernel/linux/linux-6.6/include/dt-bindings/clock/ |
| D | am4.h | 8 #define AM4_CLKCTRL_OFFSET 0x20
12 #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
14 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
17 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228
19 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
20 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
23 #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
25 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
26 #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
27 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/ |
| D | drm_edid.c | 65 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
93 #define MICROSOFT_IEEE_OUI 0xca125c
102 #define LEVEL_DMT 0
121 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
123 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
124 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
127 EDID_QUIRK('B', 'N', 'Q', 0x78d6, EDID_QUIRK_FORCE_8BPC),
130 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
133 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
136 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/include/asm/hardware/ |
| D | cache-aurora-l2.h | 14 #define AURORA_SYNC_REG 0x700
15 #define AURORA_RANGE_BASE_ADDR_REG 0x720
16 #define AURORA_FLUSH_PHY_ADDR_REG 0x7f0
17 #define AURORA_INVAL_RANGE_REG 0x774
18 #define AURORA_CLEAN_RANGE_REG 0x7b4
19 #define AURORA_FLUSH_RANGE_REG 0x7f4
23 (0x3 << AURORA_ACR_REPLACEMENT_OFFSET)
25 (0 << AURORA_ACR_REPLACEMENT_OFFSET)
34 #define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET 0
36 (0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/include/asm/hardware/ |
| D | cache-aurora-l2.h | 17 #define AURORA_SYNC_REG 0x700
18 #define AURORA_RANGE_BASE_ADDR_REG 0x720
19 #define AURORA_FLUSH_PHY_ADDR_REG 0x7f0
20 #define AURORA_INVAL_RANGE_REG 0x774
21 #define AURORA_CLEAN_RANGE_REG 0x7b4
22 #define AURORA_FLUSH_RANGE_REG 0x7f4
26 (0x3 << AURORA_ACR_REPLACEMENT_OFFSET)
28 (0 << AURORA_ACR_REPLACEMENT_OFFSET)
37 #define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET 0
39 (0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
[all …]
|
| /kernel/linux/linux-6.6/Documentation/fb/ |
| D | viafb.modes | 256 # 0 chars 7 lines
268 timings 14667 216 0 14 7 64 4 hsync high vsync high endmode
487 # 0 chars 0 lines
499 timings 8825 280 0 16 0 88 8 endmode mode "1152x720-60"
524 hsync high vsync high endmode mode "1200x720-60"
530 timings 16260 184 28 18 1 128 3 endmode mode "1280x720-50"
779 # 1280x720, 60 Hz, Non-Interlaced (74.481 MHz dotclock)
796 mode "1280x720-60"
|
| /kernel/linux/linux-5.10/Documentation/fb/ |
| D | viafb.modes | 256 # 0 chars 7 lines
268 timings 14667 216 0 14 7 64 4 hsync high vsync high endmode
487 # 0 chars 0 lines
499 timings 8825 280 0 16 0 88 8 endmode mode "1152x720-60"
524 hsync high vsync high endmode mode "1200x720-60"
530 timings 16260 184 28 18 1 128 3 endmode mode "1280x720-50"
779 # 1280x720, 60 Hz, Non-Interlaced (74.481 MHz dotclock)
796 mode "1280x720-60"
|
| /kernel/linux/linux-6.6/drivers/phy/samsung/ |
| D | phy-exynos7-ufs.c | 10 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL 0x720
11 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
12 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
14 #define EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e
18 PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
19 PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
20 PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
21 PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY),
22 PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
23 PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
[all …]
|
| /kernel/linux/linux-5.10/drivers/phy/samsung/ |
| D | phy-exynos7-ufs.h | 12 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL 0x720
13 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
14 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
18 PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
19 PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
20 PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
21 PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY),
22 PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
23 PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
24 PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
[all …]
|
| /kernel/linux/linux-6.6/drivers/video/fbdev/sis/ |
| D | init.h | 70 static const unsigned short ModeIndex_320x200[] = {0x59, 0x41, 0x00, 0x4f};
71 static const unsigned short ModeIndex_320x240[] = {0x50, 0x56, 0x00, 0x53};
72 static const unsigned short ModeIndex_320x240_FSTN[] = {0x5a, 0x5b, 0x00, 0x00}; /* FSTN */
73 static const unsigned short ModeIndex_400x300[] = {0x51, 0x57, 0x00, 0x54};
74 static const unsigned short ModeIndex_512x384[] = {0x52, 0x58, 0x00, 0x5c};
75 static const unsigned short ModeIndex_640x400[] = {0x2f, 0x5d, 0x00, 0x5e};
76 static const unsigned short ModeIndex_640x480[] = {0x2e, 0x44, 0x00, 0x62};
77 static const unsigned short ModeIndex_720x480[] = {0x31, 0x33, 0x00, 0x35};
78 static const unsigned short ModeIndex_720x576[] = {0x32, 0x34, 0x00, 0x36};
79 static const unsigned short ModeIndex_768x576[] = {0x5f, 0x60, 0x00, 0x61};
[all …]
|
| /kernel/linux/linux-5.10/drivers/video/fbdev/sis/ |
| D | init.h | 70 static const unsigned short ModeIndex_320x200[] = {0x59, 0x41, 0x00, 0x4f};
71 static const unsigned short ModeIndex_320x240[] = {0x50, 0x56, 0x00, 0x53};
72 static const unsigned short ModeIndex_320x240_FSTN[] = {0x5a, 0x5b, 0x00, 0x00}; /* FSTN */
73 static const unsigned short ModeIndex_400x300[] = {0x51, 0x57, 0x00, 0x54};
74 static const unsigned short ModeIndex_512x384[] = {0x52, 0x58, 0x00, 0x5c};
75 static const unsigned short ModeIndex_640x400[] = {0x2f, 0x5d, 0x00, 0x5e};
76 static const unsigned short ModeIndex_640x480[] = {0x2e, 0x44, 0x00, 0x62};
77 static const unsigned short ModeIndex_720x480[] = {0x31, 0x33, 0x00, 0x35};
78 static const unsigned short ModeIndex_720x576[] = {0x32, 0x34, 0x00, 0x36};
79 static const unsigned short ModeIndex_768x576[] = {0x5f, 0x60, 0x00, 0x61};
[all …]
|
| /kernel/linux/linux-6.6/Documentation/admin-guide/media/ |
| D | vimc.rst | 36 media-ctl -d platform:vimc -V '"Sensor A":0[fmt:SBGGR8_1X8/640x480]'
37 media-ctl -d platform:vimc -V '"Debayer A":0[fmt:SBGGR8_1X8/640x480]'
38 media-ctl -d platform:vimc -V '"Scaler":0[fmt:RGB888_1X24/640x480]'
39 media-ctl -d platform:vimc -V '"Scaler":0[crop:(100,50)/400x150]'
42 v4l2-ctl -z platform:vimc -d "Raw Capture 0" -v pixelformat=BA81
65 - entity 28: Lens A (0 pad, 0 link)
66 type V4L2 subdev subtype Lens flags 0
68 - entity 29: Lens B (0 pad, 0 link)
69 type V4L2 subdev subtype Lens flags 0
72 focus_absolute: 0
[all …]
|
| /kernel/linux/linux-6.6/include/linux/usb/ |
| D | usb338x.h | 19 #define SCRATCH 0x0b
36 #define USB3380_EP_CFG_MASK_IN ((0x3 << IN_ENDPOINT_TYPE) | \
38 #define USB3380_EP_CFG_MASK_OUT ((0x3 << OUT_ENDPOINT_TYPE) | \
45 #define DEVICE_CLASS 0
48 #define U1_SYSTEM_EXIT_LATENCY 0
51 #define U1_DEVICE_EXIT_LATENCY 0
55 #define USB_L1_LPM_SUPPORT 0
58 #define BEST_EFFORT_LATENCY_TOLERANCE 0
66 #define SERIAL_NUMBER_STRING_ENABLE 0
79 #define GPEP0_TIMEOUT_ENABLE 0
[all …]
|
| /kernel/linux/linux-5.10/include/linux/usb/ |
| D | usb338x.h | 30 #define SCRATCH 0x0b
47 #define USB3380_EP_CFG_MASK_IN ((0x3 << IN_ENDPOINT_TYPE) | \
49 #define USB3380_EP_CFG_MASK_OUT ((0x3 << OUT_ENDPOINT_TYPE) | \
56 #define DEVICE_CLASS 0
59 #define U1_SYSTEM_EXIT_LATENCY 0
62 #define U1_DEVICE_EXIT_LATENCY 0
66 #define USB_L1_LPM_SUPPORT 0
69 #define BEST_EFFORT_LATENCY_TOLERANCE 0
77 #define SERIAL_NUMBER_STRING_ENABLE 0
90 #define GPEP0_TIMEOUT_ENABLE 0
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/sti/ |
| D | sti_hda.c | 23 #define HDA_ANA_CFG 0x0000
24 #define HDA_ANA_SCALE_CTRL_Y 0x0004
25 #define HDA_ANA_SCALE_CTRL_CB 0x0008
26 #define HDA_ANA_SCALE_CTRL_CR 0x000C
27 #define HDA_ANA_ANC_CTRL 0x0010
28 #define HDA_ANA_SRC_Y_CFG 0x0014
29 #define HDA_COEFF_Y_PH1_TAP123 0x0018
30 #define HDA_COEFF_Y_PH1_TAP456 0x001C
31 #define HDA_COEFF_Y_PH2_TAP123 0x0020
32 #define HDA_COEFF_Y_PH2_TAP456 0x0024
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/sti/ |
| D | sti_hda.c | 24 #define HDA_ANA_CFG 0x0000
25 #define HDA_ANA_SCALE_CTRL_Y 0x0004
26 #define HDA_ANA_SCALE_CTRL_CB 0x0008
27 #define HDA_ANA_SCALE_CTRL_CR 0x000C
28 #define HDA_ANA_ANC_CTRL 0x0010
29 #define HDA_ANA_SRC_Y_CFG 0x0014
30 #define HDA_COEFF_Y_PH1_TAP123 0x0018
31 #define HDA_COEFF_Y_PH1_TAP456 0x001C
32 #define HDA_COEFF_Y_PH2_TAP123 0x0020
33 #define HDA_COEFF_Y_PH2_TAP456 0x0024
[all …]
|
| /kernel/linux/linux-6.6/arch/sh/kernel/cpu/sh4a/ |
| D | setup-shx3.c | 20 * This intentionally only registers SCIF ports 0, 1, and 3. SCIF 2
34 DEFINE_RES_MEM(0xffc30000, 0x100),
35 DEFINE_RES_IRQ(evt2irq(0x700)),
36 DEFINE_RES_IRQ(evt2irq(0x720)),
37 DEFINE_RES_IRQ(evt2irq(0x760)),
38 DEFINE_RES_IRQ(evt2irq(0x740)),
43 .id = 0,
57 DEFINE_RES_MEM(0xffc40000, 0x100),
58 DEFINE_RES_IRQ(evt2irq(0x780)),
59 DEFINE_RES_IRQ(evt2irq(0x7a0)),
[all …]
|
| /kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh4a/ |
| D | setup-shx3.c | 20 * This intentionally only registers SCIF ports 0, 1, and 3. SCIF 2
34 DEFINE_RES_MEM(0xffc30000, 0x100),
35 DEFINE_RES_IRQ(evt2irq(0x700)),
36 DEFINE_RES_IRQ(evt2irq(0x720)),
37 DEFINE_RES_IRQ(evt2irq(0x760)),
38 DEFINE_RES_IRQ(evt2irq(0x740)),
43 .id = 0,
57 DEFINE_RES_MEM(0xffc40000, 0x100),
58 DEFINE_RES_IRQ(evt2irq(0x780)),
59 DEFINE_RES_IRQ(evt2irq(0x7a0)),
[all …]
|