| /kernel/linux/linux-6.6/arch/arm/include/asm/hardware/ |
| D | cp14.h | 45 #define RCP14_DBGDIDR() MRC14(0, c0, c0, 0)
46 #define RCP14_DBGDSCRint() MRC14(0, c0, c1, 0)
47 #define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0)
48 #define RCP14_DBGWFAR() MRC14(0, c0, c6, 0)
49 #define RCP14_DBGVCR() MRC14(0, c0, c7, 0)
50 #define RCP14_DBGECR() MRC14(0, c0, c9, 0)
51 #define RCP14_DBGDSCCR() MRC14(0, c0, c10, 0)
52 #define RCP14_DBGDSMCR() MRC14(0, c0, c11, 0)
53 #define RCP14_DBGDTRRXext() MRC14(0, c0, c0, 2)
54 #define RCP14_DBGDSCRext() MRC14(0, c0, c2, 2)
[all …]
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| /kernel/linux/linux-5.10/arch/arm/include/asm/hardware/ |
| D | cp14.h | 45 #define RCP14_DBGDIDR() MRC14(0, c0, c0, 0)
46 #define RCP14_DBGDSCRint() MRC14(0, c0, c1, 0)
47 #define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0)
48 #define RCP14_DBGWFAR() MRC14(0, c0, c6, 0)
49 #define RCP14_DBGVCR() MRC14(0, c0, c7, 0)
50 #define RCP14_DBGECR() MRC14(0, c0, c9, 0)
51 #define RCP14_DBGDSCCR() MRC14(0, c0, c10, 0)
52 #define RCP14_DBGDSMCR() MRC14(0, c0, c11, 0)
53 #define RCP14_DBGDTRRXext() MRC14(0, c0, c0, 2)
54 #define RCP14_DBGDSCRext() MRC14(0, c0, c2, 2)
[all …]
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| /kernel/liteos_a/arch/arm/arm/include/ |
| D | arm.h | 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
42 __asm__ volatile("mrc p15, 0, %0, c1,c0,0" : "=r"(val)); in OsArmReadSctlr()
48 __asm__ volatile("mcr p15, 0, %0, c1,c0,0" ::"r"(val)); in OsArmWriteSctlr()
55 __asm__ volatile("mrc p15, 0, %0, c1,c0,1" : "=r"(val)); in OsArmReadActlr()
61 __asm__ volatile("mcr p15, 0, %0, c1,c0,1" ::"r"(val)); in OsArmWriteActlr()
68 __asm__ volatile("mrc p15, 0, %0, c1,c0,2" : "=r"(val)); in OsArmReadCpacr()
74 __asm__ volatile("mcr p15, 0, %0, c1,c0,2" ::"r"(val)); in OsArmWriteCpacr()
81 __asm__ volatile("mrc p15, 0, %0, c2,c0,0" : "=r"(val)); in OsArmReadTtbr()
87 __asm__ volatile("mcr p15, 0, %0, c2,c0,0" ::"r"(val)); in OsArmWriteTtbr()
94 __asm__ volatile("mrc p15, 0, %0, c2,c0,0" : "=r"(val)); in OsArmReadTtbr0()
[all …]
|
| D | los_hw_cpu.h | 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
90 * Identification registers (c0)
92 #define MIDR CP15_REG(c0, 0, c0, 0) /* Main ID Register */
93 #define MPIDR CP15_REG(c0, 0, c0, 5) /* Multiprocessor Affinity Register */
94 #define CCSIDR CP15_REG(c0, 1, c0, 0) /* Cache Size ID Registers */
95 #define CLIDR CP15_REG(c0, 1, c0, 1) /* Cache Level ID Register */
96 #define VPIDR CP15_REG(c0, 4, c0, 0) /* Virtualization Processor ID Register */
97 #define VMPIDR CP15_REG(c0, 4, c0, 5) /* Virtualization Multiprocessor ID Register …
102 #define SCTLR CP15_REG(c1, 0, c0, 0) /* System Control Register */
103 #define ACTLR CP15_REG(c1, 0, c0, 1) /* Auxiliary Control Register */
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/ |
| D | g98.fuc0s | 7 * the Free Software Foundation; either version 2 of the License, or
194 mov $r5 2
240 shl b32 $r5 $r4 2
259 ld b16 $r6 D[$r4 + 2]
260 cmpu b32 $r6 2
342 or $r2 2
349 // if < 2, no QUERY object is involved
350 cmpu b32 $r3 2
374 // if == 2, only a single QUERY is involved...
375 cmpu b32 $r3 2
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/ |
| D | g98.fuc0s | 7 * the Free Software Foundation; either version 2 of the License, or
194 mov $r5 2
240 shl b32 $r5 $r4 2
259 ld b16 $r6 D[$r4 + 2]
260 cmpu b32 $r6 2
342 or $r2 2
349 // if < 2, no QUERY object is involved
350 cmpu b32 $r3 2
374 // if == 2, only a single QUERY is involved...
375 cmpu b32 $r3 2
[all …]
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| /kernel/linux/linux-6.6/tools/testing/selftests/hid/tests/ |
| D | test_tablet.py | 54 raise ValueError("2 tools are not allowed")
374 input_info=(BusType.USB, 1, 2), argument
703 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75…
711 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75…
719 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75…
727 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75…
735 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75…
743 …2c 26 ff 7f 81 02 05 0d 09 55 25 08 75 08 95 01 b1 02 c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05…
751 …c0 c0 05 0d 09 04 a1 01 85 30 09 22 a1 02 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 09 47 81…
759 …c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 95 06 81 03 75 08 09 51 95 01 81 02…
[all …]
|
| D | test_multitouch.py | 30 "CYPRESS": BIT(2),
109 input_info=(BusType.USB, 1, 2), argument
222 elif value == 2:
346 Report ID (2)
396 {rdesc_finger_str * 2}
408 Report ID (2)
478 Report ID (2)
492 …c0 c0 05 0d 09 06 15 00 26 ff 00 a1 01 85 02 75 08 95 3f 09 00 82 02 01 95 3f 09 00 92 02 01 c0 05…
552 if uhdev.max_contacts > 2:
553 assert evdev.slots[2][libevdev.EV_ABS.ABS_MT_TRACKING_ID] == -1
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mm/ |
| D | proc-v7.S | 24 #include "proc-v7-2level.S"
32 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
35 mcr p15, 0, r0, c1, c0, 0 @ disable caches
55 mrc p15, 0, r2, c1, c0, 0 @ ctrl register
58 mcr p15, 0, r2, c1, c0, 0 @ disable MMU
86 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
89 bhi 2b
134 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
135 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
138 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
[all …]
|
| D | proc-v6.S | 24 #define TTB_IMP (1 << 2)
27 #define TTB_RGN_WT (2 << 3)
39 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
42 mcr p15, 0, r0, c1, c0, 0 @ disable caches
57 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
59 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
76 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
104 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
106 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
111 mcr p15, 0, r1, c13, c0, 1 @ set context ID
[all …]
|
| D | proc-arm740.S | 37 mrc p15, 0, r0, c1, c0, 0
40 mcr p15, 0, r0, c1, c0, 0 @ disable caches
51 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
52 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
54 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
62 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
71 mcr p15, 0, r0, c6, c0 @ set area 0, default
76 1: add r4, r4, #1 @ area size *= 2
87 beq 2f
89 1: add r4, r4, #1 @ area size *= 2
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/mm/ |
| D | proc-v7.S | 24 #include "proc-v7-2level.S"
34 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
37 mcr p15, 0, r0, c1, c0, 0 @ disable caches
57 mrc p15, 0, r2, c1, c0, 0 @ ctrl register
60 mcr p15, 0, r2, c1, c0, 0 @ disable MMU
88 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
91 bhi 2b
136 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
137 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
140 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
[all …]
|
| D | proc-v6.S | 24 #define TTB_IMP (1 << 2)
27 #define TTB_RGN_WT (2 << 3)
41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
59 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
61 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
78 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
106 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
108 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
113 mcr p15, 0, r1, c13, c0, 1 @ set context ID
[all …]
|
| D | proc-arm740.S | 37 mrc p15, 0, r0, c1, c0, 0
40 mcr p15, 0, r0, c1, c0, 0 @ disable caches
51 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
52 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
54 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
62 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
71 mcr p15, 0, r0, c6, c0 @ set area 0, default
76 1: add r4, r4, #1 @ area size *= 2
87 beq 2f
89 1: add r4, r4, #1 @ area size *= 2
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/tidss/ |
| D | tidss_scale_coefs.c | 17 .c2 = { 28, 34, 40, 46, 52, 58, 64, 70, 0, 2, 4, 8, 12, 16, 20, 24, },
19 .c0 = { 192, 192, 192, 190, 188, 186, 184, 182, 180, },
23 .c2 = { 24, 28, 32, 38, 44, 50, 56, 64, 0, 2, 4, 6, 8, 12, 16, 20, },
25 .c0 = { 200, 202, 204, 202, 200, 196, 192, 188, 184, },
29 .c2 = { 16, 20, 24, 30, 36, 42, 48, 56, 0, 0, 0, 2, 4, 8, 12, 14, },
31 .c0 = { 216, 216, 216, 214, 212, 208, 204, 198, 192, },
35 .c2 = { 12, 14, 16, 22, 28, 34, 40, 48, 0, 0, 0, 2, 4, 4, 4, 8, },
37 .c0 = { 232, 232, 232, 226, 220, 218, 216, 208, 200, },
41 .c2 = { 0, 2, 4, 8, 12, 18, 24, 32, 0, 0, 0, -2, -4, -4, -4, -2, },
43 .c0 = { 264, 262, 260, 254, 248, 242, 236, 226, 216, },
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/tidss/ |
| D | tidss_scale_coefs.c | 17 .c2 = { 28, 34, 40, 46, 52, 58, 64, 70, 0, 2, 4, 8, 12, 16, 20, 24, },
19 .c0 = { 192, 192, 192, 190, 188, 186, 184, 182, 180, },
23 .c2 = { 24, 28, 32, 38, 44, 50, 56, 64, 0, 2, 4, 6, 8, 12, 16, 20, },
25 .c0 = { 200, 202, 204, 202, 200, 196, 192, 188, 184, },
29 .c2 = { 16, 20, 24, 30, 36, 42, 48, 56, 0, 0, 0, 2, 4, 8, 12, 14, },
31 .c0 = { 216, 216, 216, 214, 212, 208, 204, 198, 192, },
35 .c2 = { 12, 14, 16, 22, 28, 34, 40, 48, 0, 0, 0, 2, 4, 4, 4, 8, },
37 .c0 = { 232, 232, 232, 226, 220, 218, 216, 208, 200, },
41 .c2 = { 0, 2, 4, 8, 12, 18, 24, 32, 0, 0, 0, -2, -4, -4, -4, -2, },
43 .c0 = { 264, 262, 260, 254, 248, 242, 236, 226, 216, },
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/kernel/ |
| D | hyp-stub.S | 21 .align 2
27 * Save the primary CPU boot mode. Requires 2 scratch registers.
39 * Requires 2 additional scratch registers.
114 mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR)
119 mcr p15, 4, r7, c1, c1, 2 @ HCPTR
124 mcr p15, 4, r7, c1, c0, 0 @ HSCTLR
131 mrc p15, 0, r7, c1, c0, 0 @ SCTLR
135 mcr p15, 0, r7, c1, c0, 0 @ SCTLR
137 mrc p15, 0, r7, c0, c0, 0 @ MIDR
138 mcr p15, 4, r7, c0, c0, 0 @ VPIDR
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/kernel/ |
| D | hyp-stub.S | 23 .align 2
29 * Save the primary CPU boot mode. Requires 2 scratch registers.
41 * Requires 2 additional scratch registers.
116 mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR)
121 mcr p15, 4, r7, c1, c1, 2 @ HCPTR
126 mcr p15, 4, r7, c1, c0, 0 @ HSCTLR
133 mrc p15, 0, r7, c1, c0, 0 @ SCTLR
137 mcr p15, 0, r7, c1, c0, 0 @ SCTLR
139 mrc p15, 0, r7, c0, c0, 0 @ MIDR
140 mcr p15, 4, r7, c0, c0, 0 @ VPIDR
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/include/debug/ |
| D | icedcc.S | 16 mcr p14, 0, \rd, c0, c5, 0
21 mrc p14, 0, \rx, c0, c1, 0
34 mrc p14, 0, \rx, c0, c1, 0
43 mcr p14, 0, \rd, c8, c0, 0
48 mrc p14, 0, \rx, c14, c0, 0
61 mrc p14, 0, \rx, c14, c0, 0
70 mcr p14, 0, \rd, c1, c0, 0
75 mrc p14, 0, \rx, c0, c0, 0
76 tst \rx, #2
89 mrc p14, 0, \rx, c0, c0, 0
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/include/debug/ |
| D | icedcc.S | 16 mcr p14, 0, \rd, c0, c5, 0
21 mrc p14, 0, \rx, c0, c1, 0
34 mrc p14, 0, \rx, c0, c1, 0
43 mcr p14, 0, \rd, c8, c0, 0
48 mrc p14, 0, \rx, c14, c0, 0
61 mrc p14, 0, \rx, c14, c0, 0
70 mcr p14, 0, \rd, c1, c0, 0
75 mrc p14, 0, \rx, c0, c0, 0
76 tst \rx, #2
89 mrc p14, 0, \rx, c0, c0, 0
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/include/asm/ |
| D | tls.h | 14 mrc p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register
15 mcr p15, 0, \tp, c13, c0, 3 @ set TLS register
16 mcr p15, 0, \tpuser, c13, c0, 2 @ and the user r/w register
26 mrcne p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register
27 mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register
28 mcrne p15, 0, \tpuser, c13, c0, 2 @ set user r/w register
82 asm("mcr p15, 0, %0, c13, c0, 3" in set_tls()
105 __asm__("mrc p15, 0, %0, c13, c0, 2" : "=r" (reg)); in get_tpuser()
116 asm("mcr p15, 0, %0, c13, c0, 2" in set_tpuser()
|
| /kernel/linux/linux-6.6/tools/testing/selftests/cgroup/ |
| D | test_cpuset_prs.sh | 40 DELAY_FACTOR=2
43 -d) DELAY_FACTOR=$2
70 rmdir A1/A2/A3 A1/A2 A1 B1 > /dev/null 2>&1
72 rmdir test > /dev/null 2>&1
142 echo 2-3 > cpuset.cpus
173 echo 2-3 > cpuset.cpus
175 test_effective_cpus 2-3
187 echo 2 > cpuset.cpus
191 echo 2-3 > cpuset.cpus
209 # P<v> = set cpus.partition (0:member, 1:root, 2:isolated, -1:root invalid)
[all …]
|
| /kernel/linux/linux-6.6/arch/s390/crypto/ |
| D | chacha-s390.S | 22 .long 2,0,0,0
26 .long 0,1,2,3
101 VREPF XB2,K1,2
106 VREPF XD2,K3,2
112 VREPF XC2,K2,2
442 #define C0 %v2 macro
509 VAF D2,K3,T2 # K[3]+2
514 VLR C0,K2
545 VAF C0,C0,D0
551 VX B0,B0,C0
[all …]
|
| /kernel/linux/linux-6.6/tools/testing/selftests/net/forwarding/ |
| D | bridge_igmp.sh | 17 MZPKT_IS_INC="22:00:9d:de:00:00:00:01:01:00:00:03:ef:0a:0a:0a:c0:00:02:01:c0:00:02:02:c0:00:02:03"
19 MZPKT_IS_INC2="22:00:9d:c3:00:00:00:01:01:00:00:03:ef:0a:0a:0a:c0:00:02:0a:c0:00:02:0b:c0:00:02:0c"
21 MZPKT_IS_INC3="22:00:5f:b4:00:00:00:01:01:00:00:02:ef:0a:0a:0a:c0:00:02:14:c0:00:02:1e"
23 MZPKT_ALLOW="22:00:99:c3:00:00:00:01:05:00:00:03:ef:0a:0a:0a:c0:00:02:0a:c0:00:02:0b:c0:00:02:0c"
25 MZPKT_ALLOW2="22:00:5b:b4:00:00:00:01:05:00:00:02:ef:0a:0a:0a:c0:00:02:14:c0:00:02:1e"
27 …_IS_EXC="22:00:da:b6:00:00:00:01:02:00:00:04:ef:0a:0a:0a:c0:00:02:01:c0:00:02:02:c0:00:02:14:c0:00…
29 MZPKT_IS_EXC2="22:00:5e:b4:00:00:00:01:02:00:00:02:ef:0a:0a:0a:c0:00:02:14:c0:00:02:1e"
31 MZPKT_TO_EXC="22:00:9a:b1:00:00:00:01:04:00:00:03:ef:0a:0a:0a:c0:00:02:01:c0:00:02:14:c0:00:02:1e"
33 MZPKT_BLOCK="22:00:98:b1:00:00:00:01:06:00:00:03:ef:0a:0a:0a:c0:00:02:01:c0:00:02:14:c0:00:02:1e"
49 simple_if_init $h2 192.0.2.2/24 2001:db8:1::2/64
[all …]
|
| /kernel/liteos_a/arch/arm/arm/src/startup/ |
| D | reset_vector_mp.S | 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
121 mcr p15, 0, r0, c13, c0, 4
123 mrc p15, 0, r0, c1, c0, 0
125 bic r0, #(1 << 2) /* d cache */
127 mcr p15, 0, r0, c1, c0, 0
131 MRC p15, 0, r0, c1, c1, 2
134 MCR p15, 0, r0, c1, c1, 2
137 MCR p15, 0, r0, c1, c0, 2
148 mrc p15, 0, r12, c0, c0, 5 /* r12: get cpuid */
204 str r12, [r4, r7, lsr #(20 - 2)] /* jumpTable[paIndex] = pt entry */
[all …]
|