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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
Damdgpu_ring.c40 * Most engines on the GPU are fed via ring buffers. Ring
46 * pointers are equal, the ring is idle. When the host
47 * writes commands to the ring buffer, it increments the
53 * amdgpu_ring_max_ibs - Return max IBs that fit in a single submission.
55 * @type: ring type for which to return the limit.
73 * amdgpu_ring_alloc - allocate space on the ring buffer
75 * @ring: amdgpu_ring structure holding ring information
76 * @ndw: number of dwords to allocate in the ring buffer
78 * Allocate @ndw dwords in the ring buffer (all asics).
81 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw) in amdgpu_ring_alloc() argument
[all …]
Damdgpu_ih.c24 #include <linux/dma-mapping.h>
30 * amdgpu_ih_ring_init - initialize the IH state
33 * @ih: ih ring to initialize
34 * @ring_size: ring size to allocate
38 * for the IH ring buffer.
47 /* Align ring size */ in amdgpu_ih_ring_init()
48 rb_bufsz = order_base_2(ring_size / 4); in amdgpu_ih_ring_init()
49 ring_size = (1 << rb_bufsz) * 4; in amdgpu_ih_ring_init()
50 ih->ring_size = ring_size; in amdgpu_ih_ring_init()
51 ih->ptr_mask = ih->ring_size - 1; in amdgpu_ih_ring_init()
[all …]
Dsdma_v4_0.c399 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); in sdma_v4_0_get_reg_offset()
401 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset); in sdma_v4_0_get_reg_offset()
403 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset); in sdma_v4_0_get_reg_offset()
405 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset); in sdma_v4_0_get_reg_offset()
406 case 4: in sdma_v4_0_get_reg_offset()
407 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset); in sdma_v4_0_get_reg_offset()
409 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset); in sdma_v4_0_get_reg_offset()
411 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset); in sdma_v4_0_get_reg_offset()
413 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset); in sdma_v4_0_get_reg_offset()
431 case 4: in sdma_v4_0_seq_to_irq_id()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Damdgpu_ring.c40 * Most engines on the GPU are fed via ring buffers. Ring
46 * pointers are equal, the ring is idle. When the host
47 * writes commands to the ring buffer, it increments the
53 * amdgpu_ring_alloc - allocate space on the ring buffer
56 * @ring: amdgpu_ring structure holding ring information
57 * @ndw: number of dwords to allocate in the ring buffer
59 * Allocate @ndw dwords in the ring buffer (all asics).
62 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw) in amdgpu_ring_alloc() argument
66 ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask; in amdgpu_ring_alloc()
71 if (WARN_ON_ONCE(ndw > ring->max_dw)) in amdgpu_ring_alloc()
[all …]
Damdgpu_ih.c24 #include <linux/dma-mapping.h>
30 * amdgpu_ih_ring_init - initialize the IH state
33 * @ih: ih ring to initialize
34 * @ring_size: ring size to allocate
38 * for the IH ring buffer.
47 /* Align ring size */ in amdgpu_ih_ring_init()
48 rb_bufsz = order_base_2(ring_size / 4); in amdgpu_ih_ring_init()
49 ring_size = (1 << rb_bufsz) * 4; in amdgpu_ih_ring_init()
50 ih->ring_size = ring_size; in amdgpu_ih_ring_init()
51 ih->ptr_mask = ih->ring_size - 1; in amdgpu_ih_ring_init()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/broadcom/
Dbgmac.c33 dev_err(bgmac->dev, "Timeout waiting for reg 0x%X\n", reg); in bgmac_wait_value()
41 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) in bgmac_dma_tx_reset() argument
46 if (!ring->mmio_base) in bgmac_dma_tx_reset()
49 /* Suspend DMA TX ring first. in bgmac_dma_tx_reset()
53 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, in bgmac_dma_tx_reset()
56 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); in bgmac_dma_tx_reset()
67 dev_err(bgmac->dev, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n", in bgmac_dma_tx_reset()
68 ring->mmio_base, val); in bgmac_dma_tx_reset()
71 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0); in bgmac_dma_tx_reset()
73 ring->mmio_base + BGMAC_DMA_TX_STATUS, in bgmac_dma_tx_reset()
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/broadcom/
Dbgmac.c33 dev_err(bgmac->dev, "Timeout waiting for reg 0x%X\n", reg); in bgmac_wait_value()
41 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) in bgmac_dma_tx_reset() argument
46 if (!ring->mmio_base) in bgmac_dma_tx_reset()
49 /* Suspend DMA TX ring first. in bgmac_dma_tx_reset()
53 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, in bgmac_dma_tx_reset()
56 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); in bgmac_dma_tx_reset()
67 dev_err(bgmac->dev, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n", in bgmac_dma_tx_reset()
68 ring->mmio_base, val); in bgmac_dma_tx_reset()
71 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0); in bgmac_dma_tx_reset()
73 ring->mmio_base + BGMAC_DMA_TX_STATUS, in bgmac_dma_tx_reset()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/apm/xgene/
Dxgene_enet_ring2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Applied Micro X-Gene SoC Ethernet Driver
12 static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring) in xgene_enet_ring_init() argument
14 u32 *ring_cfg = ring->state; in xgene_enet_ring_init()
15 u64 addr = ring->dma; in xgene_enet_ring_init()
17 if (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU) { in xgene_enet_ring_init()
18 ring_cfg[0] |= SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK); in xgene_enet_ring_init()
27 ring_cfg[3] |= SET_VAL(RINGSIZE, ring->cfgsize) in xgene_enet_ring_init()
30 ring_cfg[4] |= SET_VAL(X2_SELTHRSH, 1); in xgene_enet_ring_init()
34 static void xgene_enet_ring_set_type(struct xgene_enet_desc_ring *ring) in xgene_enet_ring_set_type() argument
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/apm/xgene/
Dxgene_enet_ring2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Applied Micro X-Gene SoC Ethernet Driver
12 static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring) in xgene_enet_ring_init() argument
14 u32 *ring_cfg = ring->state; in xgene_enet_ring_init()
15 u64 addr = ring->dma; in xgene_enet_ring_init()
17 if (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU) { in xgene_enet_ring_init()
18 ring_cfg[0] |= SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK); in xgene_enet_ring_init()
27 ring_cfg[3] |= SET_VAL(RINGSIZE, ring->cfgsize) in xgene_enet_ring_init()
30 ring_cfg[4] |= SET_VAL(X2_SELTHRSH, 1); in xgene_enet_ring_init()
34 static void xgene_enet_ring_set_type(struct xgene_enet_desc_ring *ring) in xgene_enet_ring_set_type() argument
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Dr600_dma.c35 * to the 3D engine (ring buffer, IBs, etc.), but the
44 * r600_dma_get_rptr - get the current read pointer
47 * @ring: radeon ring pointer
52 struct radeon_ring *ring) in r600_dma_get_rptr() argument
56 if (rdev->wb.enabled) in r600_dma_get_rptr()
57 rptr = rdev->wb.wb[ring->rptr_offs/4]; in r600_dma_get_rptr()
65 * r600_dma_get_wptr - get the current write pointer
68 * @ring: radeon ring pointer
73 struct radeon_ring *ring) in r600_dma_get_wptr() argument
79 * r600_dma_set_wptr - commit the write pointer
[all …]
Dradeon_ring.c38 * Most engines on the GPU are fed via ring buffers. Ring
44 * pointers are equal, the ring is idle. When the host
45 * writes commands to the ring buffer, it increments the
49 static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring);
52 * radeon_ring_supports_scratch_reg - check if the ring supports
56 * @ring: radeon_ring structure holding ring information
58 * Check if a specific ring supports writing to scratch registers (all asics).
59 * Returns true if the ring supports writing to scratch regs, false if not.
62 struct radeon_ring *ring) in radeon_ring_supports_scratch_reg() argument
64 switch (ring->idx) { in radeon_ring_supports_scratch_reg()
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Devergreen_dma.c32 * evergreen_dma_fence_ring_emit - emit a fence on the DMA ring
37 * Add a DMA fence packet to the ring to write
39 * an interrupt if needed (evergreen-SI).
44 struct radeon_ring *ring = &rdev->ring[fence->ring]; in evergreen_dma_fence_ring_emit() local
45 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in evergreen_dma_fence_ring_emit()
47 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0)); in evergreen_dma_fence_ring_emit()
48 radeon_ring_write(ring, addr & 0xfffffffc); in evergreen_dma_fence_ring_emit()
49 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in evergreen_dma_fence_ring_emit()
50 radeon_ring_write(ring, fence->seq); in evergreen_dma_fence_ring_emit()
52 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0)); in evergreen_dma_fence_ring_emit()
[all …]
Dcik_sdma.c39 * sDMA - System DMA
43 * and each one supports 1 ring buffer used for gfx
47 * (ring buffer, IBs, etc.), but sDMA has it's own
56 * cik_sdma_get_rptr - get the current read pointer
59 * @ring: radeon ring pointer
64 struct radeon_ring *ring) in cik_sdma_get_rptr() argument
68 if (rdev->wb.enabled) { in cik_sdma_get_rptr()
69 rptr = rdev->wb.wb[ring->rptr_offs/4]; in cik_sdma_get_rptr()
71 if (ring->idx == R600_RING_TYPE_DMA_INDEX) in cik_sdma_get_rptr()
83 * cik_sdma_get_wptr - get the current write pointer
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Dni.c50 spin_lock_irqsave(&rdev->smc_idx_lock, flags); in tn_smc_rreg()
53 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); in tn_smc_rreg()
61 spin_lock_irqsave(&rdev->smc_idx_lock, flags); in tn_smc_wreg()
64 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); in tn_smc_wreg()
458 switch (rdev->family) { in ni_init_golden_registers()
468 if ((rdev->pdev->device == 0x9900) || in ni_init_golden_registers()
469 (rdev->pdev->device == 0x9901) || in ni_init_golden_registers()
470 (rdev->pdev->device == 0x9903) || in ni_init_golden_registers()
471 (rdev->pdev->device == 0x9904) || in ni_init_golden_registers()
472 (rdev->pdev->device == 0x9905) || in ni_init_golden_registers()
[all …]
Dvce_v1_0.c15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
46 uint32_t nonce[4];
47 uint32_t sigval[4];
52 * vce_v1_0_get_rptr - get read pointer
55 * @ring: radeon_ring pointer
60 struct radeon_ring *ring) in vce_v1_0_get_rptr() argument
62 if (ring->idx == TN_RING_TYPE_VCE1_INDEX) in vce_v1_0_get_rptr()
69 * vce_v1_0_get_wptr - get write pointer
72 * @ring: radeon_ring pointer
77 struct radeon_ring *ring) in vce_v1_0_get_wptr() argument
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
Dr600_dma.c34 * to the 3D engine (ring buffer, IBs, etc.), but the
43 * r600_dma_get_rptr - get the current read pointer
46 * @ring: radeon ring pointer
51 struct radeon_ring *ring) in r600_dma_get_rptr() argument
55 if (rdev->wb.enabled) in r600_dma_get_rptr()
56 rptr = rdev->wb.wb[ring->rptr_offs/4]; in r600_dma_get_rptr()
64 * r600_dma_get_wptr - get the current write pointer
67 * @ring: radeon ring pointer
72 struct radeon_ring *ring) in r600_dma_get_wptr() argument
78 * r600_dma_set_wptr - commit the write pointer
[all …]
Dradeon_ring.c37 * Most engines on the GPU are fed via ring buffers. Ring
43 * pointers are equal, the ring is idle. When the host
44 * writes commands to the ring buffer, it increments the
48 static void radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring);
51 * radeon_ring_supports_scratch_reg - check if the ring supports
55 * @ring: radeon_ring structure holding ring information
57 * Check if a specific ring supports writing to scratch registers (all asics).
58 * Returns true if the ring supports writing to scratch regs, false if not.
61 struct radeon_ring *ring) in radeon_ring_supports_scratch_reg() argument
63 switch (ring->idx) { in radeon_ring_supports_scratch_reg()
[all …]
Devergreen_dma.c31 * evergreen_dma_fence_ring_emit - emit a fence on the DMA ring
36 * Add a DMA fence packet to the ring to write
38 * an interrupt if needed (evergreen-SI).
43 struct radeon_ring *ring = &rdev->ring[fence->ring]; in evergreen_dma_fence_ring_emit() local
44 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in evergreen_dma_fence_ring_emit()
46 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0)); in evergreen_dma_fence_ring_emit()
47 radeon_ring_write(ring, addr & 0xfffffffc); in evergreen_dma_fence_ring_emit()
48 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in evergreen_dma_fence_ring_emit()
49 radeon_ring_write(ring, fence->seq); in evergreen_dma_fence_ring_emit()
51 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0)); in evergreen_dma_fence_ring_emit()
[all …]
Dcik_sdma.c38 * sDMA - System DMA
42 * and each one supports 1 ring buffer used for gfx
46 * (ring buffer, IBs, etc.), but sDMA has it's own
55 * cik_sdma_get_rptr - get the current read pointer
58 * @ring: radeon ring pointer
63 struct radeon_ring *ring) in cik_sdma_get_rptr() argument
67 if (rdev->wb.enabled) { in cik_sdma_get_rptr()
68 rptr = rdev->wb.wb[ring->rptr_offs/4]; in cik_sdma_get_rptr()
70 if (ring->idx == R600_RING_TYPE_DMA_INDEX) in cik_sdma_get_rptr()
82 * cik_sdma_get_wptr - get the current write pointer
[all …]
Dni.c52 spin_lock_irqsave(&rdev->smc_idx_lock, flags); in tn_smc_rreg()
55 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); in tn_smc_rreg()
63 spin_lock_irqsave(&rdev->smc_idx_lock, flags); in tn_smc_wreg()
66 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); in tn_smc_wreg()
445 switch (rdev->family) { in ni_init_golden_registers()
455 if ((rdev->pdev->device == 0x9900) || in ni_init_golden_registers()
456 (rdev->pdev->device == 0x9901) || in ni_init_golden_registers()
457 (rdev->pdev->device == 0x9903) || in ni_init_golden_registers()
458 (rdev->pdev->device == 0x9904) || in ni_init_golden_registers()
459 (rdev->pdev->device == 0x9905) || in ni_init_golden_registers()
[all …]
Dvce_v1_0.c15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
47 uint32_t nonce[4];
48 uint32_t sigval[4];
53 * vce_v1_0_get_rptr - get read pointer
56 * @ring: radeon_ring pointer
61 struct radeon_ring *ring) in vce_v1_0_get_rptr() argument
63 if (ring->idx == TN_RING_TYPE_VCE1_INDEX) in vce_v1_0_get_rptr()
70 * vce_v1_0_get_wptr - get write pointer
73 * @ring: radeon_ring pointer
78 struct radeon_ring *ring) in vce_v1_0_get_wptr() argument
[all …]
/kernel/linux/linux-6.6/drivers/soc/ti/
Dk3-ringacc.c1 // SPDX-License-Identifier: GPL-2.0
3 * TI K3 NAVSS Ring Accelerator subsystem driver
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
8 #include <linux/dma-mapping.h>
14 #include <linux/dma/ti-cppi5.h>
15 #include <linux/soc/ti/k3-ringacc.h>
28 * struct k3_ring_rt_regs - The RA realtime Control/Status Registers region
31 * @db: Ring Doorbell Register
33 * @occ: Ring Occupancy Register
34 * @indx: Ring Current Index Register
[all …]
/kernel/linux/linux-5.10/drivers/soc/ti/
Dk3-ringacc.c1 // SPDX-License-Identifier: GPL-2.0
3 * TI K3 NAVSS Ring Accelerator subsystem driver
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
8 #include <linux/dma-mapping.h>
14 #include <linux/soc/ti/k3-ringacc.h>
26 * struct k3_ring_rt_regs - The RA realtime Control/Status Registers region
29 * @db: Ring Doorbell Register
31 * @occ: Ring Occupancy Register
32 * @indx: Ring Current Index Register
33 * @hwocc: Ring Hardware Occupancy Register
[all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/snowridgex/
Duncore-io.json12 …"PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes)…
13 "ScaleUnit": "4Bytes",
27 …"PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) t…
28 "ScaleUnit": "4Bytes",
123 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
129 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
178 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
184 …plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4",
222 "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
227 "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7",
[all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/icelakex/
Duncore-io.json94 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
100 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
149 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4",
155 …plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4",
193 "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
198 "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7",
203 "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7",
208 "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7",
253 "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 4",
258 …fer Occupancy : Part 4 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, O…
[all …]

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