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/kernel/linux/linux-5.10/drivers/gpu/drm/meson/
Dmeson_dw_hdmi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * Bit 15-10: RW Reserved. Default 1 starting from G12A
13 * Bit 9 RW sw_reset_i2c starting from G12A
14 * Bit 8 RW sw_reset_axiarb starting from G12A
15 * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
16 * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
17 * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
18 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
20 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
23 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/meson/
Dmeson_dw_hdmi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * Bit 15-10: RW Reserved. Default 1 starting from G12A
13 * Bit 9 RW sw_reset_i2c starting from G12A
14 * Bit 8 RW sw_reset_axiarb starting from G12A
15 * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
16 * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
17 * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
18 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
20 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
23 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
[all …]
/kernel/linux/linux-6.6/drivers/power/supply/
Dbd99954-charger.h1 /* SPDX-License-Identifier: GPL-2.0-only */
512 [F_SDP_CHG_TRIG_EN] = REG_FIELD(CHGOP_SET1, 9, 9),
551 [F_PROCHOT_IDCHG_DG_SET] = REG_FIELD(PROCHOT_CTRL_SET, 8, 9),
557 [F_IMON_INSEL] = REG_FIELD(PMON_IOUT_CTRL_SET, 9, 9),
564 [F_PMON_DACIN_VAL] = REG_FIELD(PMON_DACIN_VAL, 0, 9),
586 [F_VCC_RREF_EN] = REG_FIELD(VCC_UCD_FCTRL_SET, 9, 9),
599 [F_VCC_RREF_EN_TSTENB] = REG_FIELD(VCC_UCD_FCTRL_EN, 9, 9),
630 [F_VBUS_RREF_EN] = REG_FIELD(VCC_UCD_FCTRL_SET, 9, 9),
644 [F_VBUS_RREF_EN_TSTENB] = REG_FIELD(VBUS_UCD_FCTRL_EN, 9, 9),
659 [F_VACP_AUTO_DISCHG] = REG_FIELD(IC_SET1, 9, 9),
[all …]
/kernel/linux/linux-5.10/drivers/power/supply/
Dbd99954-charger.h1 /* SPDX-License-Identifier: GPL-2.0-only */
512 [F_SDP_CHG_TRIG_EN] = REG_FIELD(CHGOP_SET1, 9, 9),
551 [F_PROCHOT_IDCHG_DG_SET] = REG_FIELD(PROCHOT_CTRL_SET, 8, 9),
557 [F_IMON_INSEL] = REG_FIELD(PMON_IOUT_CTRL_SET, 9, 9),
564 [F_PMON_DACIN_VAL] = REG_FIELD(PMON_DACIN_VAL, 0, 9),
586 [F_VCC_RREF_EN] = REG_FIELD(VCC_UCD_FCTRL_SET, 9, 9),
599 [F_VCC_RREF_EN_TSTENB] = REG_FIELD(VCC_UCD_FCTRL_EN, 9, 9),
630 [F_VBUS_RREF_EN] = REG_FIELD(VCC_UCD_FCTRL_SET, 9, 9),
644 [F_VBUS_RREF_EN_TSTENB] = REG_FIELD(VBUS_UCD_FCTRL_EN, 9, 9),
659 [F_VACP_AUTO_DISCHG] = REG_FIELD(IC_SET1, 9, 9),
[all …]
/kernel/linux/linux-5.10/drivers/tty/serial/
Datmel_serial.h1 /* SPDX-License-Identifier: GPL-2.0+ */
16 #define ATMEL_US_RSTRX BIT(2) /* Reset Receiver */
17 #define ATMEL_US_RSTTX BIT(3) /* Reset Transmitter */
18 #define ATMEL_US_RXEN BIT(4) /* Receiver Enable */
19 #define ATMEL_US_RXDIS BIT(5) /* Receiver Disable */
20 #define ATMEL_US_TXEN BIT(6) /* Transmitter Enable */
21 #define ATMEL_US_TXDIS BIT(7) /* Transmitter Disable */
22 #define ATMEL_US_RSTSTA BIT(8) /* Reset Status Bits */
23 #define ATMEL_US_STTBRK BIT(9) /* Start Break */
24 #define ATMEL_US_STPBRK BIT(10) /* Stop Break */
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/mediatek/
Dmtk_dp_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2019-2022 MediaTek Inc.
11 #define MTK_DP_HPD_DISCONNECT BIT(1)
12 #define MTK_DP_HPD_CONNECT BIT(2)
13 #define MTK_DP_HPD_INTERRUPT BIT(3)
21 #define DA_XTP_GLB_CKDET_EN_FORCE_VAL BIT(15)
22 #define DA_XTP_GLB_CKDET_EN_FORCE_EN BIT(14)
23 #define DA_CKM_INTCKTX_EN_FORCE_VAL BIT(13)
24 #define DA_CKM_INTCKTX_EN_FORCE_EN BIT(12)
25 #define DA_CKM_CKTX0_EN_FORCE_VAL BIT(11)
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/kernel/linux/linux-5.10/include/soc/mscc/
Docelot_ana.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define ANA_ANAGEFIL_B_DOM_EN BIT(22)
12 #define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
13 #define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
14 #define ANA_ANAGEFIL_PID_EN BIT(19)
18 #define ANA_ANAGEFIL_VID_EN BIT(13)
27 #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
31 #define ANA_AUTOAGE_AGE_FAST BIT(21)
35 #define ANA_AUTOAGE_AUTOAGE_LOCKED BIT(0)
37 #define ANA_MACTOPTIONS_REDUCED_TABLE BIT(1)
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Docelot_qsys.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
13 #define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1)
14 #define QSYS_PORT_MODE_DEQUEUE_LATE BIT(0)
16 #define QSYS_STAT_CNT_CFG_TX_GREEN_CNT_MODE BIT(5)
17 #define QSYS_STAT_CNT_CFG_TX_YELLOW_CNT_MODE BIT(4)
18 #define QSYS_STAT_CNT_CFG_DROP_GREEN_CNT_MODE BIT(3)
19 #define QSYS_STAT_CNT_CFG_DROP_YELLOW_CNT_MODE BIT(2)
20 #define QSYS_STAT_CNT_CFG_DROP_COUNT_ONCE BIT(1)
21 #define QSYS_STAT_CNT_CFG_DROP_COUNT_EGRESS BIT(0)
54 #define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT(x) (((x) << 9) & GENMASK(18, 9))
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/kernel/linux/linux-6.6/arch/arm64/include/asm/
Dsysreg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
164 #include "asm/sysreg-defs.h"
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/kernel/linux/linux-5.10/include/net/9p/
D9p.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * include/net/9p/9p.h
5 * 9P protocol definitions.
16 * enum p9_debug_flags - bits for mount time debug parameter
18 * @P9_DEBUG_9P: 9P protocol tracing
27 * @P9_DEBUG_FSC: FS-cache tracing
43 P9_DEBUG_FID = (1<<9),
62 * enum p9_msg_t - 9P message types
64 * @P9_RLERROR: response for any failed request for 9P2000.L
71 * @P9_TLCREATE: prepare a handle for I/O on an new file for 9P2000.L
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_interrupts.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
30 * WB interrupt status bit definitions
32 #define DPU_INTR_WB_0_DONE BIT(0)
33 #define DPU_INTR_WB_1_DONE BIT(1)
34 #define DPU_INTR_WB_2_DONE BIT(4)
37 * WDOG timer interrupt status bit definitions
39 #define DPU_INTR_WD_TIMER_0_DONE BIT(2)
40 #define DPU_INTR_WD_TIMER_1_DONE BIT(3)
41 #define DPU_INTR_WD_TIMER_2_DONE BIT(5)
[all …]
/kernel/linux/linux-6.6/include/net/9p/
D9p.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * 9P protocol definitions.
14 * enum p9_debug_flags - bits for mount time debug parameter
16 * @P9_DEBUG_9P: 9P protocol tracing
25 * @P9_DEBUG_FSC: FS-cache tracing
41 P9_DEBUG_FID = (1<<9),
62 * enum p9_msg_t - 9P message types
64 * @P9_RLERROR: response for any failed request for 9P2000.L
71 * @P9_TLCREATE: prepare a handle for I/O on an new file for 9P2000.L
72 * @P9_RLCREATE: response with file access information for 9P2000.L
[all …]
/kernel/linux/linux-6.6/include/soc/mscc/
Docelot_ana.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define ANA_ANAGEFIL_B_DOM_EN BIT(22)
12 #define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
13 #define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
14 #define ANA_ANAGEFIL_PID_EN BIT(19)
18 #define ANA_ANAGEFIL_VID_EN BIT(13)
27 #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
31 #define ANA_AUTOAGE_AGE_FAST BIT(21)
35 #define ANA_AUTOAGE_AUTOAGE_LOCKED BIT(0)
37 #define ANA_MACTOPTIONS_REDUCED_TABLE BIT(1)
[all …]
Docelot_qsys.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
13 #define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1)
14 #define QSYS_PORT_MODE_DEQUEUE_LATE BIT(0)
16 #define QSYS_STAT_CNT_CFG_TX_GREEN_CNT_MODE BIT(5)
17 #define QSYS_STAT_CNT_CFG_TX_YELLOW_CNT_MODE BIT(4)
18 #define QSYS_STAT_CNT_CFG_DROP_GREEN_CNT_MODE BIT(3)
19 #define QSYS_STAT_CNT_CFG_DROP_YELLOW_CNT_MODE BIT(2)
20 #define QSYS_STAT_CNT_CFG_DROP_COUNT_ONCE BIT(1)
21 #define QSYS_STAT_CNT_CFG_DROP_COUNT_EGRESS BIT(0)
54 #define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT(x) (((x) << 9) & GENMASK(18, 9))
[all …]
/kernel/linux/linux-6.6/tools/arch/arm64/include/asm/
Dsysreg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
19 * [20-19] : Op0
20 * [18-16] : Op1
21 * [15-12] : CRn
22 * [11-8] : CRm
23 * [7-5] : Op2
80 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
133 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
236 #define SYS_PAR_EL1_F BIT(0)
241 #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7)
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/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtw88/
Drtw8821c.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
21 ether_addr_copy(efuse->addr, map->e.mac_addr); in rtw8821ce_efuse_parsing()
26 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_read_efuse()
32 efuse->rfe_option = map->rfe_option; in rtw8821c_read_efuse()
33 efuse->rf_board_option = map->rf_board_option; in rtw8821c_read_efuse()
34 efuse->crystal_cap = map->xtal_k; in rtw8821c_read_efuse()
35 efuse->pa_type_2g = map->pa_type; in rtw8821c_read_efuse()
36 efuse->pa_type_5g = map->pa_type; in rtw8821c_read_efuse()
37 efuse->lna_type_2g = map->lna_type_2g[0]; in rtw8821c_read_efuse()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/vc4/
Dvc4_packet.h78 /* Not an actual hardware packet -- this is what we use to put
115 #define VC4_PACKET_CLIP_WINDOW_SIZE 9
117 #define VC4_PACKET_Z_CLIPPING_SIZE 9
118 #define VC4_PACKET_CLIPPER_XY_SCALING_SIZE 9
119 #define VC4_PACKET_CLIPPER_Z_SCALING_SIZE 9
124 #define VC4_PACKET_GEM_HANDLES_SIZE 9
145 #define VC4_LOADSTORE_FULL_RES_EOF BIT(3)
146 #define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL BIT(2)
147 #define VC4_LOADSTORE_FULL_RES_DISABLE_ZS BIT(1)
148 #define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR BIT(0)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/vc4/
Dvc4_packet.h78 /* Not an actual hardware packet -- this is what we use to put
115 #define VC4_PACKET_CLIP_WINDOW_SIZE 9
117 #define VC4_PACKET_Z_CLIPPING_SIZE 9
118 #define VC4_PACKET_CLIPPER_XY_SCALING_SIZE 9
119 #define VC4_PACKET_CLIPPER_Z_SCALING_SIZE 9
124 #define VC4_PACKET_GEM_HANDLES_SIZE 9
145 #define VC4_LOADSTORE_FULL_RES_EOF BIT(3)
146 #define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL BIT(2)
147 #define VC4_LOADSTORE_FULL_RES_DISABLE_ZS BIT(1)
148 #define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR BIT(0)
[all …]
/kernel/linux/linux-6.6/arch/csky/abiv1/inc/abi/
Dpgtable-bits.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 /* We borrow bit 9 to store the exclusive marker in swap PTEs. */
14 #define _PAGE_SWP_EXCLUSIVE (1<<9)
21 #define _PAGE_CACHE (3<<9)
22 #define _PAGE_UNCACHE (2<<9)
24 #define _CACHE_MASK (7<<9)
36 * bit 0: _PAGE_PRESENT (zero)
37 * bit 1: _PAGE_READ (zero)
38 * bit 2 - 5: swap type[0 - 3]
39 * bit 6: _PAGE_GLOBAL (zero)
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7915/
Dmac.h1 /* SPDX-License-Identifier: ISC */
14 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
15 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
29 #define MT_RXD1_NORMAL_WLAN_IDX GENMASK(9, 0)
30 #define MT_RXD1_NORMAL_GROUP_1 BIT(11)
31 #define MT_RXD1_NORMAL_GROUP_2 BIT(12)
32 #define MT_RXD1_NORMAL_GROUP_3 BIT(13)
33 #define MT_RXD1_NORMAL_GROUP_4 BIT(14)
34 #define MT_RXD1_NORMAL_GROUP_5 BIT(15)
37 #define MT_RXD1_NORMAL_CM BIT(23)
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/kmb/
Dkmb_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2018-2020 Intel Corporation
14 #define LCD_CTRL_INTERLACED BIT(0)
15 #define LCD_CTRL_ENABLE BIT(1)
16 #define LCD_CTRL_VL1_ENABLE BIT(2)
17 #define LCD_CTRL_VL2_ENABLE BIT(3)
18 #define LCD_CTRL_GL1_ENABLE BIT(4)
19 #define LCD_CTRL_GL2_ENABLE BIT(5)
21 #define LCD_CTRL_ALPHA_BLEND_VL2 BIT(6)
25 #define LCD_CTRL_ALPHA_TOP_VL2 BIT(8)
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtw89/
Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
9 #define B_AX_AUTOLOAD_SUS BIT(5)
13 #define B_AX_PWC_EV2EF_B15 BIT(15)
14 #define B_AX_PWC_EV2EF_B14 BIT(14)
15 #define B_AX_ISO_EB2CORE BIT(8)
18 #define B_AX_FEN_BB_GLB_RSTN BIT(1)
19 #define B_AX_FEN_BBRSTB BIT(0)
22 #define B_AX_SOP_ASWRM BIT(31)
23 #define B_AX_SOP_PWMM_DSWR BIT(29)
[all …]
/kernel/linux/linux-5.10/drivers/phy/rockchip/
Dphy-rockchip-typec.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chris Zhong <zyw@rock-chips.com>
5 * Kever Yang <kever.yang@rock-chips.com>
7 * The ROCKCHIP Type-C PHY has two PLL clocks. The first PLL clock
8 * is used for USB3, the second PLL clock is used for DP. This Type-C PHY has
34 * This Type-C PHY driver supports normal and flip orientation. The orientation
40 #include <linux/clk-provider.h>
103 #define CMN_TXPXCAL_START BIT(15)
104 #define CMN_TXPXCAL_DONE BIT(14)
105 #define CMN_TXPXCAL_NO_RESPONSE BIT(13)
[all …]
/kernel/linux/linux-6.6/drivers/phy/rockchip/
Dphy-rockchip-typec.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chris Zhong <zyw@rock-chips.com>
5 * Kever Yang <kever.yang@rock-chips.com>
7 * The ROCKCHIP Type-C PHY has two PLL clocks. The first PLL clock
8 * is used for USB3, the second PLL clock is used for DP. This Type-C PHY has
34 * This Type-C PHY driver supports normal and flip orientation. The orientation
40 #include <linux/clk-provider.h>
103 #define CMN_TXPXCAL_START BIT(15)
104 #define CMN_TXPXCAL_DONE BIT(14)
105 #define CMN_TXPXCAL_NO_RESPONSE BIT(13)
[all …]
/kernel/linux/linux-6.6/include/linux/soc/mediatek/
Dinfracfg.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define MT8195_TOP_AXI_PROT_EN_VDOSYS0 BIT(6)
34 #define MT8195_TOP_AXI_PROT_EN_VPPSYS0 BIT(10)
35 #define MT8195_TOP_AXI_PROT_EN_MFG1 BIT(11)
37 #define MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND BIT(23)
39 #define MT8195_TOP_AXI_PROT_EN_1_CAM BIT(22)
40 #define MT8195_TOP_AXI_PROT_EN_2_CAM BIT(0)
42 #define MT8195_TOP_AXI_PROT_EN_2_MFG1 BIT(7)
43 #define MT8195_TOP_AXI_PROT_EN_2_AUDIO (BIT(9) | BIT(11))
44 #define MT8195_TOP_AXI_PROT_EN_2_ADSP (BIT(12) | GENMASK(16, 14))
[all …]

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