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/kernel/linux/linux-5.10/drivers/clocksource/
Dtimer-sun5i.c6 * Maxime Ripard <maxime.ripard@free-electrons.com>
13 #include <linux/clk.h>
43 struct clk *clk; member
68 * When we disable a timer, we need to wait at least for 2 cycles of
75 u32 old = readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1)); in sun5i_clkevt_sync()
77 while ((old - readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS) in sun5i_clkevt_sync()
83 u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_stop()
84 writel(val & ~TIMER_CTL_ENABLE, ce->timer.base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_stop()
91 writel(delay, ce->timer.base + TIMER_INTVAL_LO_REG(timer)); in sun5i_clkevt_time_setup()
96 u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_start()
[all …]
Dingenic-ost.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk.h>
11 #include <linux/mfd/ingenic-tcu.h>
25 * The TCU_REG_OST_CNT{L,R} from <linux/mfd/ingenic-tcu.h> are only for the
37 struct clk *clk; member
39 struct clocksource cs; member
46 /* Read using __iomem pointer instead of regmap to avoid locking */ in ingenic_ost_read_cntl()
47 return readl(ingenic_ost->regs + OST_REG_CNTL); in ingenic_ost_read_cntl()
52 /* Read using __iomem pointer instead of regmap to avoid locking */ in ingenic_ost_read_cnth()
53 return readl(ingenic_ost->regs + OST_REG_CNTH); in ingenic_ost_read_cnth()
[all …]
Dh8300_tpu.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk.h>
26 struct clocksource cs; member
37 tcnt = ioread16be(p->mapbase1 + TCNT) << 16; in read_tcnt32()
38 tcnt |= ioread16be(p->mapbase2 + TCNT); in read_tcnt32()
47 o1 = ioread8(p->mapbase1 + TSR) & TCFV; in tpu_get_counter()
55 o1 = ioread8(p->mapbase1 + TSR) & TCFV; in tpu_get_counter()
63 static inline struct tpu_priv *cs_to_priv(struct clocksource *cs) in cs_to_priv() argument
65 return container_of(cs, struct tpu_priv, cs); in cs_to_priv()
68 static u64 tpu_clocksource_read(struct clocksource *cs) in tpu_clocksource_read() argument
[all …]
Dem_sti.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Emma Mobile Timer Support - STI
14 #include <linux/clk.h>
27 struct clk *clk; member
33 struct clocksource cs; member
55 return ioread32(p->base + offs); in em_sti_read()
61 iowrite32(value, p->base + offs); in em_sti_write()
69 ret = clk_enable(p->clk); in em_sti_enable()
71 dev_err(&p->pdev->dev, "cannot enable clock\n"); in em_sti_enable()
95 clk_disable(p->clk); in em_sti_disable()
[all …]
Dh8300_timer16.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk.h>
27 struct clocksource cs; member
42 o1 = ioread8(p->mapcommon + TISRC) & p->ovf; in timer16_get_counter()
47 v1 = ioread16be(p->mapbase + TCNT); in timer16_get_counter()
48 v2 = ioread16be(p->mapbase + TCNT); in timer16_get_counter()
49 v3 = ioread16be(p->mapbase + TCNT); in timer16_get_counter()
50 o1 = ioread8(p->mapcommon + TISRC) & p->ovf; in timer16_get_counter()
65 bclr(p->ovf, p->mapcommon + TISRC); in timer16_interrupt()
66 p->total_cycles += 0x10000; in timer16_interrupt()
[all …]
Dsh_tmu.c1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Timer Support - TMU
8 #include <linux/clk.h>
47 struct clocksource cs; member
56 struct clk *clk; member
70 #define TSTR -1 /* shared register */
89 switch (ch->tmu->model) { in sh_tmu_read()
91 return ioread8(ch->tmu->mapbase + 2); in sh_tmu_read()
93 return ioread8(ch->tmu->mapbase + 4); in sh_tmu_read()
100 return ioread16(ch->base + offs); in sh_tmu_read()
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Dingenic-timer.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk.h>
13 #include <linux/mfd/ingenic-tcu.h>
24 #include <dt-bindings/clock/ingenic,tcu.h>
36 struct clk *clk; member
43 struct clk *cs_clk;
45 struct clocksource cs; member
57 regmap_read(tcu->map, TCU_REG_TCNTc(tcu->cs_channel), &count); in ingenic_tcu_timer_read()
62 static u64 notrace ingenic_tcu_timer_cs_read(struct clocksource *cs) in ingenic_tcu_timer_cs_read() argument
70 return container_of(timer, struct ingenic_tcu, timers[timer->cpu]); in to_ingenic_tcu()
[all …]
/kernel/linux/linux-6.6/drivers/clocksource/
Dingenic-ost.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk.h>
11 #include <linux/mfd/ingenic-tcu.h>
25 * The TCU_REG_OST_CNT{L,R} from <linux/mfd/ingenic-tcu.h> are only for the
37 struct clk *clk; member
39 struct clocksource cs; member
46 /* Read using __iomem pointer instead of regmap to avoid locking */ in ingenic_ost_read_cntl()
47 return readl(ingenic_ost->regs + OST_REG_CNTL); in ingenic_ost_read_cntl()
52 /* Read using __iomem pointer instead of regmap to avoid locking */ in ingenic_ost_read_cnth()
53 return readl(ingenic_ost->regs + OST_REG_CNTH); in ingenic_ost_read_cnth()
[all …]
Dem_sti.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Emma Mobile Timer Support - STI
14 #include <linux/clk.h>
27 struct clk *clk; member
33 struct clocksource cs; member
55 return ioread32(p->base + offs); in em_sti_read()
61 iowrite32(value, p->base + offs); in em_sti_write()
69 ret = clk_enable(p->clk); in em_sti_enable()
71 dev_err(&p->pdev->dev, "cannot enable clock\n"); in em_sti_enable()
95 clk_disable(p->clk); in em_sti_disable()
[all …]
Dtimer-sun5i.c1 // SPDX-License-Identifier: GPL-2.0
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
10 #include <linux/clk.h>
38 struct clk *clk; member
53 * When we disable a timer, we need to wait at least for 2 cycles of
60 u32 old = readl(ce->base + TIMER_CNTVAL_LO_REG(1)); in sun5i_clkevt_sync()
62 while ((old - readl(ce->base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS) in sun5i_clkevt_sync()
68 u32 val = readl(ce->base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_stop()
69 writel(val & ~TIMER_CTL_ENABLE, ce->base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_stop()
76 writel(delay, ce->base + TIMER_INTVAL_LO_REG(timer)); in sun5i_clkevt_time_setup()
[all …]
Dsh_tmu.c1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Timer Support - TMU
8 #include <linux/clk.h>
47 struct clocksource cs; member
56 struct clk *clk; member
70 #define TSTR -1 /* shared register */
89 switch (ch->tmu->model) { in sh_tmu_read()
91 return ioread8(ch->tmu->mapbase + 2); in sh_tmu_read()
93 return ioread8(ch->tmu->mapbase + 4); in sh_tmu_read()
100 return ioread16(ch->base + offs); in sh_tmu_read()
[all …]
Dingenic-timer.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk.h>
14 #include <linux/mfd/ingenic-tcu.h>
23 #include <dt-bindings/clock/ingenic,tcu.h>
35 struct clk *clk; member
42 struct clk *cs_clk;
44 struct clocksource cs; member
56 regmap_read(tcu->map, TCU_REG_TCNTc(tcu->cs_channel), &count); in ingenic_tcu_timer_read()
61 static u64 notrace ingenic_tcu_timer_cs_read(struct clocksource *cs) in ingenic_tcu_timer_cs_read() argument
69 return container_of(timer, struct ingenic_tcu, timers[timer->cpu]); in to_ingenic_tcu()
[all …]
/kernel/linux/linux-5.10/drivers/memory/
Dti-aemif.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010 - 2013 Texas Instruments Incorporated. http://www.ti.com/
8 * Murali Karicheri <m-karicheri2@ti.com>
12 #include <linux/clk.h>
20 #include <linux/platform_data/ti-aemif.h>
84 * struct aemif_cs_data: structure to hold cs parameters
85 * @cs: chip-select number
98 u8 cs; member
112 * struct aemif_device: structure to hold device data
114 * @clk: source clock
[all …]
Dpl172.c1 // SPDX-License-Identifier: GPL-2.0
9 * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
13 #include <linux/clk.h>
53 struct clk *clk; member
65 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; in pl172_timing_prop()
69 dev_err(&adev->dev, "%s timing too tight\n", name); in pl172_timing_prop()
70 return -EINVAL; in pl172_timing_prop()
73 writel(cycles, pl172->base + reg_offset); in pl172_timing_prop()
76 dev_dbg(&adev->dev, "%s: %u cycle(s)\n", name, start + in pl172_timing_prop()
77 readl(pl172->base + reg_offset)); in pl172_timing_prop()
[all …]
/kernel/linux/linux-6.6/drivers/memory/
Dti-aemif.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010 - 2013 Texas Instruments Incorporated. http://www.ti.com/
8 * Murali Karicheri <m-karicheri2@ti.com>
12 #include <linux/clk.h>
20 #include <linux/platform_data/ti-aemif.h>
84 * struct aemif_cs_data: structure to hold cs parameters
85 * @cs: chip-select number
98 u8 cs; member
112 * struct aemif_device: structure to hold device data
114 * @clk: source clock
[all …]
Dpl172.c1 // SPDX-License-Identifier: GPL-2.0
9 * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
13 #include <linux/clk.h>
53 struct clk *clk; member
65 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; in pl172_timing_prop()
69 dev_err(&adev->dev, "%s timing too tight\n", name); in pl172_timing_prop()
70 return -EINVAL; in pl172_timing_prop()
73 writel(cycles, pl172->base + reg_offset); in pl172_timing_prop()
76 dev_dbg(&adev->dev, "%s: %u cycle(s)\n", name, start + in pl172_timing_prop()
77 readl(pl172->base + reg_offset)); in pl172_timing_prop()
[all …]
/kernel/linux/linux-6.6/drivers/spi/
Dspi-dw-mmio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Memory-mapped interface driver for DW SPI Core
8 #include <linux/clk.h>
24 #include "spi-dw.h"
30 struct clk *clk; member
31 struct clk *pclk;
57 * Elba SoC does not use ssi, pin override is used for cs 0,1 and
58 * gpios for cs 2,3 as defined in the device tree.
60 * cs: | 1 0
61 * bit: |---3-------2-------1-------0
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/kernel/linux/linux-5.10/drivers/mfd/
Datmel-smc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
11 #include <linux/mfd/syscon/atmel-smc.h>
15 * atmel_smc_cs_conf_init - initialize a SMC CS conf
16 * @conf: the SMC CS conf to initialize
18 * Set all fields to 0 so that one can start defining a new config.
27 * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
29 * @ncycles: number of MCK clk cycles
32 * @msbfactor: factor applied to the MSB
33 * @encodedval: param used to store the encoding result
[all …]
/kernel/linux/linux-6.6/drivers/mfd/
Datmel-smc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
11 #include <linux/mfd/syscon/atmel-smc.h>
15 * atmel_smc_cs_conf_init - initialize a SMC CS conf
16 * @conf: the SMC CS conf to initialize
18 * Set all fields to 0 so that one can start defining a new config.
27 * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
29 * @ncycles: number of MCK clk cycles
32 * @msbfactor: factor applied to the MSB
33 * @encodedval: param used to store the encoding result
[all …]
/kernel/linux/linux-5.10/drivers/spi/
Dspi-s3c24xx.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2009 Simtec Electronics
13 #include <linux/clk.h>
22 #include <linux/spi/s3c24xx-fiq.h>
27 #include "spi-s3c24xx-regs.h"
30 * struct s3c24xx_spi_devstate - per device data
33 * @spcon: Value to write to the SPCON register.
34 * @sppre: Value to write to the SPPRE register.
51 /* bitbang has to be first */
66 int cs, int pol);
[all …]
Dspi-txx9.c5 * Copyright (C) 2000-2001 Toshiba Corporation
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
14 * Convert to generic SPI framework - Atsushi Nemoto (anemo@mba.ocn.ne.jp)
26 #include <linux/clk.h>
82 struct clk *clk; member
89 return __raw_readl(c->membase + reg); in txx9spi_rd()
93 __raw_writel(val, c->membase + reg); in txx9spi_wr()
105 if (c->last_chipselect) in txx9spi_cs_func()
106 gpiod_set_value(c->last_chipselect, in txx9spi_cs_func()
[all …]
Dspi-dw-mmio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Memory-mapped interface driver for DW SPI Core
8 #include <linux/clk.h>
24 #include "spi-dw.h"
30 struct clk *clk; member
31 struct clk *pclk;
57 * The Designware SPI controller (referred to as master in the documentation)
59 * selects then needs to be either driven as GPIOs or, for the first 4 using the
65 struct dw_spi *dws = spi_master_get_devdata(spi->master); in dw_spi_mscc_set_cs()
67 struct dw_spi_mscc *dwsmscc = dwsmmio->priv; in dw_spi_mscc_set_cs()
[all …]
/kernel/linux/linux-5.10/include/linux/platform_data/
Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
39 /* ADV signal timings corresponding to GPMC_CONFIG3 */
47 /* WE signals timings corresponding to GPMC_CONFIG4 */
51 /* OE signals timings corresponding to GPMC_CONFIG4 */
57 /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
59 u32 access; /* Start-cycle to first data valid delay */
78 u32 t_ceasu; /* address setup to CS valid */
79 u32 t_avdasu; /* address setup to ADV valid */
[all …]
/kernel/linux/linux-6.6/include/linux/platform_data/
Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
39 /* ADV signal timings corresponding to GPMC_CONFIG3 */
47 /* WE signals timings corresponding to GPMC_CONFIG4 */
51 /* OE signals timings corresponding to GPMC_CONFIG4 */
57 /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
59 u32 access; /* Start-cycle to first data valid delay */
78 u32 t_ceasu; /* address setup to CS valid */
79 u32 t_avdasu; /* address setup to ADV valid */
[all …]
/kernel/linux/linux-5.10/drivers/bus/
Dimx-weim.c11 #include <linux/clk.h>
15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
62 struct cs_timing cs[MAX_CS_COUNT]; member
67 { .compatible = "fsl,imx1-weim", .data = &imx1_weim_devtype, },
69 { .compatible = "fsl,imx27-weim", .data = &imx27_weim_devtype, },
71 { .compatible = "fsl,imx50-weim", .data = &imx50_weim_devtype, },
72 { .compatible = "fsl,imx6q-weim", .data = &imx50_weim_devtype, },
74 { .compatible = "fsl,imx51-weim", .data = &imx51_weim_devtype, },
81 struct device_node *np = pdev->dev.of_node; in imx_weim_gpr_setup()
93 int cs = 0; in imx_weim_gpr_setup() local
[all …]

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