| /kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/ |
| D | 0026_linux_drivers_mailbox.patch | 96 const struct imx_mu_dcfg *dcfg;
160 + status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
161 + can_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4);
170 + imx_mu_write(priv, val, priv->dcfg->xTR + (idx % 4) * 4);
184 + status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
185 + can_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4);
194 + *val = imx_mu_read(priv, priv->dcfg->xRR + (idx % 4) * 4);
206 - val = imx_mu_read(priv, priv->dcfg->xCR);
207 + val = imx_mu_read(priv, priv->dcfg->xCR[type]);
210 - imx_mu_write(priv, val, priv->dcfg->xCR);
[all …]
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| /kernel/linux/linux-6.6/drivers/mailbox/ |
| D | imx-mailbox.c | 89 const struct imx_mu_dcfg *dcfg; member
159 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]); in imx_mu_tx_waiting_write()
160 can_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4); in imx_mu_tx_waiting_write()
169 imx_mu_write(priv, val, priv->dcfg->xTR + (idx % 4) * 4); in imx_mu_tx_waiting_write()
183 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]); in imx_mu_rx_waiting_read()
184 can_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4); in imx_mu_rx_waiting_read()
193 *val = imx_mu_read(priv, priv->dcfg->xRR + (idx % 4) * 4); in imx_mu_rx_waiting_read()
205 val = imx_mu_read(priv, priv->dcfg->xCR[type]); in imx_mu_xcr_rmw()
208 imx_mu_write(priv, val, priv->dcfg->xCR[type]); in imx_mu_xcr_rmw()
222 imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4); in imx_mu_generic_tx()
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/fsl/ |
| D | fsl,layerscape-dcfg.yaml | 4 $id: http://devicetree.org/schemas/soc/fsl/fsl,layerscape-dcfg.yaml#
14 DCFG is the device configuration unit, that provides general purpose
24 - fsl,ls1012a-dcfg
25 - fsl,ls1021a-dcfg
26 - fsl,ls1043a-dcfg
27 - fsl,ls1046a-dcfg
28 - fsl,ls1088a-dcfg
29 - fsl,ls2080a-dcfg
30 - fsl,lx2160a-dcfg
35 - fsl,ls1028a-dcfg
[all …]
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| /kernel/linux/linux-6.6/drivers/video/fbdev/geode/ |
| D | video_cs5530.c | 98 u32 dcfg; in cs5530_configure_display() local
100 dcfg = readl(par->vid_regs + CS5530_DISPLAY_CONFIG); in cs5530_configure_display()
103 dcfg &= ~(CS5530_DCFG_CRT_SYNC_SKW_MASK | CS5530_DCFG_PWR_SEQ_DLY_MASK in cs5530_configure_display()
110 dcfg |= (CS5530_DCFG_CRT_SYNC_SKW_INIT | CS5530_DCFG_PWR_SEQ_DLY_INIT in cs5530_configure_display()
115 dcfg |= CS5530_DCFG_DAC_PWR_EN; in cs5530_configure_display()
116 dcfg |= CS5530_DCFG_HSYNC_EN | CS5530_DCFG_VSYNC_EN; in cs5530_configure_display()
120 dcfg |= CS5530_DCFG_FP_PWR_EN; in cs5530_configure_display()
121 dcfg |= CS5530_DCFG_FP_DATA_EN; in cs5530_configure_display()
126 dcfg |= CS5530_DCFG_CRT_HSYNC_POL; in cs5530_configure_display()
128 dcfg |= CS5530_DCFG_CRT_VSYNC_POL; in cs5530_configure_display()
[all …]
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| D | display_gx.c | 60 u32 gcfg, dcfg; in gx_set_mode() local
68 dcfg = read_dc(par, DC_DISPLAY_CFG); in gx_set_mode()
71 dcfg &= ~DC_DISPLAY_CFG_TGEN; in gx_set_mode()
72 write_dc(par, DC_DISPLAY_CFG, dcfg); in gx_set_mode()
91 dcfg = 0; in gx_set_mode()
108 dcfg |= DC_DISPLAY_CFG_GDEN | DC_DISPLAY_CFG_VDEN | in gx_set_mode()
114 dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP; in gx_set_mode()
117 dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP; in gx_set_mode()
120 dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP; in gx_set_mode()
121 dcfg |= DC_DISPLAY_CFG_PALB; in gx_set_mode()
[all …]
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| D | video_gx.c | 235 u32 dcfg, misc; in gx_configure_display() local
238 dcfg = read_vp(par, VP_DCFG); in gx_configure_display()
241 dcfg &= ~(VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN); in gx_configure_display()
242 write_vp(par, VP_DCFG, dcfg); in gx_configure_display()
245 dcfg &= ~(VP_DCFG_CRT_SYNC_SKW in gx_configure_display()
250 dcfg |= VP_DCFG_CRT_SYNC_SKW_DEFAULT; in gx_configure_display()
253 dcfg |= VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN; in gx_configure_display()
270 dcfg |= VP_DCFG_CRT_HSYNC_POL; in gx_configure_display()
272 dcfg |= VP_DCFG_CRT_VSYNC_POL; in gx_configure_display()
282 dcfg |= VP_DCFG_CRT_EN | VP_DCFG_DAC_BL_EN; in gx_configure_display()
[all …]
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| D | lxfb_ops.c | 348 unsigned int gcfg, dcfg; in lx_set_mode() local
437 dcfg = DC_DISPLAY_CFG_VDEN; /* Enable video data */ in lx_set_mode()
438 dcfg |= DC_DISPLAY_CFG_GDEN; /* Enable graphics */ in lx_set_mode()
439 dcfg |= DC_DISPLAY_CFG_TGEN; /* Turn on the timing generator */ in lx_set_mode()
440 dcfg |= DC_DISPLAY_CFG_TRUP; /* Update timings immediately */ in lx_set_mode()
441 dcfg |= DC_DISPLAY_CFG_PALB; /* Palette bypass in > 8 bpp modes */ in lx_set_mode()
442 dcfg |= DC_DISPLAY_CFG_VISL; in lx_set_mode()
443 dcfg |= DC_DISPLAY_CFG_DCEN; /* Always center the display */ in lx_set_mode()
449 dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP; in lx_set_mode()
453 dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP; in lx_set_mode()
[all …]
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| /kernel/linux/linux-5.10/drivers/video/fbdev/geode/ |
| D | video_cs5530.c | 98 u32 dcfg; in cs5530_configure_display() local
100 dcfg = readl(par->vid_regs + CS5530_DISPLAY_CONFIG); in cs5530_configure_display()
103 dcfg &= ~(CS5530_DCFG_CRT_SYNC_SKW_MASK | CS5530_DCFG_PWR_SEQ_DLY_MASK in cs5530_configure_display()
110 dcfg |= (CS5530_DCFG_CRT_SYNC_SKW_INIT | CS5530_DCFG_PWR_SEQ_DLY_INIT in cs5530_configure_display()
115 dcfg |= CS5530_DCFG_DAC_PWR_EN; in cs5530_configure_display()
116 dcfg |= CS5530_DCFG_HSYNC_EN | CS5530_DCFG_VSYNC_EN; in cs5530_configure_display()
120 dcfg |= CS5530_DCFG_FP_PWR_EN; in cs5530_configure_display()
121 dcfg |= CS5530_DCFG_FP_DATA_EN; in cs5530_configure_display()
126 dcfg |= CS5530_DCFG_CRT_HSYNC_POL; in cs5530_configure_display()
128 dcfg |= CS5530_DCFG_CRT_VSYNC_POL; in cs5530_configure_display()
[all …]
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| D | display_gx.c | 60 u32 gcfg, dcfg; in gx_set_mode() local
68 dcfg = read_dc(par, DC_DISPLAY_CFG); in gx_set_mode()
71 dcfg &= ~DC_DISPLAY_CFG_TGEN; in gx_set_mode()
72 write_dc(par, DC_DISPLAY_CFG, dcfg); in gx_set_mode()
91 dcfg = 0; in gx_set_mode()
108 dcfg |= DC_DISPLAY_CFG_GDEN | DC_DISPLAY_CFG_VDEN | in gx_set_mode()
114 dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP; in gx_set_mode()
117 dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP; in gx_set_mode()
120 dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP; in gx_set_mode()
121 dcfg |= DC_DISPLAY_CFG_PALB; in gx_set_mode()
[all …]
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| D | video_gx.c | 235 u32 dcfg, misc; in gx_configure_display() local
238 dcfg = read_vp(par, VP_DCFG); in gx_configure_display()
241 dcfg &= ~(VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN); in gx_configure_display()
242 write_vp(par, VP_DCFG, dcfg); in gx_configure_display()
245 dcfg &= ~(VP_DCFG_CRT_SYNC_SKW in gx_configure_display()
250 dcfg |= VP_DCFG_CRT_SYNC_SKW_DEFAULT; in gx_configure_display()
253 dcfg |= VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN; in gx_configure_display()
270 dcfg |= VP_DCFG_CRT_HSYNC_POL; in gx_configure_display()
272 dcfg |= VP_DCFG_CRT_VSYNC_POL; in gx_configure_display()
282 dcfg |= VP_DCFG_CRT_EN | VP_DCFG_DAC_BL_EN; in gx_configure_display()
[all …]
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| D | lxfb_ops.c | 348 unsigned int gcfg, dcfg; in lx_set_mode() local
437 dcfg = DC_DISPLAY_CFG_VDEN; /* Enable video data */ in lx_set_mode()
438 dcfg |= DC_DISPLAY_CFG_GDEN; /* Enable graphics */ in lx_set_mode()
439 dcfg |= DC_DISPLAY_CFG_TGEN; /* Turn on the timing generator */ in lx_set_mode()
440 dcfg |= DC_DISPLAY_CFG_TRUP; /* Update timings immediately */ in lx_set_mode()
441 dcfg |= DC_DISPLAY_CFG_PALB; /* Palette bypass in > 8 bpp modes */ in lx_set_mode()
442 dcfg |= DC_DISPLAY_CFG_VISL; in lx_set_mode()
443 dcfg |= DC_DISPLAY_CFG_DCEN; /* Always center the display */ in lx_set_mode()
449 dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP; in lx_set_mode()
453 dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP; in lx_set_mode()
[all …]
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| /kernel/linux/linux-5.10/drivers/nvmem/ |
| D | snvs_lpgpr.c | 35 const struct snvs_lpgpr_cfg *dcfg; member
56 const struct snvs_lpgpr_cfg *dcfg = priv->dcfg; in snvs_lpgpr_write() local
60 ret = regmap_read(priv->regmap, dcfg->offset_hplr, &lock_reg); in snvs_lpgpr_write()
67 ret = regmap_read(priv->regmap, dcfg->offset_lplr, &lock_reg); in snvs_lpgpr_write()
74 return regmap_bulk_write(priv->regmap, dcfg->offset + offset, val, in snvs_lpgpr_write()
82 const struct snvs_lpgpr_cfg *dcfg = priv->dcfg; in snvs_lpgpr_read() local
84 return regmap_bulk_read(priv->regmap, dcfg->offset + offset, in snvs_lpgpr_read()
96 const struct snvs_lpgpr_cfg *dcfg; in snvs_lpgpr_probe() local
105 dcfg = of_device_get_match_data(dev); in snvs_lpgpr_probe()
106 if (!dcfg) in snvs_lpgpr_probe()
[all …]
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| /kernel/linux/linux-6.6/drivers/nvmem/ |
| D | snvs_lpgpr.c | 36 const struct snvs_lpgpr_cfg *dcfg; member
57 const struct snvs_lpgpr_cfg *dcfg = priv->dcfg; in snvs_lpgpr_write() local
61 ret = regmap_read(priv->regmap, dcfg->offset_hplr, &lock_reg); in snvs_lpgpr_write()
68 ret = regmap_read(priv->regmap, dcfg->offset_lplr, &lock_reg); in snvs_lpgpr_write()
75 return regmap_bulk_write(priv->regmap, dcfg->offset + offset, val, in snvs_lpgpr_write()
83 const struct snvs_lpgpr_cfg *dcfg = priv->dcfg; in snvs_lpgpr_read() local
85 return regmap_bulk_read(priv->regmap, dcfg->offset + offset, in snvs_lpgpr_read()
97 const struct snvs_lpgpr_cfg *dcfg; in snvs_lpgpr_probe() local
106 dcfg = of_device_get_match_data(dev); in snvs_lpgpr_probe()
107 if (!dcfg) in snvs_lpgpr_probe()
[all …]
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| /kernel/linux/linux-5.10/drivers/remoteproc/ |
| D | imx_rproc.c | 85 const struct imx_rproc_dcfg *dcfg; member
161 const struct imx_rproc_dcfg *dcfg = priv->dcfg; in imx_rproc_start() local
165 ret = regmap_update_bits(priv->regmap, dcfg->src_reg, in imx_rproc_start()
166 dcfg->src_mask, dcfg->src_start); in imx_rproc_start()
176 const struct imx_rproc_dcfg *dcfg = priv->dcfg; in imx_rproc_stop() local
180 ret = regmap_update_bits(priv->regmap, dcfg->src_reg, in imx_rproc_stop()
181 dcfg->src_mask, dcfg->src_stop); in imx_rproc_stop()
191 const struct imx_rproc_dcfg *dcfg = priv->dcfg; in imx_rproc_da_to_sys() local
195 for (i = 0; i < dcfg->att_size; i++) { in imx_rproc_da_to_sys()
196 const struct imx_rproc_att *att = &dcfg->att[i]; in imx_rproc_da_to_sys()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/freescale/ |
| D | fsl,layerscape-dcfg.txt | 1 Freescale DCFG
3 DCFG is the device configuration unit, that provides general purpose
9 Chip-specific strings are of the form "fsl,<chip>-dcfg",
13 - reg : should contain base address and length of DCFG memory-mapped registers
16 dcfg: dcfg@1ee0000 {
17 compatible = "fsl,ls1021a-dcfg";
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| /kernel/linux/linux-6.6/drivers/remoteproc/ |
| D | imx_rproc.c | 102 const struct imx_rproc_dcfg *dcfg; member
376 const struct imx_rproc_dcfg *dcfg = priv->dcfg; in imx_rproc_start() local
385 switch (dcfg->method) { in imx_rproc_start()
388 ret = regmap_clear_bits(priv->gpr, dcfg->gpr_reg, in imx_rproc_start()
389 dcfg->gpr_wait); in imx_rproc_start()
391 ret = regmap_update_bits(priv->regmap, dcfg->src_reg, in imx_rproc_start()
392 dcfg->src_mask, in imx_rproc_start()
393 dcfg->src_start); in imx_rproc_start()
416 const struct imx_rproc_dcfg *dcfg = priv->dcfg; in imx_rproc_stop() local
421 switch (dcfg->method) { in imx_rproc_stop()
[all …]
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| D | imx_dsp_rproc.c | 135 * @dcfg: imx_rproc_dcfg handler
139 const struct imx_rproc_dcfg *dcfg; member
248 .dcfg = &dsp_rproc_cfg_imx8mp,
264 .dcfg = &dsp_rproc_cfg_imx8ulp,
276 .dcfg = &dsp_rproc_cfg_imx8qxp,
287 .dcfg = &dsp_rproc_cfg_imx8qm,
319 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg; in imx_dsp_rproc_start() local
323 switch (dcfg->method) { in imx_dsp_rproc_start()
326 dcfg->src_reg, in imx_dsp_rproc_start()
327 dcfg->src_mask, in imx_dsp_rproc_start()
[all …]
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| /kernel/linux/linux-5.10/drivers/mailbox/ |
| D | imx-mailbox.c | 67 const struct imx_mu_dcfg *dcfg; member
108 val = imx_mu_read(priv, priv->dcfg->xCR); in imx_mu_xcr_rmw()
111 imx_mu_write(priv, val, priv->dcfg->xCR); in imx_mu_xcr_rmw()
125 imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]); in imx_mu_generic_tx()
145 dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]); in imx_mu_generic_rx()
177 imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]); in imx_mu_scu_tx()
179 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR, in imx_mu_scu_tx()
187 imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]); in imx_mu_scu_tx()
209 *data++ = imx_mu_read(priv, priv->dcfg->xRR[0]); in imx_mu_scu_rx()
217 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR, xsr, in imx_mu_scu_rx()
[all …]
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| /kernel/linux/linux-5.10/drivers/soc/fsl/ |
| D | guts.c | 229 { .compatible = "fsl,ls1021a-dcfg", },
230 { .compatible = "fsl,ls1043a-dcfg", },
231 { .compatible = "fsl,ls2080a-dcfg", },
232 { .compatible = "fsl,ls1088a-dcfg", },
233 { .compatible = "fsl,ls1012a-dcfg", },
234 { .compatible = "fsl,ls1046a-dcfg", },
235 { .compatible = "fsl,lx2160a-dcfg", },
236 { .compatible = "fsl,ls1028a-dcfg", },
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| /kernel/linux/linux-6.6/drivers/soc/fsl/ |
| D | guts.c | 170 { .compatible = "fsl,ls1021a-dcfg", },
171 { .compatible = "fsl,ls1043a-dcfg", },
172 { .compatible = "fsl,ls2080a-dcfg", },
173 { .compatible = "fsl,ls1088a-dcfg", },
174 { .compatible = "fsl,ls1012a-dcfg", },
175 { .compatible = "fsl,ls1046a-dcfg", },
176 { .compatible = "fsl,lx2160a-dcfg", },
177 { .compatible = "fsl,ls1028a-dcfg", .data = &ls1028a_data},
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| /kernel/linux/linux-5.10/drivers/net/ethernet/intel/ixgbe/ |
| D | ixgbe_dcb_nl.c | 26 struct ixgbe_dcb_config *dcfg = &adapter->dcb_cfg; in ixgbe_copy_dcb_cfg() local
46 dst = &dcfg->tc_config[i - DCB_PG_ATTR_TC_0]; in ixgbe_copy_dcb_cfg()
95 if (dcfg->bw_percentage[tx][j] != scfg->bw_percentage[tx][j]) { in ixgbe_copy_dcb_cfg()
96 dcfg->bw_percentage[tx][j] = scfg->bw_percentage[tx][j]; in ixgbe_copy_dcb_cfg()
99 if (dcfg->bw_percentage[rx][j] != scfg->bw_percentage[rx][j]) { in ixgbe_copy_dcb_cfg()
100 dcfg->bw_percentage[rx][j] = scfg->bw_percentage[rx][j]; in ixgbe_copy_dcb_cfg()
107 if (dcfg->tc_config[j].dcb_pfc != scfg->tc_config[j].dcb_pfc) { in ixgbe_copy_dcb_cfg()
108 dcfg->tc_config[j].dcb_pfc = scfg->tc_config[j].dcb_pfc; in ixgbe_copy_dcb_cfg()
113 if (dcfg->pfc_mode_enable != scfg->pfc_mode_enable) { in ixgbe_copy_dcb_cfg()
114 dcfg->pfc_mode_enable = scfg->pfc_mode_enable; in ixgbe_copy_dcb_cfg()
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| /kernel/linux/linux-6.6/drivers/net/ethernet/intel/ixgbe/ |
| D | ixgbe_dcb_nl.c | 24 struct ixgbe_dcb_config *dcfg = &adapter->dcb_cfg; in ixgbe_copy_dcb_cfg() local
44 dst = &dcfg->tc_config[i - DCB_PG_ATTR_TC_0]; in ixgbe_copy_dcb_cfg()
93 if (dcfg->bw_percentage[tx][j] != scfg->bw_percentage[tx][j]) { in ixgbe_copy_dcb_cfg()
94 dcfg->bw_percentage[tx][j] = scfg->bw_percentage[tx][j]; in ixgbe_copy_dcb_cfg()
97 if (dcfg->bw_percentage[rx][j] != scfg->bw_percentage[rx][j]) { in ixgbe_copy_dcb_cfg()
98 dcfg->bw_percentage[rx][j] = scfg->bw_percentage[rx][j]; in ixgbe_copy_dcb_cfg()
105 if (dcfg->tc_config[j].dcb_pfc != scfg->tc_config[j].dcb_pfc) { in ixgbe_copy_dcb_cfg()
106 dcfg->tc_config[j].dcb_pfc = scfg->tc_config[j].dcb_pfc; in ixgbe_copy_dcb_cfg()
111 if (dcfg->pfc_mode_enable != scfg->pfc_mode_enable) { in ixgbe_copy_dcb_cfg()
112 dcfg->pfc_mode_enable = scfg->pfc_mode_enable; in ixgbe_copy_dcb_cfg()
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| /kernel/linux/linux-6.6/drivers/iio/adc/ |
| D | ti-tsc2046.c | 143 const struct tsc2046_adc_dcfg *dcfg; member
794 const struct tsc2046_adc_dcfg *dcfg; in tsc2046_adc_probe() local
807 dcfg = device_get_match_data(dev); in tsc2046_adc_probe()
808 if (!dcfg) { in tsc2046_adc_probe()
811 dcfg = (const struct tsc2046_adc_dcfg *)id->driver_data; in tsc2046_adc_probe()
813 if (!dcfg) in tsc2046_adc_probe()
828 priv->dcfg = dcfg; in tsc2046_adc_probe()
834 indio_dev->channels = dcfg->channels; in tsc2046_adc_probe()
835 indio_dev->num_channels = dcfg->num_channels; in tsc2046_adc_probe()
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| /kernel/linux/linux-6.6/drivers/media/pci/pt1/ |
| D | pt1.c | 971 struct tc90522_config dcfg; in pt1_init_frontends() local
975 dcfg = pt1_configs[i].demod_cfg; in pt1_init_frontends()
976 dcfg.tuner_i2c = NULL; in pt1_init_frontends()
980 info->addr, &dcfg); in pt1_init_frontends()
991 tcfg.fe = dcfg.fe; in pt1_init_frontends()
993 info->type, dcfg.tuner_i2c, in pt1_init_frontends()
1000 tcfg.fe = dcfg.fe; in pt1_init_frontends()
1002 info->type, dcfg.tuner_i2c, in pt1_init_frontends()
1009 ret = pt1_init_frontend(pt1->adaps[i], dcfg.fe); in pt1_init_frontends()
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| /kernel/linux/linux-5.10/drivers/media/pci/pt1/ |
| D | pt1.c | 972 struct tc90522_config dcfg; in pt1_init_frontends() local
976 dcfg = pt1_configs[i].demod_cfg; in pt1_init_frontends()
977 dcfg.tuner_i2c = NULL; in pt1_init_frontends()
981 info->addr, &dcfg); in pt1_init_frontends()
992 tcfg.fe = dcfg.fe; in pt1_init_frontends()
994 info->type, dcfg.tuner_i2c, in pt1_init_frontends()
1001 tcfg.fe = dcfg.fe; in pt1_init_frontends()
1003 info->type, dcfg.tuner_i2c, in pt1_init_frontends()
1010 ret = pt1_init_frontend(pt1->adaps[i], dcfg.fe); in pt1_init_frontends()
|