| /kernel/linux/linux-6.6/drivers/pci/controller/dwc/ |
| D | pcie-tegra194.c | 3 * PCIe host controller driver for the following SoCs
35 #include "pcie-designware.h"
300 static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value, in appl_writel() argument
303 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
306 static inline u32 appl_readl(struct tegra_pcie_dw *pcie, const u32 reg) in appl_readl() argument
308 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
315 static void tegra_pcie_icc_set(struct tegra_pcie_dw *pcie) in tegra_pcie_icc_set() argument
317 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_icc_set()
320 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in tegra_pcie_icc_set()
327 if (icc_set_bw(pcie->icc_path, MBps_to_icc(val), 0)) in tegra_pcie_icc_set()
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| D | pcie-intel-gw.c | 3 * PCIe host controller driver for Intel Gateway SoCs
20 #include "pcie-designware.h"
26 /* PCIe Application logic Registers */
84 static inline void pcie_app_wr(struct intel_pcie *pcie, u32 ofs, u32 val) in pcie_app_wr() argument
86 writel(val, pcie->app_base + ofs); in pcie_app_wr()
89 static void pcie_app_wr_mask(struct intel_pcie *pcie, u32 ofs, in pcie_app_wr_mask() argument
92 pcie_update_bits(pcie->app_base, ofs, mask, val); in pcie_app_wr_mask()
95 static inline u32 pcie_rc_cfg_rd(struct intel_pcie *pcie, u32 ofs) in pcie_rc_cfg_rd() argument
97 return dw_pcie_readl_dbi(&pcie->pci, ofs); in pcie_rc_cfg_rd()
100 static inline void pcie_rc_cfg_wr(struct intel_pcie *pcie, u32 ofs, u32 val) in pcie_rc_cfg_wr() argument
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| D | Kconfig | 3 menu "DesignWare-based PCIe controllers"
18 bool "Amazon Annapurna Labs PCIe controller"
24 Say Y here to enable support of the Amazon's Annapurna Labs PCIe
25 controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
28 Annapurna Labs PCIe controller don't need to enable this.
31 tristate "Amlogic Meson PCIe controller"
45 bool "Axis ARTPEC-6 PCIe controller (host mode)"
51 Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
55 bool "Axis ARTPEC-6 PCIe controller (endpoint mode)"
61 Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
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| D | pcie-visconti.c | 3 * DWC PCIe RC driver for Toshiba Visconti ARM SoC
24 #include "pcie-designware.h"
96 /* Access registers in PCIe ulreg */
97 static void visconti_ulreg_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_ulreg_writel() argument
99 writel_relaxed(val, pcie->ulreg_base + reg); in visconti_ulreg_writel()
102 static u32 visconti_ulreg_readl(struct visconti_pcie *pcie, u32 reg) in visconti_ulreg_readl() argument
104 return readl_relaxed(pcie->ulreg_base + reg); in visconti_ulreg_readl()
107 /* Access registers in PCIe smu */
108 static void visconti_smu_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_smu_writel() argument
110 writel_relaxed(val, pcie->smu_base + reg); in visconti_smu_writel()
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| D | pcie-qcom.c | 3 * Qualcomm PCIe root complex driver
27 #include <linux/phy/pcie.h>
35 #include "pcie-designware.h"
222 int (*get_resources)(struct qcom_pcie *pcie);
223 int (*init)(struct qcom_pcie *pcie);
224 int (*post_init)(struct qcom_pcie *pcie);
225 void (*deinit)(struct qcom_pcie *pcie);
226 void (*ltssm_enable)(struct qcom_pcie *pcie);
227 int (*config_sid)(struct qcom_pcie *pcie);
250 static void qcom_ep_reset_assert(struct qcom_pcie *pcie) in qcom_ep_reset_assert() argument
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| D | pcie-uniphier.c | 3 * PCIe host controller driver for UniPhier SoCs
23 #include "pcie-designware.h"
75 static void uniphier_pcie_ltssm_enable(struct uniphier_pcie *pcie, in uniphier_pcie_ltssm_enable() argument
80 val = readl(pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
85 writel(val, pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
88 static void uniphier_pcie_init_rc(struct uniphier_pcie *pcie) in uniphier_pcie_init_rc() argument
93 val = readl(pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
96 writel(val, pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
99 val = readl(pcie->base + PCL_APP_PM0); in uniphier_pcie_init_rc()
101 writel(val, pcie->base + PCL_APP_PM0); in uniphier_pcie_init_rc()
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| D | pci-layerscape.c | 3 * PCIe host controller driver for Freescale Layerscape SoCs
26 #include "pcie-designware.h"
52 #define ls_pcie_pf_readl_addr(addr) ls_pcie_pf_readl(pcie, addr)
55 static bool ls_pcie_is_bridge(struct ls_pcie *pcie) in ls_pcie_is_bridge() argument
57 struct dw_pcie *pci = pcie->pci; in ls_pcie_is_bridge()
67 static void ls_pcie_clear_multifunction(struct ls_pcie *pcie) in ls_pcie_clear_multifunction() argument
69 struct dw_pcie *pci = pcie->pci; in ls_pcie_clear_multifunction()
75 static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) in ls_pcie_drop_msg_tlp() argument
78 struct dw_pcie *pci = pcie->pci; in ls_pcie_drop_msg_tlp()
86 static void ls_pcie_fix_error_response(struct ls_pcie *pcie) in ls_pcie_fix_error_response() argument
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| /kernel/linux/linux-5.10/drivers/pci/controller/dwc/ |
| D | pcie-tegra194.c | 3 * PCIe host controller driver for Tegra194 SoC
34 #include "pcie-designware.h"
321 static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value, in appl_writel() argument
324 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
327 static inline u32 appl_readl(struct tegra_pcie_dw *pcie, const u32 reg) in appl_readl() argument
329 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
339 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); in apply_bad_link_workaround() local
348 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in apply_bad_link_workaround()
351 if (pcie->init_link_width > current_link_width) { in apply_bad_link_workaround()
352 dev_warn(pci->dev, "PCIe link is bad, width reduced\n"); in apply_bad_link_workaround()
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| /kernel/linux/linux-6.6/drivers/pci/controller/ |
| D | pci-aardvark.c | 3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
32 /* PCIe core registers */
125 /* PCIe window configuration */
216 /* PCIe core controller registers */
224 /* PCIe Central Interrupts Registers */
293 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) in advk_writel() argument
295 writel(val, pcie->base + reg); in advk_writel()
298 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) in advk_readl() argument
300 return readl(pcie->base + reg); in advk_readl()
303 static u8 advk_pcie_ltssm_state(struct advk_pcie *pcie) in advk_pcie_ltssm_state() argument
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| D | pcie-altera.c | 6 * Description: Altera PCIe host controller driver
44 #define S10_RP_CFG_ADDR(pcie, reg) \ argument
45 (((pcie)->hip_base) + (reg) + (1 << 20))
46 #define S10_RP_SECONDARY(pcie) \ argument
47 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
59 #define TLP_CFG_DW0(pcie, cfg) \ argument
62 #define TLP_CFG_DW1(pcie, tag, be) \ argument
63 (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
98 int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);
99 void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers,
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| D | pcie-xilinx-nwl.c | 3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
161 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
176 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) in nwl_bridge_readl() argument
178 return readl(pcie->breg_base + off); in nwl_bridge_readl()
181 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) in nwl_bridge_writel() argument
183 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
186 static bool nwl_pcie_link_up(struct nwl_pcie *pcie) in nwl_pcie_link_up() argument
188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
193 static bool nwl_phy_link_up(struct nwl_pcie *pcie) in nwl_phy_link_up() argument
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| D | pci-tegra.c | 3 * PCIe host controller driver for Tegra SoCs
8 * Based on NVIDIA PCIe driver
11 * Bits taken from arch/arm/mach-dove/pcie.c
257 * entries, one entry per PCIe port. These field definitions and desired
362 struct tegra_pcie *pcie; member
375 static inline void afi_writel(struct tegra_pcie *pcie, u32 value, in afi_writel() argument
378 writel(value, pcie->afi + offset); in afi_writel()
381 static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset) in afi_readl() argument
383 return readl(pcie->afi + offset); in afi_readl()
386 static inline void pads_writel(struct tegra_pcie *pcie, u32 value, in pads_writel() argument
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| D | pcie-mediatek-gen3.c | 3 * MediaTek PCIe host controller driver.
116 * struct mtk_gen3_pcie - PCIe port information
117 * @dev: pointer to PCIe device
123 * @clks: PCIe clocks
124 * @num_clks: PCIe clocks count for this port
125 * @irq: PCIe controller interrupt number
199 struct mtk_gen3_pcie *pcie = bus->sysdata; in mtk_pcie_config_tlp_header() local
208 writel_relaxed(val, pcie->base + PCIE_CFGNUM_REG); in mtk_pcie_config_tlp_header()
214 struct mtk_gen3_pcie *pcie = bus->sysdata; in mtk_pcie_map_bus() local
216 return pcie->base + PCIE_CFG_OFFSET_ADDR + where; in mtk_pcie_map_bus()
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| D | pcie-brcmstb.c | 40 /* Broadcom STB PCIe Register Offsets */
147 /* PCIe parameters */
181 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX]) argument
182 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA]) argument
183 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1]) argument
221 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
222 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
248 /* Internal PCIe Host Controller Information.*/
265 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
266 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
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| D | pcie-xilinx.c | 3 * PCIe host controller driver for Xilinx AXI PCIe Bridge
7 * Based on the Tegra PCIe driver
94 * struct xilinx_pcie - PCIe port information
113 static inline u32 pcie_read(struct xilinx_pcie *pcie, u32 reg) in pcie_read() argument
115 return readl(pcie->reg_base + reg); in pcie_read()
118 static inline void pcie_write(struct xilinx_pcie *pcie, u32 val, u32 reg) in pcie_write() argument
120 writel(val, pcie->reg_base + reg); in pcie_write()
123 static inline bool xilinx_pcie_link_up(struct xilinx_pcie *pcie) in xilinx_pcie_link_up() argument
125 return (pcie_read(pcie, XILINX_PCIE_REG_PSCR) & in xilinx_pcie_link_up()
131 * @pcie: PCIe port information
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| D | pcie-rcar-host.c | 3 * PCIe driver for Renesas R-Car SoCs
7 * arch/sh/drivers/pci/pcie-sh7786.c
33 #include "pcie-rcar.h"
44 /* Structure representing the PCIe interface */
46 struct rcar_pcie pcie; member
71 * Test if the PCIe controller received PM_ENTER_L1 DLLP and in rcar_pcie_wakeup()
72 * the PCIe controller is not in L1 link state. If true, apply in rcar_pcie_wakeup()
98 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) in rcar_read_conf() argument
101 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_read_conf()
123 static int rcar_pci_write_reg_workaround(struct rcar_pcie *pcie, u32 val, in rcar_pci_write_reg_workaround() argument
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| /kernel/linux/linux-5.10/drivers/pci/controller/ |
| D | pcie-altera.c | 6 * Description: Altera PCIe host controller driver
45 #define S10_RP_CFG_ADDR(pcie, reg) \ argument
46 (((pcie)->hip_base) + (reg) + (1 << 20))
47 #define S10_RP_SECONDARY(pcie) \ argument
48 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
60 #define TLP_CFG_DW0(pcie, cfg) \ argument
63 #define TLP_CFG_DW1(pcie, tag, be) \ argument
64 (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
99 int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);
100 void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers,
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| D | pci-tegra.c | 3 * PCIe host controller driver for Tegra SoCs
8 * Based on NVIDIA PCIe driver
11 * Bits taken from arch/arm/mach-dove/pcie.c
271 * entries, one entry per PCIe port. These field definitions and desired
376 struct tegra_pcie *pcie; member
394 static inline void afi_writel(struct tegra_pcie *pcie, u32 value, in afi_writel() argument
397 writel(value, pcie->afi + offset); in afi_writel()
400 static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset) in afi_readl() argument
402 return readl(pcie->afi + offset); in afi_readl()
405 static inline void pads_writel(struct tegra_pcie *pcie, u32 value, in pads_writel() argument
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| D | pci-aardvark.c | 3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
30 /* PCIe core registers */
121 /* PCIe window configuration */
212 /* PCIe core controller registers */
220 /* PCIe Central Interrupts Registers */
299 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) in advk_writel() argument
301 writel(val, pcie->base + reg); in advk_writel()
304 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) in advk_readl() argument
306 return readl(pcie->base + reg); in advk_readl()
309 static u8 advk_pcie_ltssm_state(struct advk_pcie *pcie) in advk_pcie_ltssm_state() argument
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| D | pcie-xilinx-nwl.c | 3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
161 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
176 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) in nwl_bridge_readl() argument
178 return readl(pcie->breg_base + off); in nwl_bridge_readl()
181 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) in nwl_bridge_writel() argument
183 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
186 static bool nwl_pcie_link_up(struct nwl_pcie *pcie) in nwl_pcie_link_up() argument
188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
193 static bool nwl_phy_link_up(struct nwl_pcie *pcie) in nwl_phy_link_up() argument
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/ |
| D | fsl,imx6q-pcie-common.yaml | 4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#
7 title: Freescale i.MX6 PCIe RC/EP controller
14 Generic Freescale i.MX PCIe Root Port and Endpoint controller
29 fsl,imx7d-pcie-phy:
31 description: A phandle to an fsl,imx7d-pcie-phy node. Additional
32 required properties for imx7d-pcie, imx7d-pcie-ep, imx8mq-pcie,
33 and imx8mq-pcie-ep.
39 imx6sx-pcie, imx6sx-pcie-ep, to PCIE_PHY power domain for
40 imx7d-pcie, imx7d-pcie-ep, imx8mq-pcie and imx8mq-pcie-ep.
42 for imx6sx-pcie and imx6sx-pcie-ep.
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| D | qcom,pcie.yaml | 4 $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
15 PCIe IP.
21 - qcom,pcie-apq8064
22 - qcom,pcie-apq8084
23 - qcom,pcie-ipq4019
24 - qcom,pcie-ipq6018
25 - qcom,pcie-ipq8064
26 - qcom,pcie-ipq8064-v2
27 - qcom,pcie-ipq8074
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| /kernel/linux/linux-5.10/drivers/staging/mt7621-pci/ |
| D | pci-mt7621.c | 12 * support RT2880/RT3883 PCIe
15 * support RT6855/MT7620 PCIe
66 /* PCIe RC control registers */
92 * struct mt7621_pcie_port - PCIe port information
95 * @pcie: pointer to PCIe host info
106 struct mt7621_pcie *pcie; member
116 * struct mt7621_pcie - PCIe host information
122 * @dev: Pointer to PCIe device
124 * @ports: pointer to PCIe port information
125 * @irq_map: irq mapping info according pcie link status
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| /kernel/linux/linux-5.10/drivers/pci/controller/mobiveil/ |
| D | pcie-mobiveil-host.c | 3 * PCIe host controller driver for Mobiveil PCIe Host controller
28 #include "pcie-mobiveil.h"
53 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus() local
54 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
62 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
74 mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0)); in mobiveil_pcie_map_bus()
88 struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc); in mobiveil_pcie_isr() local
89 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_isr()
90 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_isr()
105 val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); in mobiveil_pcie_isr()
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| /kernel/linux/linux-6.6/drivers/pci/controller/mobiveil/ |
| D | pcie-mobiveil-host.c | 3 * PCIe host controller driver for Mobiveil PCIe Host controller
25 #include "pcie-mobiveil.h"
50 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus() local
51 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
59 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
71 mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0)); in mobiveil_pcie_map_bus()
85 struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc); in mobiveil_pcie_isr() local
86 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_isr()
87 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_isr()
102 val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); in mobiveil_pcie_isr()
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