Home
last modified time | relevance | path

Searched +full:cdns +full:- +full:pcie +full:- +full:host (Results 1 – 25 of 38) sorted by relevance

12

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dcdns,cdns-pcie-host.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence PCIe host controller
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: "cdns-pcie-host.yaml#"
18 const: cdns,cdns-pcie-host
23 reg-names:
[all …]
Dcdns-pcie-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Cadence PCIe Host
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: "/schemas/pci/pci-bus.yaml#"
14 - $ref: "cdns-pcie.yaml#"
17 cdns,max-outbound-regions:
25 cdns,no-bar-match-nbits:
[all …]
Dti,j721e-pci-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI J721E PCI Host (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: "cdns-pcie-host.yaml#"
19 - ti,j721e-pcie-host
24 reg-names:
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/
Dcdns,cdns-pcie-host.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence PCIe host controller
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: cdns-pcie-host.yaml#
18 const: cdns,cdns-pcie-host
23 reg-names:
[all …]
Dcdns-pcie-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence PCIe Host
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: cdns-pcie.yaml#
17 cdns,max-outbound-regions:
25 cdns,no-bar-match-nbits:
[all …]
Dti,j721e-pci-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721E PCI Host (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: cdns-pcie-host.yaml#
19 - const: ti,j721e-pcie-host
20 - description: PCIe controller in AM64
[all …]
/kernel/linux/linux-6.6/drivers/pci/controller/cadence/
Dpcie-cadence-plat.c1 // SPDX-License-Identifier: GPL-2.0
3 * Cadence PCIe platform driver.
13 #include "pcie-cadence.h"
18 * struct cdns_plat_pcie - private data for this PCIe platform driver
19 * @pcie: Cadence PCIe controller
20 * @is_rc: Set to 1 indicates the PCIe controller mode is Root Complex,
24 struct cdns_pcie *pcie; member
34 static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) in cdns_plat_cpu_addr_fixup() argument
47 struct device *dev = &pdev->dev; in cdns_plat_pcie_probe()
57 return -EINVAL; in cdns_plat_pcie_probe()
[all …]
Dpcie-cadence-ep.c1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe endpoint controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
9 #include <linux/pci-epc.h>
13 #include "pcie-cadence.h"
19 static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) in cdns_pcie_get_fn_from_vfn() argument
27 first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OFFSET); in cdns_pcie_get_fn_from_vfn()
28 stride = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); in cdns_pcie_get_fn_from_vfn()
29 fn = fn + first_vf_offset + ((vfn - 1) * stride); in cdns_pcie_get_fn_from_vfn()
39 struct cdns_pcie *pcie = &ep->pcie; in cdns_pcie_ep_write_header() local
[all …]
Dpcie-cadence-host.c1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe host controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
13 #include "pcie-cadence.h"
33 struct cdns_pcie *pcie = &rc->pcie; in cdns_pci_map_bus() local
34 unsigned int busn = bus->number; in cdns_pci_map_bus()
46 return pcie->reg_base + (where & 0xfff); in cdns_pci_map_bus()
49 if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1)) in cdns_pci_map_bus()
51 /* Clear AXI link-down status */ in cdns_pci_map_bus()
52 cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0); in cdns_pci_map_bus()
[all …]
/kernel/linux/linux-5.10/drivers/pci/controller/cadence/
Dpcie-cadence-plat.c1 // SPDX-License-Identifier: GPL-2.0
3 * Cadence PCIe platform driver.
14 #include "pcie-cadence.h"
19 * struct cdns_plat_pcie - private data for this PCIe platform driver
20 * @pcie: Cadence PCIe controller
21 * @is_rc: Set to 1 indicates the PCIe controller mode is Root Complex,
25 struct cdns_pcie *pcie; member
35 static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) in cdns_plat_cpu_addr_fixup() argument
49 struct device *dev = &pdev->dev; in cdns_plat_pcie_probe()
59 return -EINVAL; in cdns_plat_pcie_probe()
[all …]
Dpcie-cadence-ep.c1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe endpoint controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
9 #include <linux/pci-epc.h>
13 #include "pcie-cadence.h"
23 struct cdns_pcie *pcie = &ep->pcie; in cdns_pcie_ep_write_header() local
25 cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); in cdns_pcie_ep_write_header()
26 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid); in cdns_pcie_ep_write_header()
27 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code); in cdns_pcie_ep_write_header()
28 cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE, in cdns_pcie_ep_write_header()
[all …]
Dpcie-cadence-host.c1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe host controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
13 #include "pcie-cadence.h"
33 struct cdns_pcie *pcie = &rc->pcie; in cdns_pci_map_bus() local
34 unsigned int busn = bus->number; in cdns_pci_map_bus()
46 return pcie->reg_base + (where & 0xfff); in cdns_pci_map_bus()
49 if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1)) in cdns_pci_map_bus()
51 /* Clear AXI link-down status */ in cdns_pci_map_bus()
52 cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0); in cdns_pci_map_bus()
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/
Dk3-j721e-common-proc-board.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include "k3-j721e-som-p0.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/net/ti-dp83867.h>
15 stdout-path = "serial2:115200n8";
19 gpio_keys: gpio-keys {
20 compatible = "gpio-keys";
[all …]
Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/mux/ti-serdes.h>
12 cmn_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
18 cmn_refclk1: clock-cmnrefclk1 {
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/socionext/
Duniphier-pxs3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-pxs3";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <0>;
[all …]
Duniphier-ld20.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-ld20";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/xilinx/
Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
24 #address-cells = <2>;
25 #size-cells = <2>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/ti/
Dk3-j721e-common-proc-board.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include "k3-j721e-som-p0.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/net/ti-dp83867.h>
14 #include <dt-bindings/phy/phy-cadence.h>
17 compatible = "ti,j721e-evm", "ti,j721e";
33 stdout-path = "serial2:115200n8";
[all …]
Dk3-am64-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
[all …]
Dk3-am642-phyboard-electra-rdk.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
10 * https://www.phytec.com/product/phyboard-am64x
13 /dts-v1/;
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/leds/common.h>
18 #include <dt-bindings/leds/leds-pca9532.h>
19 #include <dt-bindings/phy/phy.h>
20 #include "k3-am642.dtsi"
[all …]
Dk3-j721e-sk.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
5 * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM
8 /dts-v1/;
10 #include "k3-j721e.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/net/ti-dp83867.h>
16 compatible = "ti,j721e-sk", "ti,j721e";
29 stdout-path = "serial2:115200n8";
[all …]
Dk3-am65-iot2050-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) Siemens AG, 2018-2021
12 #include "k3-am654.dtsi"
13 #include <dt-bindings/phy/phy.h>
33 stdout-path = "serial3:115200n8";
36 reserved-memory {
37 #address-cells = <2>;
38 #size-cells = <2>;
41 secure_ddr: secure-ddr@9e800000 {
42 reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
[all …]
Dk3-j721e-beagleboneai64.dts1 // SPDX-License-Identifier: GPL-2.0
3 * https://beagleboard.org/ai-64
4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
11 #include "k3-j721e.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/leds/common.h>
15 #include <dt-bindings/net/ti-dp83867.h>
16 #include <dt-bindings/phy/phy-cadence.h>
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/socionext/
Duniphier-pxs3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "socionext,uniphier-pxs3";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
20 #address-cells = <2>;
[all …]
Duniphier-ld20.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "socionext,uniphier-ld20";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
[all …]

12