1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM 6 */ 7 8/dts-v1/; 9 10#include "k3-j721e.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/net/ti-dp83867.h> 14 15/ { 16 compatible = "ti,j721e-sk", "ti,j721e"; 17 model = "Texas Instruments J721E SK"; 18 19 aliases { 20 serial0 = &wkup_uart0; 21 serial1 = &mcu_uart0; 22 serial2 = &main_uart0; 23 serial3 = &main_uart1; 24 ethernet0 = &cpsw_port1; 25 mmc1 = &main_sdhci1; 26 }; 27 28 chosen { 29 stdout-path = "serial2:115200n8"; 30 }; 31 32 memory@80000000 { 33 device_type = "memory"; 34 /* 4G RAM */ 35 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 36 <0x00000008 0x80000000 0x00000000 0x80000000>; 37 }; 38 39 reserved_memory: reserved-memory { 40 #address-cells = <2>; 41 #size-cells = <2>; 42 ranges; 43 44 secure_ddr: optee@9e800000 { 45 reg = <0x00 0x9e800000 0x00 0x01800000>; 46 alignment = <0x1000>; 47 no-map; 48 }; 49 50 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 51 compatible = "shared-dma-pool"; 52 reg = <0x00 0xa0000000 0x00 0x100000>; 53 no-map; 54 }; 55 56 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 57 compatible = "shared-dma-pool"; 58 reg = <0x00 0xa0100000 0x00 0xf00000>; 59 no-map; 60 }; 61 62 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 63 compatible = "shared-dma-pool"; 64 reg = <0x00 0xa1000000 0x00 0x100000>; 65 no-map; 66 }; 67 68 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 69 compatible = "shared-dma-pool"; 70 reg = <0x00 0xa1100000 0x00 0xf00000>; 71 no-map; 72 }; 73 74 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 75 compatible = "shared-dma-pool"; 76 reg = <0x00 0xa2000000 0x00 0x100000>; 77 no-map; 78 }; 79 80 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 81 compatible = "shared-dma-pool"; 82 reg = <0x00 0xa2100000 0x00 0xf00000>; 83 no-map; 84 }; 85 86 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 87 compatible = "shared-dma-pool"; 88 reg = <0x00 0xa3000000 0x00 0x100000>; 89 no-map; 90 }; 91 92 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 93 compatible = "shared-dma-pool"; 94 reg = <0x00 0xa3100000 0x00 0xf00000>; 95 no-map; 96 }; 97 98 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 99 compatible = "shared-dma-pool"; 100 reg = <0x00 0xa4000000 0x00 0x100000>; 101 no-map; 102 }; 103 104 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 105 compatible = "shared-dma-pool"; 106 reg = <0x00 0xa4100000 0x00 0xf00000>; 107 no-map; 108 }; 109 110 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 111 compatible = "shared-dma-pool"; 112 reg = <0x00 0xa5000000 0x00 0x100000>; 113 no-map; 114 }; 115 116 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 117 compatible = "shared-dma-pool"; 118 reg = <0x00 0xa5100000 0x00 0xf00000>; 119 no-map; 120 }; 121 122 c66_0_dma_memory_region: c66-dma-memory@a6000000 { 123 compatible = "shared-dma-pool"; 124 reg = <0x00 0xa6000000 0x00 0x100000>; 125 no-map; 126 }; 127 128 c66_0_memory_region: c66-memory@a6100000 { 129 compatible = "shared-dma-pool"; 130 reg = <0x00 0xa6100000 0x00 0xf00000>; 131 no-map; 132 }; 133 134 c66_1_dma_memory_region: c66-dma-memory@a7000000 { 135 compatible = "shared-dma-pool"; 136 reg = <0x00 0xa7000000 0x00 0x100000>; 137 no-map; 138 }; 139 140 c66_1_memory_region: c66-memory@a7100000 { 141 compatible = "shared-dma-pool"; 142 reg = <0x00 0xa7100000 0x00 0xf00000>; 143 no-map; 144 }; 145 146 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 147 compatible = "shared-dma-pool"; 148 reg = <0x00 0xa8000000 0x00 0x100000>; 149 no-map; 150 }; 151 152 c71_0_memory_region: c71-memory@a8100000 { 153 compatible = "shared-dma-pool"; 154 reg = <0x00 0xa8100000 0x00 0xf00000>; 155 no-map; 156 }; 157 158 rtos_ipc_memory_region: ipc-memories@aa000000 { 159 reg = <0x00 0xaa000000 0x00 0x01c00000>; 160 alignment = <0x1000>; 161 no-map; 162 }; 163 }; 164 165 vusb_main: fixedregulator-vusb-main5v0 { 166 /* USB MAIN INPUT 5V DC */ 167 compatible = "regulator-fixed"; 168 regulator-name = "vusb-main5v0"; 169 regulator-min-microvolt = <5000000>; 170 regulator-max-microvolt = <5000000>; 171 regulator-always-on; 172 regulator-boot-on; 173 }; 174 175 vsys_3v3: fixedregulator-vsys3v3 { 176 /* Output of LM5141 */ 177 compatible = "regulator-fixed"; 178 regulator-name = "vsys_3v3"; 179 regulator-min-microvolt = <3300000>; 180 regulator-max-microvolt = <3300000>; 181 vin-supply = <&vusb_main>; 182 regulator-always-on; 183 regulator-boot-on; 184 }; 185 186 vsys_5v0: fixedregulator-vsys5v0 { 187 /* Output of LM61460 */ 188 compatible = "regulator-fixed"; 189 regulator-name = "vsys_5v0"; 190 regulator-min-microvolt = <5000000>; 191 regulator-max-microvolt = <5000000>; 192 vin-supply = <&vusb_main>; 193 regulator-always-on; 194 regulator-boot-on; 195 }; 196 197 vdd_mmc1: fixedregulator-sd { 198 compatible = "regulator-fixed"; 199 pinctrl-names = "default"; 200 pinctrl-0 = <&vdd_mmc1_en_pins_default>; 201 regulator-name = "vdd_mmc1"; 202 regulator-min-microvolt = <3300000>; 203 regulator-max-microvolt = <3300000>; 204 regulator-boot-on; 205 enable-active-high; 206 vin-supply = <&vsys_3v3>; 207 gpio = <&wkup_gpio0 8 GPIO_ACTIVE_HIGH>; 208 }; 209 210 vdd_sd_dv_alt: gpio-regulator-tps659411 { 211 compatible = "regulator-gpio"; 212 pinctrl-names = "default"; 213 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; 214 regulator-name = "tps659411"; 215 regulator-min-microvolt = <1800000>; 216 regulator-max-microvolt = <3300000>; 217 regulator-boot-on; 218 vin-supply = <&vsys_3v3>; 219 gpios = <&wkup_gpio0 9 GPIO_ACTIVE_HIGH>; 220 states = <1800000 0x0>, 221 <3300000 0x1>; 222 }; 223 224 vdd_sd_dv: gpio-regulator-TLV71033 { 225 compatible = "regulator-gpio"; 226 pinctrl-names = "default"; 227 pinctrl-0 = <&vdd_sd_dv_pins_default>; 228 regulator-name = "tlv71033"; 229 regulator-min-microvolt = <1800000>; 230 regulator-max-microvolt = <3300000>; 231 regulator-boot-on; 232 vin-supply = <&vsys_5v0>; 233 gpios = <&main_gpio0 118 GPIO_ACTIVE_HIGH>; 234 states = <1800000 0x0>, 235 <3300000 0x1>; 236 }; 237 238 transceiver1: can-phy1 { 239 compatible = "ti,tcan1042"; 240 #phy-cells = <0>; 241 max-bitrate = <5000000>; 242 pinctrl-names = "default"; 243 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; 244 standby-gpios = <&wkup_gpio0 3 GPIO_ACTIVE_HIGH>; 245 }; 246 247 transceiver2: can-phy2 { 248 compatible = "ti,tcan1042"; 249 #phy-cells = <0>; 250 max-bitrate = <5000000>; 251 pinctrl-names = "default"; 252 pinctrl-0 = <&main_mcan0_gpio_pins_default>; 253 standby-gpios = <&main_gpio0 65 GPIO_ACTIVE_HIGH>; 254 }; 255 256 transceiver3: can-phy3 { 257 compatible = "ti,tcan1042"; 258 #phy-cells = <0>; 259 max-bitrate = <5000000>; 260 pinctrl-names = "default"; 261 pinctrl-0 = <&main_mcan5_gpio_pins_default>; 262 standby-gpios = <&main_gpio0 66 GPIO_ACTIVE_HIGH>; 263 }; 264 265 transceiver4: can-phy4 { 266 compatible = "ti,tcan1042"; 267 #phy-cells = <0>; 268 max-bitrate = <5000000>; 269 pinctrl-names = "default"; 270 pinctrl-0 = <&main_mcan9_gpio_pins_default>; 271 standby-gpios = <&main_gpio0 67 GPIO_ACTIVE_HIGH>; 272 }; 273 274 dp_pwr_3v3: fixedregulator-dp-prw { 275 compatible = "regulator-fixed"; 276 regulator-name = "dp-pwr"; 277 regulator-min-microvolt = <3300000>; 278 regulator-max-microvolt = <3300000>; 279 pinctrl-names = "default"; 280 pinctrl-0 = <&dp_pwr_en_pins_default>; 281 gpio = <&main_gpio0 111 0>; /* DP0_3V3 _EN */ 282 enable-active-high; 283 }; 284 285 dp0: connector { 286 compatible = "dp-connector"; 287 label = "DP0"; 288 type = "full-size"; 289 dp-pwr-supply = <&dp_pwr_3v3>; 290 291 port { 292 dp_connector_in: endpoint { 293 remote-endpoint = <&dp0_out>; 294 }; 295 }; 296 }; 297 298 hdmi-connector { 299 compatible = "hdmi-connector"; 300 label = "hdmi"; 301 type = "a"; 302 303 pinctrl-names = "default"; 304 pinctrl-0 = <&hdmi_hpd_pins_default>; 305 306 ddc-i2c-bus = <&main_i2c1>; 307 308 /* HDMI_HPD */ 309 hpd-gpios = <&main_gpio1 0 GPIO_ACTIVE_HIGH>; 310 311 port { 312 hdmi_connector_in: endpoint { 313 remote-endpoint = <&tfp410_out>; 314 }; 315 }; 316 }; 317 318 dvi-bridge { 319 compatible = "ti,tfp410"; 320 321 pinctrl-names = "default"; 322 pinctrl-0 = <&hdmi_pdn_pins_default>; 323 324 powerdown-gpios = <&main_gpio0 127 GPIO_ACTIVE_LOW>; 325 ti,deskew = <0>; 326 327 ports { 328 #address-cells = <1>; 329 #size-cells = <0>; 330 331 port@0 { 332 reg = <0>; 333 334 tfp410_in: endpoint { 335 remote-endpoint = <&dpi1_out>; 336 pclk-sample = <1>; 337 }; 338 }; 339 340 port@1 { 341 reg = <1>; 342 343 tfp410_out: endpoint { 344 remote-endpoint = 345 <&hdmi_connector_in>; 346 }; 347 }; 348 }; 349 }; 350 351 csi_mux: mux-controller { 352 compatible = "gpio-mux"; 353 #mux-state-cells = <1>; 354 mux-gpios = <&main_gpio0 88 GPIO_ACTIVE_HIGH>; 355 idle-state = <0>; 356 pinctrl-names = "default"; 357 pinctrl-0 = <&main_csi_mux_sel_pins_default>; 358 }; 359}; 360 361&main_pmx0 { 362 main_mmc1_pins_default: main-mmc1-default-pins { 363 pinctrl-single,pins = < 364 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ 365 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ 366 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 367 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ 368 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 369 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ 370 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ 371 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ 372 >; 373 }; 374 375 main_uart0_pins_default: main-uart0-default-pins { 376 pinctrl-single,pins = < 377 J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */ 378 J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */ 379 J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ 380 J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ 381 >; 382 }; 383 384 main_uart1_pins_default: main-uart1-default-pins { 385 pinctrl-single,pins = < 386 J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ 387 J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ 388 >; 389 }; 390 391 main_i2c0_pins_default: main-i2c0-default-pins { 392 pinctrl-single,pins = < 393 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ 394 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ 395 >; 396 }; 397 398 main_i2c1_pins_default: main-i2c1-default-pins { 399 pinctrl-single,pins = < 400 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ 401 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ 402 >; 403 }; 404 405 main_i2c3_pins_default: main-i2c3-default-pins { 406 pinctrl-single,pins = < 407 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ 408 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ 409 >; 410 }; 411 412 main_usbss0_pins_default: main-usbss0-default-pins { 413 pinctrl-single,pins = < 414 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ 415 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ 416 >; 417 }; 418 419 main_usbss1_pins_default: main-usbss1-default-pins { 420 pinctrl-single,pins = < 421 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ 422 >; 423 }; 424 425 main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins { 426 pinctrl-single,pins = < 427 J721E_IOPAD(0x164, PIN_OUTPUT, 7) /* (V29) RGMII5_TD2 */ 428 >; 429 }; 430 431 main_mcan0_pins_default: main-mcan0-default-pins { 432 pinctrl-single,pins = < 433 J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */ 434 J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */ 435 >; 436 }; 437 438 main_mcan0_gpio_pins_default: main-mcan0-gpio-default-pins { 439 pinctrl-single,pins = < 440 J721E_IOPAD(0x108, PIN_INPUT, 7) /* (AD27) PRG0_PRU1_GPO2.GPIO0_65 */ 441 >; 442 }; 443 444 main_mcan5_pins_default: main-mcan5-default-pins { 445 pinctrl-single,pins = < 446 J721E_IOPAD(0x050, PIN_INPUT, 6) /* (AE21) PRG1_PRU0_GPO18.MCAN5_RX */ 447 J721E_IOPAD(0x04c, PIN_OUTPUT, 6) /* (AJ21) PRG1_PRU0_GPO17.MCAN5_TX */ 448 >; 449 }; 450 451 main_mcan5_gpio_pins_default: main-mcan5-gpio-default-pins { 452 pinctrl-single,pins = < 453 J721E_IOPAD(0x10c, PIN_INPUT, 7) /* (AC25) PRG0_PRU1_GPO3.GPIO0_66 */ 454 >; 455 }; 456 457 main_mcan9_pins_default: main-mcan9-default-pins { 458 pinctrl-single,pins = < 459 J721E_IOPAD(0x0d0, PIN_INPUT, 6) /* (AC27) PRG0_PRU0_GPO8.MCAN9_RX */ 460 J721E_IOPAD(0x0cc, PIN_OUTPUT, 6) /* (AC28) PRG0_PRU0_GPO7.MCAN9_TX */ 461 >; 462 }; 463 464 main_mcan9_gpio_pins_default: main-mcan9-gpio-default-pins { 465 pinctrl-single,pins = < 466 J721E_IOPAD(0x110, PIN_INPUT, 7) /* (AD29) PRG0_PRU1_GPO4.GPIO0_67 */ 467 >; 468 }; 469 470 dp0_pins_default: dp0-default-pins { 471 pinctrl-single,pins = < 472 J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ 473 >; 474 }; 475 476 dp_pwr_en_pins_default: dp-pwr-en-default-pins { 477 pinctrl-single,pins = < 478 J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */ 479 >; 480 }; 481 482 dss_vout0_pins_default: dss-vout0-default-pins { 483 pinctrl-single,pins = < 484 J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */ 485 J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */ 486 J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */ 487 J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */ 488 J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */ 489 J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */ 490 J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */ 491 J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */ 492 J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */ 493 J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */ 494 J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */ 495 J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */ 496 J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */ 497 J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */ 498 J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */ 499 J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */ 500 J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */ 501 J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */ 502 J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */ 503 J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */ 504 J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */ 505 J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */ 506 J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */ 507 J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */ 508 J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */ 509 J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */ 510 J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */ 511 J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */ 512 >; 513 }; 514 515 hdmi_hpd_pins_default: hdmi-hpd-default-pins { 516 pinctrl-single,pins = < 517 J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */ 518 >; 519 }; 520 521 hdmi_pdn_pins_default: hdmi-pdn-default-pins { 522 pinctrl-single,pins = < 523 J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ 524 >; 525 }; 526 527 /* Reset for M.2 E Key slot on PCIe0 */ 528 ekey_reset_pins_default: ekey-reset-pns-default-pins { 529 pinctrl-single,pins = < 530 J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ 531 >; 532 }; 533 534 main_i2c5_pins_default: main-i2c5-default-pins { 535 pinctrl-single,pins = < 536 J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ 537 J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ 538 >; 539 }; 540 541 rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { 542 pinctrl-single,pins = < 543 J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ 544 J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */ 545 J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ 546 J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */ 547 J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ 548 J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ 549 J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ 550 J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */ 551 J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */ 552 J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */ 553 J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */ 554 J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */ 555 J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */ 556 J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */ 557 J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ 558 J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */ 559 J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ 560 J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */ 561 J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */ 562 J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */ 563 J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */ 564 J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */ 565 J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */ 566 >; 567 }; 568 569 rpi_header_gpio1_pins_default: rpi-header-gpio1-default-pins { 570 pinctrl-single,pins = < 571 J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */ 572 >; 573 }; 574}; 575 576&wkup_pmx0 { 577 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 578 pinctrl-single,pins = < 579 J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ 580 J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ 581 J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */ 582 J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */ 583 J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */ 584 J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */ 585 J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */ 586 J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */ 587 J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */ 588 J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */ 589 J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */ 590 J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */ 591 >; 592 }; 593 594 mcu_mdio_pins_default: mcu-mdio1-default-pins { 595 pinctrl-single,pins = < 596 J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ 597 J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ 598 >; 599 }; 600 601 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 602 pinctrl-single,pins = < 603 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */ 604 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */ 605 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */ 606 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */ 607 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */ 608 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */ 609 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */ 610 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */ 611 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */ 612 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */ 613 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */ 614 >; 615 }; 616 617 vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins { 618 pinctrl-single,pins = < 619 J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */ 620 >; 621 }; 622 623 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { 624 pinctrl-single,pins = < 625 J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */ 626 >; 627 }; 628 629 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 630 pinctrl-single,pins = < 631 J721E_IOPAD(0x1dc, PIN_OUTPUT, 7) /* (Y1) SPI1_CLK.GPIO0_118 */ 632 >; 633 }; 634 635 wkup_uart0_pins_default: wkup-uart0-default-pins { 636 pinctrl-single,pins = < 637 J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ 638 J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ 639 >; 640 }; 641 642 mcu_uart0_pins_default: mcu-uart0-default-pins { 643 pinctrl-single,pins = < 644 J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */ 645 J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */ 646 J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ 647 J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ 648 >; 649 }; 650 651 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 652 pinctrl-single,pins = < 653 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ 654 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ 655 >; 656 }; 657 658 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 659 pinctrl-single,pins = < 660 J721E_WKUP_IOPAD(0x0ac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */ 661 J721E_WKUP_IOPAD(0x0a8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */ 662 >; 663 }; 664 665 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { 666 pinctrl-single,pins = < 667 J721E_WKUP_IOPAD(0x0bc, PIN_INPUT, 7) /* (F27) WKUP_GPIO0_3 */ 668 >; 669 }; 670 671 /* Reset for M.2 M Key slot on PCIe1 */ 672 mkey_reset_pins_default: mkey-reset-pns-default-pins { 673 pinctrl-single,pins = < 674 J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */ 675 >; 676 }; 677}; 678 679&wkup_uart0 { 680 /* Wakeup UART is used by System firmware */ 681 status = "reserved"; 682 pinctrl-names = "default"; 683 pinctrl-0 = <&wkup_uart0_pins_default>; 684}; 685 686&wkup_i2c0 { 687 status = "okay"; 688 pinctrl-names = "default"; 689 pinctrl-0 = <&wkup_i2c0_pins_default>; 690 clock-frequency = <400000>; 691 692 eeprom@51 { 693 /* AT24C512C-MAHM-T */ 694 compatible = "atmel,24c512"; 695 reg = <0x51>; 696 }; 697}; 698 699&mcu_uart0 { 700 status = "okay"; 701 pinctrl-names = "default"; 702 pinctrl-0 = <&mcu_uart0_pins_default>; 703}; 704 705&main_uart0 { 706 status = "okay"; 707 pinctrl-names = "default"; 708 pinctrl-0 = <&main_uart0_pins_default>; 709 /* Shared with ATF on this platform */ 710 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 711}; 712 713&main_uart1 { 714 status = "okay"; 715 pinctrl-names = "default"; 716 pinctrl-0 = <&main_uart1_pins_default>; 717}; 718 719&main_sdhci1 { 720 /* SD Card */ 721 status = "okay"; 722 vmmc-supply = <&vdd_mmc1>; 723 vqmmc-supply = <&vdd_sd_dv_alt>; 724 pinctrl-names = "default"; 725 pinctrl-0 = <&main_mmc1_pins_default>; 726 ti,driver-strength-ohm = <50>; 727 disable-wp; 728}; 729 730&ospi0 { 731 status = "okay"; 732 pinctrl-names = "default"; 733 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 734 735 flash@0 { 736 compatible = "jedec,spi-nor"; 737 reg = <0x0>; 738 spi-tx-bus-width = <8>; 739 spi-rx-bus-width = <8>; 740 spi-max-frequency = <25000000>; 741 cdns,tshsl-ns = <60>; 742 cdns,tsd2d-ns = <60>; 743 cdns,tchsh-ns = <60>; 744 cdns,tslch-ns = <60>; 745 cdns,read-delay = <4>; 746 747 partitions { 748 compatible = "fixed-partitions"; 749 #address-cells = <1>; 750 #size-cells = <1>; 751 752 partition@0 { 753 label = "ospi.tiboot3"; 754 reg = <0x0 0x80000>; 755 }; 756 757 partition@80000 { 758 label = "ospi.tispl"; 759 reg = <0x80000 0x200000>; 760 }; 761 762 partition@280000 { 763 label = "ospi.u-boot"; 764 reg = <0x280000 0x400000>; 765 }; 766 767 partition@680000 { 768 label = "ospi.env"; 769 reg = <0x680000 0x40000>; 770 }; 771 772 partition@6c0000 { 773 label = "ospi.sysfw"; 774 reg = <0x6c0000 0x100000>; 775 }; 776 777 partition@7c0000 { 778 label = "ospi.env.backup"; 779 reg = <0x7c0000 0x40000>; 780 }; 781 782 partition@800000 { 783 label = "ospi.rootfs"; 784 reg = <0x800000 0x37c0000>; 785 }; 786 787 partition@3fc0000 { 788 label = "ospi.phypattern"; 789 reg = <0x3fc0000 0x40000>; 790 }; 791 }; 792 }; 793}; 794 795&main_i2c0 { 796 status = "okay"; 797 pinctrl-names = "default"; 798 pinctrl-0 = <&main_i2c0_pins_default>; 799 clock-frequency = <400000>; 800 801 i2c-mux@71 { 802 compatible = "nxp,pca9543"; 803 #address-cells = <1>; 804 #size-cells = <0>; 805 reg = <0x71>; 806 807 /* PCIe1 M.2 M Key I2C */ 808 i2c@0 { 809 #address-cells = <1>; 810 #size-cells = <0>; 811 reg = <0>; 812 }; 813 814 /* PCIe0 M.2 E Key I2C */ 815 i2c@1 { 816 #address-cells = <1>; 817 #size-cells = <0>; 818 reg = <1>; 819 }; 820 }; 821}; 822 823&main_i2c1 { 824 status = "okay"; 825 pinctrl-names = "default"; 826 pinctrl-0 = <&main_i2c1_pins_default>; 827 /* i2c1 is used for DVI DDC, so we need to use 100kHz */ 828 clock-frequency = <100000>; 829}; 830 831&main_i2c3 { 832 status = "okay"; 833 pinctrl-names = "default"; 834 pinctrl-0 = <&main_i2c3_pins_default>; 835 clock-frequency = <400000>; 836 837 i2c-mux@70 { 838 compatible = "nxp,pca9543"; 839 #address-cells = <1>; 840 #size-cells = <0>; 841 reg = <0x70>; 842 843 /* CSI0 I2C */ 844 cam0_i2c: i2c@0 { 845 #address-cells = <1>; 846 #size-cells = <0>; 847 reg = <0>; 848 }; 849 850 /* CSI1 I2C */ 851 cam1_i2c: i2c@1 { 852 #address-cells = <1>; 853 #size-cells = <0>; 854 reg = <1>; 855 }; 856 }; 857}; 858 859&main_i2c5 { 860 /* Brought out on RPi Header */ 861 status = "okay"; 862 pinctrl-names = "default"; 863 pinctrl-0 = <&main_i2c5_pins_default>; 864 clock-frequency = <400000>; 865}; 866 867&main_gpio0 { 868 status = "okay"; 869 pinctrl-names = "default"; 870 pinctrl-0 = <&rpi_header_gpio0_pins_default>; 871}; 872 873&main_gpio1 { 874 status = "okay"; 875 pinctrl-names = "default"; 876 pinctrl-0 = <&rpi_header_gpio1_pins_default>; 877}; 878 879&wkup_gpio0 { 880 status = "okay"; 881}; 882 883&usb_serdes_mux { 884 idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ 885}; 886 887&serdes_ln_ctrl { 888 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_IP4_UNUSED>, 889 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 890 <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>, 891 <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, 892 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 893 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 894}; 895 896&serdes_wiz3 { 897 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; 898 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ 899}; 900 901&serdes3 { 902 serdes3_usb_link: phy@0 { 903 reg = <0>; 904 cdns,num-lanes = <2>; 905 #phy-cells = <0>; 906 cdns,phy-type = <PHY_TYPE_USB3>; 907 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; 908 }; 909}; 910 911&serdes4 { 912 torrent_phy_dp: phy@0 { 913 reg = <0>; 914 resets = <&serdes_wiz4 1>; 915 cdns,phy-type = <PHY_TYPE_DP>; 916 cdns,num-lanes = <4>; 917 cdns,max-bit-rate = <5400>; 918 #phy-cells = <0>; 919 }; 920}; 921 922&mhdp { 923 phys = <&torrent_phy_dp>; 924 phy-names = "dpphy"; 925 pinctrl-names = "default"; 926 pinctrl-0 = <&dp0_pins_default>; 927}; 928 929&usbss0 { 930 pinctrl-names = "default"; 931 pinctrl-0 = <&main_usbss0_pins_default>; 932 ti,vbus-divider; 933}; 934 935&usb0 { 936 dr_mode = "otg"; 937 maximum-speed = "super-speed"; 938 phys = <&serdes3_usb_link>; 939 phy-names = "cdns3,usb3-phy"; 940}; 941 942&serdes2 { 943 serdes2_usb_link: phy@1 { 944 reg = <1>; 945 cdns,num-lanes = <1>; 946 #phy-cells = <0>; 947 cdns,phy-type = <PHY_TYPE_USB3>; 948 resets = <&serdes_wiz2 2>; 949 }; 950}; 951 952&usbss1 { 953 pinctrl-names = "default"; 954 pinctrl-0 = <&main_usbss1_pins_default>; 955 ti,vbus-divider; 956}; 957 958&usb1 { 959 dr_mode = "host"; 960 maximum-speed = "super-speed"; 961 phys = <&serdes2_usb_link>; 962 phy-names = "cdns3,usb3-phy"; 963}; 964 965&mcu_cpsw { 966 pinctrl-names = "default"; 967 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; 968}; 969 970&davinci_mdio { 971 phy0: ethernet-phy@0 { 972 reg = <0>; 973 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 974 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 975 }; 976}; 977 978&cpsw_port1 { 979 phy-mode = "rgmii-rxid"; 980 phy-handle = <&phy0>; 981}; 982 983&dss { 984 pinctrl-names = "default"; 985 pinctrl-0 = <&dss_vout0_pins_default>; 986 987 assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */ 988 <&k3_clks 152 4>, /* VP 2 pixel clock */ 989 <&k3_clks 152 9>, /* VP 3 pixel clock */ 990 <&k3_clks 152 13>; /* VP 4 pixel clock */ 991 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ 992 <&k3_clks 152 6>, /* DPI0_EXT_CLKSEL_OUT0 */ 993 <&k3_clks 152 11>, /* PLL18_HSDIV0 */ 994 <&k3_clks 152 18>; /* DPI1_EXT_CLKSEL_OUT0 */ 995}; 996 997&dss_ports { 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 1001 port@0 { 1002 reg = <0>; 1003 1004 dpi0_out: endpoint { 1005 remote-endpoint = <&dp0_in>; 1006 }; 1007 }; 1008 1009 port@1 { 1010 reg = <1>; 1011 1012 dpi1_out: endpoint { 1013 remote-endpoint = <&tfp410_in>; 1014 }; 1015 }; 1016}; 1017 1018&dp0_ports { 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 1022 port@0 { 1023 reg = <0>; 1024 dp0_in: endpoint { 1025 remote-endpoint = <&dpi0_out>; 1026 }; 1027 }; 1028 1029 port@4 { 1030 reg = <4>; 1031 dp0_out: endpoint { 1032 remote-endpoint = <&dp_connector_in>; 1033 }; 1034 }; 1035}; 1036 1037&serdes0 { 1038 serdes0_pcie_link: phy@0 { 1039 reg = <0>; 1040 cdns,num-lanes = <1>; 1041 #phy-cells = <0>; 1042 cdns,phy-type = <PHY_TYPE_PCIE>; 1043 resets = <&serdes_wiz0 1>; 1044 }; 1045}; 1046 1047&serdes1 { 1048 serdes1_pcie_link: phy@0 { 1049 reg = <0>; 1050 cdns,num-lanes = <2>; 1051 #phy-cells = <0>; 1052 cdns,phy-type = <PHY_TYPE_PCIE>; 1053 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; 1054 }; 1055}; 1056 1057&pcie0_rc { 1058 status = "okay"; 1059 pinctrl-names = "default"; 1060 pinctrl-0 = <&ekey_reset_pins_default>; 1061 reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>; 1062 1063 phys = <&serdes0_pcie_link>; 1064 phy-names = "pcie-phy"; 1065 num-lanes = <1>; 1066}; 1067 1068&pcie1_rc { 1069 status = "okay"; 1070 pinctrl-names = "default"; 1071 pinctrl-0 = <&mkey_reset_pins_default>; 1072 reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>; 1073 1074 phys = <&serdes1_pcie_link>; 1075 phy-names = "pcie-phy"; 1076 num-lanes = <2>; 1077}; 1078 1079&mcu_mcan0 { 1080 pinctrl-names = "default"; 1081 pinctrl-0 = <&mcu_mcan0_pins_default>; 1082 phys = <&transceiver1>; 1083 status = "okay"; 1084}; 1085 1086&main_mcan0 { 1087 pinctrl-names = "default"; 1088 pinctrl-0 = <&main_mcan0_pins_default>; 1089 phys = <&transceiver2>; 1090 status = "okay"; 1091}; 1092 1093&main_mcan5 { 1094 pinctrl-names = "default"; 1095 pinctrl-0 = <&main_mcan5_pins_default>; 1096 phys = <&transceiver3>; 1097 status = "okay"; 1098}; 1099 1100&main_mcan9 { 1101 pinctrl-names = "default"; 1102 pinctrl-0 = <&main_mcan9_pins_default>; 1103 phys = <&transceiver4>; 1104 status = "okay"; 1105}; 1106 1107&ufs_wrapper { 1108 status = "disabled"; 1109}; 1110 1111&mailbox0_cluster0 { 1112 status = "okay"; 1113 interrupts = <436>; 1114 1115 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 1116 ti,mbox-rx = <0 0 0>; 1117 ti,mbox-tx = <1 0 0>; 1118 }; 1119 1120 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 1121 ti,mbox-rx = <2 0 0>; 1122 ti,mbox-tx = <3 0 0>; 1123 }; 1124}; 1125 1126&mailbox0_cluster1 { 1127 status = "okay"; 1128 interrupts = <432>; 1129 1130 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 1131 ti,mbox-rx = <0 0 0>; 1132 ti,mbox-tx = <1 0 0>; 1133 }; 1134 1135 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 1136 ti,mbox-rx = <2 0 0>; 1137 ti,mbox-tx = <3 0 0>; 1138 }; 1139}; 1140 1141&mailbox0_cluster2 { 1142 status = "okay"; 1143 interrupts = <428>; 1144 1145 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 1146 ti,mbox-rx = <0 0 0>; 1147 ti,mbox-tx = <1 0 0>; 1148 }; 1149 1150 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 1151 ti,mbox-rx = <2 0 0>; 1152 ti,mbox-tx = <3 0 0>; 1153 }; 1154}; 1155 1156&mailbox0_cluster3 { 1157 status = "okay"; 1158 interrupts = <424>; 1159 1160 mbox_c66_0: mbox-c66-0 { 1161 ti,mbox-rx = <0 0 0>; 1162 ti,mbox-tx = <1 0 0>; 1163 }; 1164 1165 mbox_c66_1: mbox-c66-1 { 1166 ti,mbox-rx = <2 0 0>; 1167 ti,mbox-tx = <3 0 0>; 1168 }; 1169}; 1170 1171&mailbox0_cluster4 { 1172 status = "okay"; 1173 interrupts = <420>; 1174 1175 mbox_c71_0: mbox-c71-0 { 1176 ti,mbox-rx = <0 0 0>; 1177 ti,mbox-tx = <1 0 0>; 1178 }; 1179}; 1180 1181&mcu_r5fss0_core0 { 1182 mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; 1183 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 1184 <&mcu_r5fss0_core0_memory_region>; 1185}; 1186 1187&mcu_r5fss0_core1 { 1188 mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; 1189 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 1190 <&mcu_r5fss0_core1_memory_region>; 1191}; 1192 1193&main_r5fss0_core0 { 1194 mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; 1195 memory-region = <&main_r5fss0_core0_dma_memory_region>, 1196 <&main_r5fss0_core0_memory_region>; 1197}; 1198 1199&main_r5fss0_core1 { 1200 mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; 1201 memory-region = <&main_r5fss0_core1_dma_memory_region>, 1202 <&main_r5fss0_core1_memory_region>; 1203}; 1204 1205&main_r5fss1_core0 { 1206 mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; 1207 memory-region = <&main_r5fss1_core0_dma_memory_region>, 1208 <&main_r5fss1_core0_memory_region>; 1209}; 1210 1211&main_r5fss1_core1 { 1212 mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; 1213 memory-region = <&main_r5fss1_core1_dma_memory_region>, 1214 <&main_r5fss1_core1_memory_region>; 1215}; 1216 1217&c66_0 { 1218 status = "okay"; 1219 mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; 1220 memory-region = <&c66_0_dma_memory_region>, 1221 <&c66_0_memory_region>; 1222}; 1223 1224&c66_1 { 1225 status = "okay"; 1226 mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; 1227 memory-region = <&c66_1_dma_memory_region>, 1228 <&c66_1_memory_region>; 1229}; 1230 1231&c71_0 { 1232 status = "okay"; 1233 mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; 1234 memory-region = <&c71_0_dma_memory_region>, 1235 <&c71_0_memory_region>; 1236}; 1237