| /kernel/linux/linux-6.6/arch/arm64/boot/dts/xilinx/ |
| D | zynqmp-zc1751-xm019-dc5.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm019-dc5 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
33 stdout-path = "serial0:115200n8";
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| D | zynqmp-sck-kv-g-revB.dtso | 1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16 /dts-v1/;
20 si5332_0: si5332-0 { /* u17 */
21 compatible = "fixed-clock";
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| /kernel/linux/linux-6.6/drivers/clk/renesas/ |
| D | rzg2l-cpg.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * Based on renesas-cpg-mssr.c
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/clk/renesas.h>
28 #include <linux/reset-controller.h>
32 #include <dt-bindings/clock/renesas-cpg-mssr.h>
34 #include "rzg2l-cpg.h"
64 * struct clk_hw_data - clock hardware data
66 * @conf: clock configuration (register offset, shift, width)
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| /kernel/linux/linux-5.10/drivers/memory/ |
| D | atmel-ebi.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
9 #include <linux/clk.h>
12 #include <linux/mfd/syscon/atmel-matrix.h>
13 #include <linux/mfd/syscon/atmel-smc.h>
17 #include <soc/at91/atmel-sfr.h>
41 struct atmel_ebi_dev_config *conf);
44 struct atmel_ebi_dev_config *conf);
46 struct atmel_ebi_dev_config *conf);
50 struct clk *clk; member
[all …]
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| /kernel/linux/linux-6.6/drivers/memory/ |
| D | atmel-ebi.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
9 #include <linux/clk.h>
12 #include <linux/mfd/syscon/atmel-matrix.h>
13 #include <linux/mfd/syscon/atmel-smc.h>
17 #include <soc/at91/atmel-sfr.h>
41 struct atmel_ebi_dev_config *conf);
44 struct atmel_ebi_dev_config *conf);
46 struct atmel_ebi_dev_config *conf);
50 struct clk *clk; member
[all …]
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| /kernel/linux/linux-5.10/drivers/spi/ |
| D | spi-meson-spicc.c | 7 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
30 * - all transfers are cutted in 16 words burst because the FIFO hangs on
31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
33 * - CS management is dumb, and goes UP between every burst, so is really a
69 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
72 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
89 #define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */
92 #define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */
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| /kernel/linux/linux-5.10/drivers/mfd/ |
| D | atmel-smc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
11 #include <linux/mfd/syscon/atmel-smc.h>
15 * atmel_smc_cs_conf_init - initialize a SMC CS conf
16 * @conf: the SMC CS conf to initialize
20 void atmel_smc_cs_conf_init(struct atmel_smc_cs_conf *conf) in atmel_smc_cs_conf_init() argument
22 memset(conf, 0, sizeof(*conf)); in atmel_smc_cs_conf_init()
27 * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
29 * @ncycles: number of MCK clk cycles
40 * If the @ncycles value is too big to be encoded, -ERANGE is returned and
[all …]
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| /kernel/linux/linux-6.6/drivers/mfd/ |
| D | atmel-smc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
11 #include <linux/mfd/syscon/atmel-smc.h>
15 * atmel_smc_cs_conf_init - initialize a SMC CS conf
16 * @conf: the SMC CS conf to initialize
20 void atmel_smc_cs_conf_init(struct atmel_smc_cs_conf *conf) in atmel_smc_cs_conf_init() argument
22 memset(conf, 0, sizeof(*conf)); in atmel_smc_cs_conf_init()
27 * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
29 * @ncycles: number of MCK clk cycles
40 * If the @ncycles value is too big to be encoded, -ERANGE is returned and
[all …]
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| /kernel/linux/linux-6.6/drivers/spi/ |
| D | spi-meson-spicc.c | 7 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
30 * - all transfers are cutted in 16 words burst because the FIFO hangs on
31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
33 * - CS management is dumb, and goes UP between every burst, so is really a
69 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
72 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
89 #define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */
92 #define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */
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| D | spi-ep93xx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Mika Westerberg
7 * Explicit FIFO handling code was inspired by amba-pl022 driver.
9 * Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
17 #include <linux/clk.h>
30 #include <linux/platform_data/dma-ep93xx.h>
31 #include <linux/platform_data/spi-ep93xx.h>
69 * struct ep93xx_spi - EP93xx SPI controller structure
70 * @clk: clock for the controller
75 * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp4/ |
| D | mdp4_lvds_pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
21 struct msm_drm_private *priv = lvds_pll->dev->dev_private; in get_kms()
22 return to_mdp4_kms(to_mdp_kms(priv->kms)); in get_kms()
30 } conf[32]; member
53 return &freqtbl[i-1]; in find_rate()
54 return &freqtbl[i-1]; in find_rate()
61 const struct pll_rate *pll_rate = find_rate(lvds_pll->pixclk); in mpd4_lvds_pll_enable()
64 DBG("pixclk=%lu (%lu)", lvds_pll->pixclk, pll_rate->rate); in mpd4_lvds_pll_enable()
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/mdp4/ |
| D | mdp4_lvds_pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
21 struct msm_drm_private *priv = lvds_pll->dev->dev_private; in get_kms()
22 return to_mdp4_kms(to_mdp_kms(priv->kms)); in get_kms()
30 } conf[32]; member
53 return &freqtbl[i-1]; in find_rate()
54 return &freqtbl[i-1]; in find_rate()
61 const struct pll_rate *pll_rate = find_rate(lvds_pll->pixclk); in mpd4_lvds_pll_enable()
64 DBG("pixclk=%lu (%lu)", lvds_pll->pixclk, pll_rate->rate); in mpd4_lvds_pll_enable()
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/ |
| D | mt7622-rfb1.dts | 6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
18 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
25 stdout-path = "serial0:115200n8";
31 proc-supply = <&mt6380_vcpu_reg>;
32 sram-supply = <&mt6380_vm_reg>;
36 proc-supply = <&mt6380_vcpu_reg>;
37 sram-supply = <&mt6380_vm_reg>;
[all …]
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| D | mt7622-bananapi-bpi-r64.dts | 5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
16 model = "Bananapi BPI-R64";
17 compatible = "bananapi,bpi-r64", "mediatek,mt7622";
24 stdout-path = "serial0:115200n8";
30 proc-supply = <&mt6380_vcpu_reg>;
31 sram-supply = <&mt6380_vm_reg>;
35 proc-supply = <&mt6380_vcpu_reg>;
[all …]
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| /kernel/linux/linux-5.10/sound/soc/jz4740/ |
| D | jz4740-i2s.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
15 #include <linux/clk.h>
18 #include <linux/dma-mapping.h>
27 #include "jz4740-i2s.h"
107 struct clk *clk_aic;
108 struct clk *clk_i2s;
119 return readl(i2s->base + reg); in jz4740_i2s_read()
125 writel(value, i2s->base + reg); in jz4740_i2s_write()
140 uint32_t conf; in jz4740_i2s_startup() local
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/mediatek/ |
| D | mt7622-rfb1.dts | 6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
18 chassis-type = "embedded";
19 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
32 proc-supply = <&mt6380_vcpu_reg>;
33 sram-supply = <&mt6380_vm_reg>;
37 proc-supply = <&mt6380_vcpu_reg>;
[all …]
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| D | mt7622-bananapi-bpi-r64.dts | 5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
17 model = "Bananapi BPI-R64";
18 chassis-type = "embedded";
19 compatible = "bananapi,bpi-r64", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
32 proc-supply = <&mt6380_vcpu_reg>;
[all …]
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| /kernel/linux/linux-5.10/drivers/pinctrl/ |
| D | pinctrl-at91-pio4.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <linux/clk.h>
18 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-utils.h"
93 * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
95 * @clk: clock of the controller.
116 struct clk *clk; member
141 {"atmel,drive-strength", ATMEL_PIN_CONFIG_DRIVE_STRENGTH, 0},
144 /* --- GPIO --- */
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| /kernel/linux/linux-6.6/drivers/clk/ |
| D | clk-sparx5.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/microchip,sparx5.h>
59 const struct s5_pll_conf *conf) in s5_calc_freq() argument
61 unsigned long rate = parent_rate / conf->div; in s5_calc_freq()
63 if (conf->rot_ena) { in s5_calc_freq()
64 int sign = conf->rot_dir ? -1 : 1; in s5_calc_freq()
65 int divt = sel_rates[conf->rot_sel] * (1 + conf->pre_div); in s5_calc_freq()
78 struct s5_pll_conf *conf) in s5_search_fractional() argument
84 memset(conf, 0, sizeof(*conf)); in s5_search_fractional()
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| D | clk-lochnagar.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2017-2018 Cirrus Logic, Inc. and
11 #include <linux/clk-provider.h>
22 #include <dt-bindings/clock/lochnagar.h>
49 LN_PARENT("ln-none"),
50 LN_PARENT("ln-spdif-mclk"),
51 LN_PARENT("ln-psia1-mclk"),
52 LN_PARENT("ln-psia2-mclk"),
53 LN_PARENT("ln-cdc-clkout"),
54 LN_PARENT("ln-dsp-clkout"),
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/ |
| D | clk-sparx5.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/microchip,sparx5.h>
59 const struct s5_pll_conf *conf) in s5_calc_freq() argument
61 unsigned long rate = parent_rate / conf->div; in s5_calc_freq()
63 if (conf->rot_ena) { in s5_calc_freq()
64 int sign = conf->rot_dir ? -1 : 1; in s5_calc_freq()
65 int divt = sel_rates[conf->rot_sel] * (1 + conf->pre_div); in s5_calc_freq()
78 struct s5_pll_conf *conf) in s5_search_fractional() argument
84 memset(conf, 0, sizeof(*conf)); in s5_search_fractional()
[all …]
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| D | clk-lochnagar.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2017-2018 Cirrus Logic, Inc. and
11 #include <linux/clk-provider.h>
22 #include <dt-bindings/clk/lochnagar.h>
49 LN_PARENT("ln-none"),
50 LN_PARENT("ln-spdif-mclk"),
51 LN_PARENT("ln-psia1-mclk"),
52 LN_PARENT("ln-psia2-mclk"),
53 LN_PARENT("ln-cdc-clkout"),
54 LN_PARENT("ln-dsp-clkout"),
[all …]
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| /kernel/linux/linux-5.10/drivers/pci/controller/ |
| D | pci-mvebu.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 #include <linux/clk.h>
24 #include "../pci-bridge-emul.h"
36 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
96 struct clk *clk; member
110 writel(val, port->base + reg); in mvebu_writel()
115 return readl(port->base + reg); in mvebu_readl()
120 return port->io_target != -1 && port->io_attr != -1; in mvebu_has_ioport()
150 * BAR[0] -> internal registers (needed for MSI)
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| /kernel/linux/linux-5.10/drivers/pinctrl/cirrus/ |
| D | pinctrl-madera-core.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016-2018 Cirrus Logic
17 #include <linux/pinctrl/pinconf-generic.h>
22 #include "../pinctrl-utils.h"
24 #include "pinctrl-madera.h"
28 * NOTE: IDs are zero-indexed for coding convenience
74 * All single-pin functions can be mapped to any GPIO, however pinmux applies
78 * Since these do not correspond to anything in the actual hardware - they are
79 * merely an adaptation to pinctrl's view of the world - we use the same name
91 /* set of pin numbers for single-pin groups, zero-indexed */
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| /kernel/linux/linux-6.6/drivers/pinctrl/cirrus/ |
| D | pinctrl-madera-core.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016-2018 Cirrus Logic
17 #include <linux/pinctrl/pinconf-generic.h>
25 #include "../pinctrl-utils.h"
27 #include "pinctrl-madera.h"
31 * NOTE: IDs are zero-indexed for coding convenience
77 * All single-pin functions can be mapped to any GPIO, however pinmux applies
81 * Since these do not correspond to anything in the actual hardware - they are
82 * merely an adaptation to pinctrl's view of the world - we use the same name
94 /* set of pin numbers for single-pin groups, zero-indexed */
[all …]
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