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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/iommu/
Drockchip,iommu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
23 - rockchip,iommu
24 - rockchip,rk3568-iommu
28 - description: configuration registers for MMU instance 0
29 - description: configuration registers for MMU instance 1
34 - description: interruption for MMU instance 0
35 - description: interruption for MMU instance 1
[all …]
/kernel/linux/linux-5.10/arch/arc/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
72 config MMU config
96 source "arch/arc/plat-tb10x/Kconfig"
97 source "arch/arc/plat-axs10x/Kconfig"
98 source "arch/arc/plat-hsdk/Kconfig"
116 ISA for the Next Generation ARC-HS cores
141 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
142 Shared Address Spaces (for sharing TLB entries in MMU)
143 -Caches: New Prog Model, Region Flush
[all …]
/kernel/linux/linux-6.6/arch/arc/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
30 select GENERIC_STRNCPY_FROM_USER if MMU
31 select GENERIC_STRNLEN_USER if MMU
68 config MMU config
88 source "arch/arc/plat-tb10x/Kconfig"
89 source "arch/arc/plat-axs10x/Kconfig"
90 source "arch/arc/plat-hsdk/Kconfig"
108 ISA for the Next Generation ARC-HS cores
126 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iommu/
Drockchip,iommu.txt9 - compatible : Should be "rockchip,iommu"
10 - reg : Address space for the configuration registers
11 - interrupts : Interrupt specifier for the IOMMU instance
12 - interrupt-names : Interrupt name for the IOMMU instance
13 - #iommu-cells : Should be <0>. This indicates the iommu is a
14 "single-master" device, and needs no additional information
17 - clocks : A list of clocks required for the IOMMU to be accessible by
19 - clock-names : Should contain the following:
20 "iface" - Main peripheral bus clock (PCLK/HCL) (required)
21 "aclk" - AXI bus clock (required)
[all …]
/kernel/linux/linux-5.10/arch/riscv/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
20 select ARCH_HAS_DEBUG_VIRTUAL if MMU
30 select ARCH_HAS_STRICT_KERNEL_RWX if MMU
33 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
37 select CLINT_TIMER if !MMU
49 select GENERIC_PTDUMP if MMU
52 select GENERIC_STRNCPY_FROM_USER if MMU
53 select GENERIC_STRNLEN_USER if MMU
54 select GENERIC_TIME_VSYSCALL if MMU && 64BIT
[all …]
/kernel/linux/linux-6.6/arch/xtensa/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_HAS_BINFMT_FLAT if !MMU
8 select ARCH_HAS_DMA_PREP_COHERENT if MMU
11 select ARCH_HAS_SYNC_DMA_FOR_CPU if MMU
12 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if MMU
13 select ARCH_HAS_DMA_SET_UNCACHED if MMU
23 select DMA_NONCOHERENT_MMAP if MMU
31 select GENERIC_IOREMAP if MMU
34 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
58 Xtensa processors are 32-bit RISC machines designed by Tensilica
[all …]
/kernel/linux/linux-5.10/arch/powerpc/include/asm/
Dreg_booke.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * specification. Notice that while the IBM-40x series of CPUs
9 * Copyright 2009-2010 Freescale Semiconductor, Inc.
15 #include <asm/ppc-opcode.h>
19 #define MSR_UCLE_LG 26 /* User-mode cache lock enable */
26 #define MSR_CM_LG 31 /* Computation Mode (0=32-bit, 1=64-bit) */
75 #define SPRN_MAS8 0x155 /* MMU Assist Register 8 */
78 #define SPRN_MAS5_MAS6 0x15c /* MMU Assist Register 5 || 6 */
79 #define SPRN_MAS8_MAS1 0x15d /* MMU Assist Register 8 || 1 */
85 #define SPRN_MAS7_MAS3 0x174 /* MMU Assist Register 7 || 3 */
[all …]
/kernel/linux/linux-6.6/arch/powerpc/include/asm/
Dreg_booke.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * specification. Notice that while the IBM-40x series of CPUs
9 * Copyright 2009-2010 Freescale Semiconductor, Inc.
15 #include <asm/ppc-opcode.h>
19 #define MSR_UCLE_LG 26 /* User-mode cache lock enable */
26 #define MSR_CM_LG 31 /* Computation Mode (0=32-bit, 1=64-bit) */
75 #define SPRN_MAS8 0x155 /* MMU Assist Register 8 */
78 #define SPRN_MAS5_MAS6 0x15c /* MMU Assist Register 5 || 6 */
79 #define SPRN_MAS8_MAS1 0x15d /* MMU Assist Register 8 || 1 */
85 #define SPRN_MAS7_MAS3 0x174 /* MMU Assist Register 7 || 3 */
[all …]
/kernel/linux/linux-6.6/arch/arm64/kernel/
Dhyp-stub.S1 /* SPDX-License-Identifier: GPL-2.0-only */
35 ventry elx_sync // Synchronous 64-bit EL1
36 ventry el1_irq_invalid // IRQ 64-bit EL1
37 ventry el1_fiq_invalid // FIQ 64-bit EL1
38 ventry el1_error_invalid // Error 64-bit EL1
40 ventry el1_sync_invalid // Synchronous 32-bit EL1
41 ventry el1_irq_invalid // IRQ 32-bit EL1
42 ventry el1_fiq_invalid // FIQ 32-bit EL1
43 ventry el1_error_invalid // Error 32-bit EL1
66 beq 9f // Nothing to reset!
[all …]
/kernel/linux/linux-6.6/drivers/iommu/arm/arm-smmu/
Darm-smmu-impl.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #define pr_fmt(fmt) "arm-smmu: " fmt
10 #include "arm-smmu.h"
44 /* Since we don't care for sGFAR, we can do without 64-bit accessors */
65 cs->id_base = atomic_fetch_add(smmu->num_context_banks, &context_count); in cavium_cfg_probe()
66 dev_notice(smmu->dev, "\tenabling workaround for Cavium erratum 27704\n"); in cavium_cfg_probe()
74 struct cavium_smmu *cs = container_of(smmu_domain->smmu, in cavium_init_context()
77 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S2) in cavium_init_context()
78 smmu_domain->cfg.vmid += cs->id_base; in cavium_init_context()
80 smmu_domain->cfg.asid += cs->id_base; in cavium_init_context()
[all …]
/kernel/linux/linux-6.6/sound/pci/aw2/
Daw2-saa7146.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Jean-Christian Hassler <jhassler@free.fr>
24 #include "aw2-saa7146.h"
26 #include "aw2-tsl.c"
28 #define WRITEREG(value, addr) writel((value), chip->base_addr + (addr))
29 #define READREG(addr) readl(chip->base_addr + (addr))
38 /* chip-specific destructor */
41 /* disable all irqs */ in snd_aw2_saa7146_free()
44 /* reset saa7146 */ in snd_aw2_saa7146_free()
48 chip->base_addr = NULL; in snd_aw2_saa7146_free()
[all …]
/kernel/linux/linux-5.10/sound/pci/aw2/
Daw2-saa7146.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Jean-Christian Hassler <jhassler@free.fr>
24 #include "aw2-saa7146.h"
26 #include "aw2-tsl.c"
28 #define WRITEREG(value, addr) writel((value), chip->base_addr + (addr))
29 #define READREG(addr) readl(chip->base_addr + (addr))
38 /* chip-specific destructor */
41 /* disable all irqs */ in snd_aw2_saa7146_free()
44 /* reset saa7146 */ in snd_aw2_saa7146_free()
48 chip->base_addr = NULL; in snd_aw2_saa7146_free()
[all …]
/kernel/liteos_a/arch/arm/arm/src/startup/
Dreset_vector_up.S2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
61 .fpu neon-vfpv4
63 .arch armv7-a
86 *Assumption: ROM code has these vectors at the hardware reset address.
87 *A simple jump removes any address-space dependencies [i.e. safer]
102 /* do some early cpu setup: i/d cache disable, mmu disabled */
106 bic r0, #(1 << 0) /* mmu */
156 bl memset_optimized /* optimized memset since r0 is 64-byte aligned */
161 …ldmia r5!, {r6-r10} /* r6 = phys, r7 = virt, r8 = size, r9 = mmu_flags, r1…
[all …]
Dreset_vector_mp.S2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
63 .fpu neon-vfpv4
65 .arch armv7-a
89 *Assumption: ROM code has these vectors at the hardware reset address.
90 *A simple jump removes any address-space dependencies [i.e. safer]
122 /* do some early cpu setup: i/d cache disable, mmu disabled */
126 bic r0, #(1 << 0) /* mmu */
181 bl memset_optimized /* optimized memset since r0 is 64-byte aligned */
186 …ldmia r5!, {r6-r10} /* r6 = phys, r7 = virt, r8 = size, r9 = mmu_flags, r1…
[all …]
/kernel/linux/linux-5.10/arch/arm/mm/
Dproc-sa110.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-sa110.S
5 * Copyright (C) 1997-2002 Russell King
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
8 * MMU functions for SA110
11 * functions on the StrongARM-110.
17 #include <asm/asm-offsets.h>
20 #include <asm/pgtable-hwdef.h>
23 #include "proc-macros.S"
45 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
[all …]
Dproc-sa1100.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-sa1100.S
5 * Copyright (C) 1997-2002 Russell King
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
8 * MMU functions for SA110
11 * functions on the StrongARM-1100 and StrongARM-1110.
15 * 12-jun-2000, Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
22 #include <asm/asm-offsets.h>
25 #include <asm/pgtable-hwdef.h>
27 #include "proc-macros.S"
[all …]
Dproc-v6.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v6.S
14 #include <asm/asm-offsets.h>
16 #include <asm/pgtable-hwdef.h>
18 #include "proc-macros.S"
42 mcr p15, 0, r0, c1, c0, 0 @ disable caches
48 * Perform a soft reset of the system. Put the CPU into the
49 * same state as it would be if it had been reset, and branch
50 * to what would be the reset vector.
52 * - loc - location to jump to for soft reset
[all …]
/kernel/linux/linux-6.6/arch/arm/mm/
Dproc-sa110.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-sa110.S
5 * Copyright (C) 1997-2002 Russell King
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
8 * MMU functions for SA110
11 * functions on the StrongARM-110.
17 #include <asm/asm-offsets.h>
20 #include <asm/pgtable-hwdef.h>
23 #include "proc-macros.S"
45 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
[all …]
Dproc-sa1100.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-sa1100.S
5 * Copyright (C) 1997-2002 Russell King
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
8 * MMU functions for SA110
11 * functions on the StrongARM-1100 and StrongARM-1110.
15 * 12-jun-2000, Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
22 #include <asm/asm-offsets.h>
25 #include <asm/pgtable-hwdef.h>
27 #include "proc-macros.S"
[all …]
/kernel/linux/linux-6.6/Documentation/ABI/testing/
Ddebugfs-driver-habanalabs46 the generic Linux user-space PCI mapping) because the DDR bar
61 the generic Linux user-space PCI mapping) because the DDR bar
77 Linux user-space PCI mapping) because the amount of internal
91 Valid values are "disable", "enable", "suspend", "resume".
99 certain error cases, after which the device is reset.
212 What: /sys/kernel/debug/habanalabs/hl<n>/mmu
220 echo "1 0x1000" > /sys/kernel/debug/habanalabs/hl0/mmu
226 Description: Check and display page fault or access violation mmu errors for
228 e.g. to display error info for MMU hw cap bit 9, you need to do:
241 Linux user-space PCI mapping) because this space is protected
[all …]
/kernel/linux/linux-6.6/Documentation/virt/kvm/arm/
Dhyp-abi.rst1 .. SPDX-License-Identifier: GPL-2.0
11 hypervisor), or any hypervisor-specific interaction when the kernel is
20 mode, but still needs to interact with it, allowing a built-in
28 Unless specified otherwise, any built-in hypervisor must implement
45 Turn HYP/EL2 MMU off, and reset HVBAR/VBAR_EL2 to the initials
57 Mask all exceptions, disable the MMU, clear I+D bits, move the arguments
65 Finish configuring EL2 depending on the command-line options,
68 supporting VHE, the EL2 MMU being off, and VHE not being disabled by
71 Any other value of r0/x0 triggers a hypervisor-specific handling,
76 clobber any of the caller-saved registers (x0-x18 on arm64, r0-r3 and
/kernel/linux/linux-5.10/arch/arm/mach-tegra/
Dsleep-tegra20.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
15 #include <asm/proc-fns.h>
20 #include "reset.h"
64 * puts the current cpu in reset
77 * r0 is cpu to reset
79 * puts the specified CPU in wait-for-event mode on the flow controller
80 * and puts the CPU in reset
85 * corrupts r0-r3, r12
101 str r1, [r3, #0x340] @ put slave CPU in reset
[all …]
Dpm.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
29 #include <asm/proc-fns.h>
36 #include "reset.h"
141 if (tegra_cpu_car_ops->rail_off_ready && in tegra_sleep_cpu()
143 return -EBUSY; in tegra_sleep_cpu()
148 * MMU-on if cache maintenance is done via Trusted Foundations in tegra_sleep_cpu()
150 * if any of secondary CPU's is online and this is the LP2-idle in tegra_sleep_cpu()
151 * code-path only for Tegra20/30. in tegra_sleep_cpu()
154 if (trusted_foundations_registered() && outer_cache.disable) in tegra_sleep_cpu()
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-tegra/
Dpm.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
29 #include <asm/proc-fns.h>
36 #include "reset.h"
141 if (tegra_cpu_car_ops->rail_off_ready && in tegra_sleep_cpu()
143 return -EBUSY; in tegra_sleep_cpu()
148 * MMU-on if cache maintenance is done via Trusted Foundations in tegra_sleep_cpu()
150 * if any of secondary CPU's is online and this is the LP2-idle in tegra_sleep_cpu()
151 * code-path only for Tegra20/30. in tegra_sleep_cpu()
154 if (trusted_foundations_registered() && outer_cache.disable) in tegra_sleep_cpu()
[all …]
Dsleep-tegra20.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
15 #include <asm/proc-fns.h>
20 #include "reset.h"
50 .arch armv7-a
89 * puts the current cpu in reset
102 * r0 is cpu to reset
104 * puts the specified CPU in wait-for-event mode on the flow controller
105 * and puts the CPU in reset
110 * corrupts r0-r3, r12
[all …]

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