| /kernel/linux/linux-6.6/drivers/gpio/ |
| D | gpio-rda.c | 1 // SPDX-License-Identifier: GPL-2.0-only
44 static inline void rda_gpio_update(struct gpio_chip *chip, unsigned int offset, in rda_gpio_update() argument
48 void __iomem *base = rda_gpio->base; in rda_gpio_update()
52 spin_lock_irqsave(&rda_gpio->lock, flags); in rda_gpio_update()
56 tmp |= BIT(offset); in rda_gpio_update()
58 tmp &= ~BIT(offset); in rda_gpio_update()
61 spin_unlock_irqrestore(&rda_gpio->lock, flags); in rda_gpio_update()
68 void __iomem *base = rda_gpio->base; in rda_gpio_irq_mask()
69 u32 offset = irqd_to_hwirq(data); in rda_gpio_irq_mask() local
72 value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT; in rda_gpio_irq_mask()
[all …]
|
| D | gpio-sa1100.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-sa1100/gpio.c
5 * Generic SA-1100 GPIO handling
40 static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset) in sa1100_gpio_get() argument
42 return readl_relaxed(sa1100_gpio_chip(chip)->membase + R_GPLR) & in sa1100_gpio_get()
43 BIT(offset); in sa1100_gpio_get()
46 static void sa1100_gpio_set(struct gpio_chip *chip, unsigned offset, int value) in sa1100_gpio_set() argument
50 writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg); in sa1100_gpio_set()
53 static int sa1100_get_direction(struct gpio_chip *chip, unsigned offset) in sa1100_get_direction() argument
55 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; in sa1100_get_direction()
[all …]
|
| D | gpio-pl061.c | 1 // SPDX-License-Identifier: GPL-2.0-only
63 static int pl061_get_direction(struct gpio_chip *gc, unsigned offset) in pl061_get_direction() argument
67 if (readb(pl061->base + GPIODIR) & BIT(offset)) in pl061_get_direction()
73 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) in pl061_direction_input() argument
79 raw_spin_lock_irqsave(&pl061->lock, flags); in pl061_direction_input()
80 gpiodir = readb(pl061->base + GPIODIR); in pl061_direction_input()
81 gpiodir &= ~(BIT(offset)); in pl061_direction_input()
82 writeb(gpiodir, pl061->base + GPIODIR); in pl061_direction_input()
83 raw_spin_unlock_irqrestore(&pl061->lock, flags); in pl061_direction_input()
88 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset, in pl061_direction_output() argument
[all …]
|
| D | gpio-mxc.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
86 .edge_sel_reg = -EINVAL,
101 .edge_sel_reg = -EINVAL,
123 #define GPIO_DR (port->hwdata->dr_reg)
124 #define GPIO_GDIR (port->hwdata->gdir_reg)
125 #define GPIO_PSR (port->hwdata->psr_reg)
126 #define GPIO_ICR1 (port->hwdata->icr1_reg)
127 #define GPIO_ICR2 (port->hwdata->icr2_reg)
128 #define GPIO_IMR (port->hwdata->imr_reg)
[all …]
|
| D | gpio-tqmx86.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * TQ-Systems TQMx86 PLD GPIO driver
23 #define TQMX86_NGPO 4 /* 0-3 - output */
24 #define TQMX86_NGPI 4 /* 4-7 - input */
25 #define TQMX86_DIR_INPUT_MASK 0xf0 /* 0-3 - output, 4-7 - input */
56 return ioread8(gd->io_base + reg); in tqmx86_gpio_read()
62 iowrite8(val, gd->io_base + reg); in tqmx86_gpio_write()
65 static int tqmx86_gpio_get(struct gpio_chip *chip, unsigned int offset) in tqmx86_gpio_get() argument
69 return !!(tqmx86_gpio_read(gpio, TQMX86_GPIOD) & BIT(offset)); in tqmx86_gpio_get()
72 static void tqmx86_gpio_set(struct gpio_chip *chip, unsigned int offset, in tqmx86_gpio_set() argument
[all …]
|
| D | gpio-mxs.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
25 #define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
26 #define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
27 #define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
28 #define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
29 #define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
30 #define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
31 #define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
32 #define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
[all …]
|
| D | gpio-stmpe.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2010
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
41 static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset) in stmpe_gpio_get() argument
44 struct stmpe *stmpe = stmpe_gpio->stmpe; in stmpe_gpio_get()
45 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)]; in stmpe_gpio_get()
46 u8 mask = BIT(offset % 8); in stmpe_gpio_get()
56 static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val) in stmpe_gpio_set() argument
59 struct stmpe *stmpe = stmpe_gpio->stmpe; in stmpe_gpio_set()
61 u8 reg = stmpe->regs[which + (offset / 8)]; in stmpe_gpio_set()
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpio/ |
| D | gpio-rda.c | 1 // SPDX-License-Identifier: GPL-2.0-only
45 static inline void rda_gpio_update(struct gpio_chip *chip, unsigned int offset, in rda_gpio_update() argument
49 void __iomem *base = rda_gpio->base; in rda_gpio_update()
53 spin_lock_irqsave(&rda_gpio->lock, flags); in rda_gpio_update()
57 tmp |= BIT(offset); in rda_gpio_update()
59 tmp &= ~BIT(offset); in rda_gpio_update()
62 spin_unlock_irqrestore(&rda_gpio->lock, flags); in rda_gpio_update()
69 void __iomem *base = rda_gpio->base; in rda_gpio_irq_mask()
70 u32 offset = irqd_to_hwirq(data); in rda_gpio_irq_mask() local
73 value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT; in rda_gpio_irq_mask()
[all …]
|
| D | gpio-sa1100.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-sa1100/gpio.c
5 * Generic SA-1100 GPIO handling
39 static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset) in sa1100_gpio_get() argument
41 return readl_relaxed(sa1100_gpio_chip(chip)->membase + R_GPLR) & in sa1100_gpio_get()
42 BIT(offset); in sa1100_gpio_get()
45 static void sa1100_gpio_set(struct gpio_chip *chip, unsigned offset, int value) in sa1100_gpio_set() argument
49 writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg); in sa1100_gpio_set()
52 static int sa1100_get_direction(struct gpio_chip *chip, unsigned offset) in sa1100_get_direction() argument
54 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; in sa1100_get_direction()
[all …]
|
| D | gpio-intel-mid.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2008-2014,2016 Intel Corporation.
33 * structure, to get a bit offset for a pin (use GPDR as an example):
36 * reg = offset / 32;
37 * bit = offset % 32;
40 * so the bit of reg_addr is to control pin offset's GPDR feature
44 GPLR = 0, /* pin level read-only */
48 GRER, /* rising edge detect */
49 GFER, /* falling edge detect */
50 GEDR, /* edge detect result */
[all …]
|
| D | gpio-pl061.c | 1 // SPDX-License-Identifier: GPL-2.0-only
63 static int pl061_get_direction(struct gpio_chip *gc, unsigned offset) in pl061_get_direction() argument
67 if (readb(pl061->base + GPIODIR) & BIT(offset)) in pl061_get_direction()
73 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) in pl061_direction_input() argument
79 raw_spin_lock_irqsave(&pl061->lock, flags); in pl061_direction_input()
80 gpiodir = readb(pl061->base + GPIODIR); in pl061_direction_input()
81 gpiodir &= ~(BIT(offset)); in pl061_direction_input()
82 writeb(gpiodir, pl061->base + GPIODIR); in pl061_direction_input()
83 raw_spin_unlock_irqrestore(&pl061->lock, flags); in pl061_direction_input()
88 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset, in pl061_direction_output() argument
[all …]
|
| D | gpio-mxs.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
26 #define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
27 #define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
28 #define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
29 #define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
30 #define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
31 #define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
32 #define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
33 #define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
[all …]
|
| D | gpio-stmpe.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2010
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
41 static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset) in stmpe_gpio_get() argument
44 struct stmpe *stmpe = stmpe_gpio->stmpe; in stmpe_gpio_get()
45 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)]; in stmpe_gpio_get()
46 u8 mask = BIT(offset % 8); in stmpe_gpio_get()
56 static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val) in stmpe_gpio_set() argument
59 struct stmpe *stmpe = stmpe_gpio->stmpe; in stmpe_gpio_set()
61 u8 reg = stmpe->regs[which + (offset / 8)]; in stmpe_gpio_set()
[all …]
|
| /kernel/linux/linux-5.10/fs/btrfs/ |
| D | backref.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include "disk-io.h"
14 #include "delayed-ref.h"
23 u64 offset; member
34 u64 offset = 0; in check_extent_in_eb() local
50 offset = extent_item_pos - data_offset; in check_extent_in_eb()
55 return -ENOMEM; in check_extent_in_eb()
57 e->next = *eie; in check_extent_in_eb()
58 e->inum = key->objectid; in check_extent_in_eb()
59 e->offset = key->offset + offset; in check_extent_in_eb()
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/ast/ |
| D | ast_dp501.c | 1 // SPDX-License-Identifier: GPL-2.0
15 release_firmware(ast->dp501_fw); in ast_release_firmware()
16 ast->dp501_fw = NULL; in ast_release_firmware()
24 ret = request_firmware(&ast->dp501_fw, "ast_dp501_fw.bin", dev->dev); in ast_load_dp501_microcode()
28 return devm_add_action_or_reset(dev->dev, ast_release_firmware, ast); in ast_load_dp501_microcode()
192 if (ast->config_mode != ast_use_p2a) in ast_backup_fw()
213 if (ast->config_mode != ast_use_p2a) in ast_launch_m68k()
219 if (ast->dp501_fw_addr) { in ast_launch_m68k()
220 fw_addr = ast->dp501_fw_addr; in ast_launch_m68k()
223 if (!ast->dp501_fw && in ast_launch_m68k()
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/ast/ |
| D | ast_dp501.c | 1 // SPDX-License-Identifier: GPL-2.0
15 release_firmware(ast->dp501_fw); in ast_release_firmware()
16 ast->dp501_fw = NULL; in ast_release_firmware()
24 ret = request_firmware(&ast->dp501_fw, "ast_dp501_fw.bin", dev->dev); in ast_load_dp501_microcode()
28 return devm_add_action_or_reset(dev->dev, ast_release_firmware, ast); in ast_load_dp501_microcode()
192 if (ast->config_mode != ast_use_p2a) in ast_backup_fw()
213 if (ast->config_mode != ast_use_p2a) in ast_launch_m68k()
219 if (ast->dp501_fw_addr) { in ast_launch_m68k()
220 fw_addr = ast->dp501_fw_addr; in ast_launch_m68k()
223 if (!ast->dp501_fw && in ast_launch_m68k()
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/remoteproc/ |
| D | qcom,sc7280-mss-pil.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-mss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sibi Sankar <quic_sibis@quicinc.com>
19 - qcom,sc7280-mss-pil
23 - description: MSS QDSP6 registers
24 - description: RMB registers
26 reg-names:
28 - const: qdsp6
[all …]
|
| D | qcom,msm8996-mss-pil.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,msm8996-mss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Sibi Sankar <quic_sibis@quicinc.com>
20 - qcom,msm8996-mss-pil
21 - qcom,msm8998-mss-pil
22 - qcom,sdm660-mss-pil
23 - qcom,sdm845-mss-pil
[all …]
|
| /kernel/linux/linux-6.6/drivers/media/rc/ |
| D | serial_ir.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * serial_ir - Device driver that records pulse- and pause-lengths
6 * (space-lengths) between DDCD event on a serial port.
8 * Copyright (C) 1996,97 Ralph Metzler <rjkm@thp.uni-koeln.de>
13 * Copyright (C) 2016 Sean Young <sean@mess.org> (port to rc-core)
27 #include <media/rc-core.h>
36 void (*send_pulse)(unsigned int length, ktime_t edge);
55 static int sense = -1; /* -1 = auto, 0 = active high, 1 = active low */
59 static void send_pulse_irdeo(unsigned int length, ktime_t edge);
62 static void send_pulse_homebrew(unsigned int length, ktime_t edge);
[all …]
|
| /kernel/linux/linux-5.10/drivers/media/rc/ |
| D | serial_ir.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * serial_ir - Device driver that records pulse- and pause-lengths
6 * (space-lengths) between DDCD event on a serial port.
8 * Copyright (C) 1996,97 Ralph Metzler <rjkm@thp.uni-koeln.de>
13 * Copyright (C) 2016 Sean Young <sean@mess.org> (port to rc-core)
27 #include <media/rc-core.h>
36 void (*send_pulse)(unsigned int length, ktime_t edge);
55 static int sense = -1; /* -1 = auto, 0 = active high, 1 = active low */
59 static void send_pulse_irdeo(unsigned int length, ktime_t edge);
62 static void send_pulse_homebrew(unsigned int length, ktime_t edge);
[all …]
|
| /kernel/linux/linux-5.10/drivers/pinctrl/ |
| D | pinctrl-at91.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Parallel I/O Controller (PIO) - System peripherals registers.
29 #define PIO_MDER 0x50 /* Multi-driver Enable Register */
30 #define PIO_MDDR 0x54 /* Multi-driver Disable Register */
31 #define PIO_MDSR 0x58 /* Multi-driver Status Register */
32 #define PIO_PUDR 0x60 /* Pull-up Disable Register */
33 #define PIO_PUER 0x64 /* Pull-up Enable Register */
34 #define PIO_PUSR 0x68 /* Pull-up Status Register */
45 #define PIO_PPDDR 0x90 /* Pad Pull-down Disable Register */
46 #define PIO_PPDER 0x94 /* Pad Pull-down Enable Register */
[all …]
|
| /kernel/linux/linux-6.6/drivers/pinctrl/ |
| D | pinctrl-at91.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Parallel I/O Controller (PIO) - System peripherals registers.
29 #define PIO_MDER 0x50 /* Multi-driver Enable Register */
30 #define PIO_MDDR 0x54 /* Multi-driver Disable Register */
31 #define PIO_MDSR 0x58 /* Multi-driver Status Register */
32 #define PIO_PUDR 0x60 /* Pull-up Disable Register */
33 #define PIO_PUER 0x64 /* Pull-up Enable Register */
34 #define PIO_PUSR 0x68 /* Pull-up Status Register */
45 #define PIO_PPDDR 0x90 /* Pad Pull-down Disable Register */
46 #define PIO_PPDER 0x94 /* Pad Pull-down Enable Register */
[all …]
|
| /kernel/linux/linux-6.6/fs/btrfs/ |
| D | backref.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include "disk-io.h"
14 #include "delayed-ref.h"
17 #include "tree-mod-log.h"
20 #include "extent-tree.h"
22 #include "tree-checker.h"
30 u64 offset; member
42 u64 offset = key->offset; in check_extent_in_eb() local
48 if (!ctx->ignore_extent_item_pos && in check_extent_in_eb()
56 if (ctx->extent_item_pos < data_offset || in check_extent_in_eb()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/virt/kvm/devices/ |
| D | mpic.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_FSL_MPIC_20 Freescale MPIC v2.0
10 - KVM_DEV_TYPE_FSL_MPIC_42 Freescale MPIC v4.2
20 KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
25 KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)
27 "attr" is the byte offset into the MPIC register space. Accesses
28 must be 4-byte aligned.
33 KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)
37 For edge-triggered interrupts: Writing 1 is considered an activating
38 edge, and writing 0 is ignored. Reading returns 1 if a previously
[all …]
|
| /kernel/linux/linux-6.6/Documentation/virt/kvm/devices/ |
| D | mpic.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_FSL_MPIC_20 Freescale MPIC v2.0
10 - KVM_DEV_TYPE_FSL_MPIC_42 Freescale MPIC v4.2
20 KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
25 KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)
27 "attr" is the byte offset into the MPIC register space. Accesses
28 must be 4-byte aligned.
33 KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)
37 For edge-triggered interrupts: Writing 1 is considered an activating
38 edge, and writing 0 is ignored. Reading returns 1 if a previously
[all …]
|