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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/gpio/
Dsprd,gpio-eic.yaml5 $id: http://devicetree.org/schemas/gpio/sprd,gpio-eic.yaml#
8 title: Unisoc EIC controller
16 The EIC is the abbreviation of external interrupt controller, which can
17 be used only in input mode. The Spreadtrum platform has 2 EIC controllers,
18 one is in digital chip, and another one is in PMIC. The digital chip EIC
19 controller contains 4 sub-modules, i.e. EIC-debounce, EIC-latch, EIC-async and
20 EIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub-
23 The EIC-debounce sub-module provides up to 8 source input signal
32 The EIC-latch sub-module is used to latch some special power down signals
33 and generate interrupts, since the EIC-latch does not depend on the APB
[all …]
/kernel/linux/linux-6.6/drivers/irqchip/
Dirq-mchp-eic.c28 * struct mchp_eic - EIC private data structure
32 * @irqs: irqs b/w eic and gic
45 static struct mchp_eic *eic; variable
51 tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_mask()
53 writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_mask()
62 tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_unmask()
64 writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_unmask()
74 tmp = readl_relaxed(eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_set_type()
96 writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq)); in mchp_eic_irq_set_type()
103 irq_set_irq_wake(eic->irqs[d->hwirq], on); in mchp_eic_irq_set_wake()
[all …]
Dirq-mips-gic.c82 /* All local interrupts are routable in EIC mode. */ in gic_local_irq_is_routable()
721 /* Enable or disable EIC */ in gic_cpu_startup()
794 /* Always use vector 1 in EIC mode */ in gic_of_init()
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpio/
Dgpio-eic-sprd.txt1 Spreadtrum EIC controller bindings
3 The EIC is the abbreviation of external interrupt controller, which can
4 be used only in input mode. The Spreadtrum platform has 2 EIC controllers,
5 one is in digital chip, and another one is in PMIC. The digital chip EIC
6 controller contains 4 sub-modules: EIC-debounce, EIC-latch, EIC-async and
7 EIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub-
10 The EIC-debounce sub-module provides up to 8 source input signal
19 The EIC-latch sub-module is used to latch some special power down signals
20 and generate interrupts, since the EIC-latch does not depend on the APB
23 The EIC-async sub-module uses a 32kHz clock to capture the short signals
[all …]
/kernel/linux/linux-5.10/drivers/gpio/
Dgpio-ep93xx.c52 struct ep93xx_gpio_irq_chip *eic; member
66 return egc->eic; in to_ep93xx_gpio_irq_chip()
81 struct ep93xx_gpio_irq_chip *eic) in ep93xx_gpio_update_int_params() argument
83 writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); in ep93xx_gpio_update_int_params()
85 writeb_relaxed(eic->int_type2, in ep93xx_gpio_update_int_params()
86 epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET); in ep93xx_gpio_update_int_params()
88 writeb_relaxed(eic->int_type1, in ep93xx_gpio_update_int_params()
89 epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET); in ep93xx_gpio_update_int_params()
91 writeb_relaxed(eic->int_unmasked & eic->int_enabled, in ep93xx_gpio_update_int_params()
92 epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); in ep93xx_gpio_update_int_params()
[all …]
Dgpio-eic-sprd.c16 /* EIC registers definition */
53 * The digital-chip EIC controller can support maximum 3 banks, and each bank
63 * The Spreadtrum EIC (external interrupt controller) can be used only in
66 * The Spreadtrum digital-chip EIC controller contains 4 sub-modules:
67 * debounce EIC, latch EIC, async EIC and sync EIC,
69 * The debounce EIC is used to capture the input signals' stable status
74 * The latch EIC is used to latch some special power down signals and
75 * generate interrupts, since the latch EIC does not depend on the APB clock
78 * The async EIC uses a 32k clock to capture the short signals (microsecond
81 * The EIC-sync is similar with GPIO's input function, which is a synchronized
[all …]
Dgpio-pmic-eic-sprd.c15 /* EIC registers definition */
27 * The PMIC EIC controller only has one bank, and each bank now can contain
48 * struct sprd_pmic_eic - PMIC EIC controller
52 * @offset: the EIC controller's offset address of the PMIC.
53 * @reg: the array to cache the EIC registers.
55 * @irq: the interrupt number of the PMIC EIC conteroller.
185 * Will set the trigger level according to current EIC level in sprd_pmic_eic_irq_set_type()
227 /* Generate trigger start pulse for debounce EIC */ in sprd_pmic_eic_bus_sync_unlock()
252 dev_warn(chip->parent, "PMIC EIC level was changed.\n"); in sprd_pmic_eic_toggle_trigger()
259 /* Generate trigger start pulse for debounce EIC */ in sprd_pmic_eic_toggle_trigger()
[all …]
DMakefile56 obj-$(CONFIG_GPIO_EIC_SPRD) += gpio-eic-sprd.o
120 obj-$(CONFIG_GPIO_PMIC_EIC_SPRD) += gpio-pmic-eic-sprd.o
/kernel/linux/linux-6.6/drivers/gpio/
Dgpio-ep93xx.c54 struct ep93xx_gpio_irq_chip *eic; member
68 return egc->eic; in to_ep93xx_gpio_irq_chip()
83 struct ep93xx_gpio_irq_chip *eic) in ep93xx_gpio_update_int_params() argument
85 writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); in ep93xx_gpio_update_int_params()
87 writeb_relaxed(eic->int_type2, in ep93xx_gpio_update_int_params()
88 epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET); in ep93xx_gpio_update_int_params()
90 writeb_relaxed(eic->int_type1, in ep93xx_gpio_update_int_params()
91 epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET); in ep93xx_gpio_update_int_params()
93 writeb_relaxed(eic->int_unmasked & eic->int_enabled, in ep93xx_gpio_update_int_params()
94 epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); in ep93xx_gpio_update_int_params()
[all …]
Dgpio-eic-sprd.c16 /* EIC registers definition */
53 * The digital-chip EIC controller can support maximum 3 banks, and each bank
63 * The Spreadtrum EIC (external interrupt controller) can be used only in
66 * The Spreadtrum digital-chip EIC controller contains 4 sub-modules:
67 * debounce EIC, latch EIC, async EIC and sync EIC,
69 * The debounce EIC is used to capture the input signals' stable status
74 * The latch EIC is used to latch some special power down signals and
75 * generate interrupts, since the latch EIC does not depend on the APB clock
78 * The async EIC uses a 32k clock to capture the short signals (microsecond
81 * The EIC-sync is similar with GPIO's input function, which is a synchronized
[all …]
Dgpio-pmic-eic-sprd.c15 /* EIC registers definition */
27 * The PMIC EIC controller only has one bank, and each bank now can contain
48 * struct sprd_pmic_eic - PMIC EIC controller
51 * @offset: the EIC controller's offset address of the PMIC.
52 * @reg: the array to cache the EIC registers.
54 * @irq: the interrupt number of the PMIC EIC conteroller.
189 * Will set the trigger level according to current EIC level in sprd_pmic_eic_irq_set_type()
231 /* Generate trigger start pulse for debounce EIC */ in sprd_pmic_eic_bus_sync_unlock()
256 dev_warn(chip->parent, "PMIC EIC level was changed.\n"); in sprd_pmic_eic_toggle_trigger()
263 /* Generate trigger start pulse for debounce EIC */ in sprd_pmic_eic_toggle_trigger()
[all …]
DMakefile57 obj-$(CONFIG_GPIO_EIC_SPRD) += gpio-eic-sprd.o
130 obj-$(CONFIG_GPIO_PMIC_EIC_SPRD) += gpio-pmic-eic-sprd.o
/kernel/linux/linux-6.6/drivers/hwmon/
Dsht21.c36 * @eic: cached electronic identification code text
45 char eic[18]; member
164 u8 eic[8]; in eic_read() local
186 eic[2] = rx[0]; in eic_read()
187 eic[3] = rx[2]; in eic_read()
188 eic[4] = rx[4]; in eic_read()
189 eic[5] = rx[6]; in eic_read()
197 eic[0] = rx[3]; in eic_read()
198 eic[1] = rx[4]; in eic_read()
199 eic[6] = rx[0]; in eic_read()
[all …]
/kernel/linux/linux-5.10/drivers/hwmon/
Dsht21.c36 * @eic: cached electronic identification code text
45 char eic[18]; member
164 u8 eic[8]; in eic_read() local
186 eic[2] = rx[0]; in eic_read()
187 eic[3] = rx[2]; in eic_read()
188 eic[4] = rx[4]; in eic_read()
189 eic[5] = rx[6]; in eic_read()
197 eic[0] = rx[3]; in eic_read()
198 eic[1] = rx[4]; in eic_read()
199 eic[6] = rx[0]; in eic_read()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/
Dmicrochip,sama7g5-eic.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/microchip,sama7g5-eic.yaml#
19 - microchip,sama7g5-eic
61 eic: interrupt-controller@e1628000 {
62 compatible = "microchip,sama7g5-eic";
/kernel/linux/linux-6.6/arch/mips/include/asm/mips-boards/
Dmaltaint.h42 * Interrupts 96..127 are used for Soc-it EIC interrupts
46 /* SOC-it EIC interrupt offsets */
/kernel/linux/linux-5.10/arch/mips/include/asm/mips-boards/
Dmaltaint.h42 * Interrupts 96..127 are used for Soc-it EIC interrupts
46 /* SOC-it EIC interrupt offsets */
/kernel/linux/linux-6.6/arch/arm64/boot/dts/sprd/
Dwhale2.dtsi202 compatible = "sprd,sc9860-eic-debounce";
212 compatible = "sprd,sc9860-eic-latch";
222 compatible = "sprd,sc9860-eic-async";
232 compatible = "sprd,sc9860-eic-sync";
/kernel/linux/linux-5.10/arch/arm64/boot/dts/sprd/
Dwhale2.dtsi200 compatible = "sprd,sc9860-eic-debounce";
210 compatible = "sprd,sc9860-eic-latch";
220 compatible = "sprd,sc9860-eic-async";
230 compatible = "sprd,sc9860-eic-sync";
/kernel/linux/linux-5.10/arch/s390/kvm/
Dintercept.c288 u16 eic = vcpu->arch.sie_block->eic; in handle_external_interrupt() local
307 if ((eic == EXT_IRQ_CLK_COMP || eic == EXT_IRQ_CPU_TIMER) && in handle_external_interrupt()
311 switch (eic) { in handle_external_interrupt()
/kernel/linux/linux-6.6/arch/s390/kvm/
Dintercept.c304 u16 eic = vcpu->arch.sie_block->eic; in handle_external_interrupt() local
323 if ((eic == EXT_IRQ_CLK_COMP || eic == EXT_IRQ_CPU_TIMER) && in handle_external_interrupt()
327 switch (eic) { in handle_external_interrupt()
/kernel/linux/linux-5.10/arch/mips/pistachio/
Dirq.c17 pr_info("EIC is %s\n", cpu_has_veic ? "on" : "off"); in arch_init_irq()
/kernel/linux/linux-6.6/Documentation/hwmon/
Dsht21.rst55 eic
/kernel/linux/linux-5.10/Documentation/hwmon/
Dsht21.rst55 eic
/kernel/linux/linux-5.10/drivers/irqchip/
Dirq-mips-gic.c81 /* All local interrupts are routable in EIC mode. */ in gic_local_irq_is_routable()
721 /* Enable or disable EIC */ in gic_cpu_startup()
795 /* Always use vector 1 in EIC mode */ in gic_of_init()

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