| /kernel/linux/linux-6.6/Documentation/gpu/ |
| D | drm-usage-stats.rst | 1 .. _drm-client-usage-stats:
8 `fops->show_fdinfo()` as part of the driver specific file operations registered
15 output is split between common and driver specific parts. Having said that,
22 - File shall contain one key value pair per one line of text.
23 - Colon character (`:`) must be used to delimit keys and values.
24 - All keys shall be prefixed with `drm-`.
25 - Whitespace between the delimiter and first non-whitespace character shall be
27 - Keys are not allowed to contain whitespace characters.
28 - Numerical key value pairs can end with optional unit string.
29 - Data type of the value is fixed as defined in the specification.
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| /kernel/linux/linux-5.10/drivers/gpu/drm/sun4i/ |
| D | sunxi_engine.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 * struct sunxi_engine_ops - helper operations for sunXi engines
25 * This callback allows to prepare our engine for an atomic
32 void (*atomic_begin)(struct sunxi_engine *engine,
38 * This callback allows to validate plane-update related CRTC
39 * constraints specific to engines. This is mirroring the
49 int (*atomic_check)(struct sunxi_engine *engine,
61 void (*commit)(struct sunxi_engine *engine);
67 * the layers supported by that engine.
77 struct sunxi_engine *engine);
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|
| /kernel/linux/linux-5.10/Documentation/driver-api/dmaengine/ |
| D | client.rst | 2 DMA Engine API Guide
7 .. note:: For DMA Engine usage in async_tx please see:
8 ``Documentation/crypto/async-tx-api.rst``
11 Below is a guide to device driver writers on how to use the Slave-DMA API of the
12 DMA Engine. This is applicable only for slave DMA usage only.
19 - Allocate a DMA slave channel
21 - Set slave and controller specific parameters
23 - Get a descriptor for transaction
25 - Submit the transaction
27 - Issue pending requests and wait for callback notification
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|
| /kernel/linux/linux-6.6/Documentation/driver-api/dmaengine/ |
| D | client.rst | 2 DMA Engine API Guide
7 .. note:: For DMA Engine usage in async_tx please see:
8 ``Documentation/crypto/async-tx-api.rst``
11 Below is a guide to device driver writers on how to use the Slave-DMA API of the
12 DMA Engine. This is applicable only for slave DMA usage only.
19 - Allocate a DMA slave channel
21 - Set slave and controller specific parameters
23 - Get a descriptor for transaction
25 - Submit the transaction
27 - Issue pending requests and wait for callback notification
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|
| /kernel/linux/linux-6.6/drivers/gpu/drm/sun4i/ |
| D | sunxi_engine.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
17 * struct sunxi_engine_ops - helper operations for sunXi engines
26 * This callback allows to prepare our engine for an atomic
33 void (*atomic_begin)(struct sunxi_engine *engine,
39 * This callback allows to validate plane-update related CRTC
40 * constraints specific to engines. This is mirroring the
50 int (*atomic_check)(struct sunxi_engine *engine,
62 void (*commit)(struct sunxi_engine *engine);
68 * the layers supported by that engine.
78 struct sunxi_engine *engine);
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|
| /kernel/linux/linux-6.6/Documentation/leds/ |
| D | leds-lp55xx.rst | 8 -----------
14 Device attributes for user-space interface
47 To support device specific configurations, special structure
50 - Maximum number of channels
51 - Reset command, chip enable command
52 - Chip specific initialization
53 - Brightness control register access
54 - Setting LED output current
55 - Program memory address access for running patterns
56 - Additional device specific attributes
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|
| /kernel/linux/linux-5.10/Documentation/leds/ |
| D | leds-lp55xx.rst | 8 -----------
14 Device attributes for user-space interface
47 To support device specific configurations, special structure
50 - Maximum number of channels
51 - Reset command, chip enable command
52 - Chip specific initialization
53 - Brightness control register access
54 - Setting LED output current
55 - Program memory address access for running patterns
56 - Additional device specific attributes
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mtd/ |
| D | nand-chip.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: mtd.yaml#
18 SPI-NAND devices are concerned by this description.
23 Contains the chip-select IDs.
25 nand-ecc-engine:
27 A phandle on the hardware ECC engine if any. There are
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|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | nand-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
21 they request the ECC engine to correct {strength} bit errors per
24 The interpretation of these parameters is implementation-defined, so
31 pattern: "^nand-controller(@.*)?"
33 "#address-cells":
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|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/fsi/ |
| D | fsi.txt | 1 FSI bus & engine generic device tree bindings
4 The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
6 nodes to probed engines. This allows for fsi engines to expose non-probeable
7 busses, which are then exposed by the device tree. For example, an FSI engine
8 that is an I2C master - the I2C bus can be described by the device tree under
9 the engine's device tree node.
13 the fsi-master-* binding specifications.
18 fsi-master {
19 /* top-level of FSI bus topology, bound to an FSI master driver and
22 fsi-slave@<link,id> {
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|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/fsi/ |
| D | fsi.txt | 1 FSI bus & engine generic device tree bindings
4 The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
6 nodes to probed engines. This allows for fsi engines to expose non-probeable
7 busses, which are then exposed by the device tree. For example, an FSI engine
8 that is an I2C master - the I2C bus can be described by the device tree under
9 the engine's device tree node.
13 the fsi-master-* binding specifications.
18 fsi-master {
19 /* top-level of FSI bus topology, bound to an FSI master driver and
22 fsi-slave@<link,id> {
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|
| /kernel/linux/linux-6.6/drivers/leds/ |
| D | leds-lp55xx-common.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 * Derived from leds-lp5521.c, leds-lp5523.c
15 #include <linux/led-class-multicolor.h>
93 * @reset : Chip specific reset command
94 * @enable : Chip specific enable command
96 * @post_init_device : Chip specific initialization code
101 * @run_engine : Run internal engine for pattern
102 * @dev_attr_group : Device specific attributes
109 /* define if the device has specific initialization process */
127 /* additional device specific attributes */
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|
| /kernel/linux/linux-5.10/drivers/leds/ |
| D | leds-lp55xx-common.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 * Derived from leds-lp5521.c, leds-lp5523.c
15 #include <linux/led-class-multicolor.h>
93 * @reset : Chip specific reset command
94 * @enable : Chip specific enable command
96 * @post_init_device : Chip specific initialization code
101 * @run_engine : Run internal engine for pattern
102 * @dev_attr_group : Device specific attributes
109 /* define if the device has specific initialization process */
127 /* additional device specific attributes */
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|
| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/ |
| D | intel_engine_heartbeat.c | 1 // SPDX-License-Identifier: MIT
17 * While the engine is active, we send a periodic pulse along the engine
18 * to check on its health and to flush any idle-barriers. If that request
19 * is stuck, and we fail to preempt it, we declare the engine hung and
20 * issue a reset -- in the hope that restores progress.
23 static bool next_heartbeat(struct intel_engine_cs *engine) in next_heartbeat() argument
28 delay = READ_ONCE(engine->props.heartbeat_interval_ms); in next_heartbeat()
30 rq = engine->heartbeat.systole; in next_heartbeat()
35 * selftests which override the value and expect specific behaviour. in next_heartbeat()
37 * heartbeat periods (or to override the pre-emption timeout as well, in next_heartbeat()
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|
| D | intel_engine_pm.c | 1 // SPDX-License-Identifier: MIT
20 static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine) in intel_gsc_idle_msg_enable() argument
22 struct drm_i915_private *i915 = engine->i915; in intel_gsc_idle_msg_enable()
24 if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) { in intel_gsc_idle_msg_enable()
25 intel_uncore_write(engine->gt->uncore, in intel_gsc_idle_msg_enable()
29 intel_uncore_write(engine->gt->uncore, in intel_gsc_idle_msg_enable()
40 if (ce->state) { in dbg_poison_ce()
41 struct drm_i915_gem_object *obj = ce->state->obj; in dbg_poison_ce()
42 int type = intel_gt_coherent_map_type(ce->engine->gt, obj, true); in dbg_poison_ce()
50 memset(map, CONTEXT_REDZONE, obj->base.size); in dbg_poison_ce()
[all …]
|
| /kernel/linux/linux-6.6/Documentation/gpu/amdgpu/ |
| D | driver-core.rst | 17 the SoC itself rather than specific IPs. E.g., things like GPU resets
23 SMU, PSP, etc.). Specific components (CPU, GPU, etc.) usually have
32 This was a dedicated IP on older pre-vega chips, but has since
34 have dedicated memory hubs for specific IPs or groups of IPs. We
58 It is described in more details in :ref:`Display Core <amdgpu-display-core>`.
61 This is a multi-purpose DMA engine. The kernel driver uses it for
67 This is the graphics and compute engine, i.e., the block that
69 largest block on the GPU. The 3D pipeline has tons of sub-blocks. In
75 This is the multi-media engine. It handles video and image encode and
76 decode. It's exposed to userspace for user mode drivers (VA-API,
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|
| /kernel/linux/linux-6.6/drivers/dma/ptdma/ |
| D | ptdma.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * -- Based on the CCP driver
25 #include "../virt-dma.h"
94 #define QUEUE_SIZE_VAL ((ffs(CMD_Q_LEN) - 2) & \
96 #define Q_PTR_MASK (2 << (QUEUE_SIZE_VAL + 5) - 1)
109 #define LSB_COUNT (LSB_END - LSB_START + 1)
124 * struct pt_passthru_engine - pass-through operation
133 * - bit_mod, byte_swap, src, dst, src_len
134 * - mask, mask_len if bit_mod is not PT_PASSTHRU_BITWISE_NOOP
145 * struct pt_cmd - PTDMA operation request
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|
| /kernel/linux/linux-5.10/Documentation/powerpc/ |
| D | vas-api.rst | 1 .. SPDX-License-Identifier: GPL-2.0
2 .. _VAS-API:
12 allows both userspace and kernel communicate to co-processor
14 unit comprises of one or more hardware engines or co-processor types
16 userspace applications will have access to only GZIP Compression engine
21 Requests to the GZIP engine must be formatted as a co-processor Request
24 the engine's request queue.
26 The GZIP engine provides two priority levels of requests: Normal and
37 Application access to the GZIP engine is provided through
38 /dev/crypto/nx-gzip device node implemented by the VAS/NX device driver.
[all …]
|
| /kernel/linux/linux-6.6/Documentation/powerpc/ |
| D | vas-api.rst | 1 .. SPDX-License-Identifier: GPL-2.0
2 .. _VAS-API:
12 allows both userspace and kernel communicate to co-processor
14 unit comprises of one or more hardware engines or co-processor types
16 userspace applications will have access to only GZIP Compression engine
21 Requests to the GZIP engine must be formatted as a co-processor Request
24 the engine's request queue.
26 The GZIP engine provides two priority levels of requests: Normal and
37 Application access to the GZIP engine is provided through
38 /dev/crypto/nx-gzip device node implemented by the VAS/NX device driver.
[all …]
|
| /kernel/linux/linux-6.6/drivers/crypto/marvell/cesa/ |
| D | cesa.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include <linux/dma-direction.h>
70 * in Errata 4.12. It looks like that it was part of an IRQ-controller in FPGA
124 * /-----------\ 0
126 * |-----------| 0x20
128 * |-----------| 0x40
130 * |-----------| 0x40 (inplace)
132 * |-----------| 0x80
133 * | DATA IN | 16 * x (max ->max_req_size)
134 * |-----------| 0x80 (inplace operation)
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|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/ |
| D | Kconfig | 1 # SPDX-License-Identifier: MIT
2 menu "Display Engine Configuration"
6 bool "AMD DC - Enable new display engine"
13 Choose this option if you want to use the new display engine
21 has been resolved: https://github.com/llvm/llvm-project/issues/41896.
26 Floating point support, required for DCN-based SoCs
51 This option enables the calculation of crc of specific region via
52 debugfs. Cooperate with specific DMCU FW.
|
| /kernel/linux/linux-5.10/drivers/crypto/marvell/cesa/ |
| D | cesa.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include <linux/dma-direction.h>
70 * in Errata 4.12. It looks like that it was part of an IRQ-controller in FPGA
124 * /-----------\ 0
126 * |-----------| 0x20
128 * |-----------| 0x40
130 * |-----------| 0x40 (inplace)
132 * |-----------| 0x80
133 * | DATA IN | 16 * x (max ->max_req_size)
134 * |-----------| 0x80 (inplace operation)
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|
| /kernel/linux/linux-6.6/drivers/accel/habanalabs/gaudi2/ |
| D | gaudi2P.h | 1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2020-2022 HabanaLabs, Ltd.
19 #define GAUDI2_LINUX_FW_FILE "habanalabs/gaudi2/gaudi2-fit.itb"
20 #define GAUDI2_BOOT_FIT_FILE "habanalabs/gaudi2/gaudi2-boot-fit.itb"
46 (((mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8191 - \
50 (((mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2047 - \
58 #define NUM_OF_EXPOSED_SM_BLOCKS ((NUM_OF_DCORES - 1) * 2)
75 #define SM_OBJS_BLOCK_SIZE (mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_0 - \
106 (GAUDI2_DCORE1_ENGINE_ID_EDMA_0 - GAUDI2_DCORE0_ENGINE_ID_EDMA_0)
141 #define VA_HOST_SPACE_PAGE_SIZE (VA_HOST_SPACE_PAGE_END - VA_HOST_SPACE_PAGE_START)
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|
| /kernel/linux/linux-6.6/drivers/net/ethernet/hisilicon/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
17 for your specific card in the following questions.
35 ports at 10/100 Mbps in full-duplex or half-duplex mode.
70 is needed by any driver which provides HNS acceleration engine or make
71 use of the engine
79 acceleration engine support. The engine is used in Hisilicon hip05,
97 This layer facilitates clients like ENET, RoCE and user-space ethernet
104 tristate "Hisilicon HNS3 HCLGE Acceleration Engine & Compatibility Layer Support"
109 This selects the HNS3_HCLGE network acceleration engine & its hardware
110 compatibility layer. The engine would be used in Hisilicon hip08 family of
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/ethernet/hisilicon/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
17 for your specific card in the following questions.
35 ports at 10/100 Mbps in full-duplex or half-duplex mode.
70 is needed by any driver which provides HNS acceleration engine or make
71 use of the engine
79 acceleration engine support. The engine is used in Hisilicon hip05,
95 This layer facilitates clients like ENET, RoCE and user-space ethernet
102 tristate "Hisilicon HNS3 HCLGE Acceleration Engine & Compatibility Layer Support"
106 This selects the HNS3_HCLGE network acceleration engine & its hardware
107 compatibility layer. The engine would be used in Hisilicon hip08 family of
[all …]
|