| /kernel/linux/linux-5.10/drivers/fpga/ |
| D | fpga-bridge.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Bridge Framework Driver
5 * Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
8 #include <linux/fpga/fpga-bridge.h>
23 * fpga_bridge_enable - Enable transactions on the bridge
25 * @bridge: FPGA bridge
29 int fpga_bridge_enable(struct fpga_bridge *bridge) in fpga_bridge_enable() argument
31 dev_dbg(&bridge->dev, "enable\n"); in fpga_bridge_enable()
33 if (bridge->br_ops && bridge->br_ops->enable_set) in fpga_bridge_enable()
34 return bridge->br_ops->enable_set(bridge, 1); in fpga_bridge_enable()
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # FPGA framework configuration
6 menuconfig FPGA config
7 tristate "FPGA Configuration Framework"
10 kernel. The FPGA framework adds a FPGA manager class and FPGA
13 if FPGA
16 tristate "Altera SOCFPGA FPGA Manager"
19 FPGA manager driver support for Altera SOCFPGA.
26 FPGA manager driver support for Altera Arria10 SoCFPGA.
41 tristate "Altera FPGA Passive Serial over SPI"
[all …]
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| D | altera-hps2fpga.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA to/from HPS Bridge Driver for Altera SoCFPGA Devices
5 * Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
8 * fpga: altera-hps2fpga: fix HPS2FPGA bridge visibility to L3 masters
9 * Signed-off-by: Anatolij Gustschin <agust@denx.de>
14 * processor system (HPS) and the embedded FPGA.
17 * allows for safe reprogramming of the FPGA, assuming that the new FPGA image
19 * reprogramming the FPGA and re-enabled after the FPGA has been programmed.
23 #include <linux/fpga/fpga-bridge.h>
49 static int alt_hps2fpga_enable_show(struct fpga_bridge *bridge) in alt_hps2fpga_enable_show() argument
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| D | altera-fpga2sdram.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA to SDRAM Bridge Driver for Altera SoCFPGA Devices
5 * Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
9 * This driver manages a bridge between an FPGA and the SDRAM used by the ARM
12 * The bridge contains 4 read ports, 4 write ports, and 6 command ports.
15 * nor can the FPGA access the SDRAM during reconfiguration. This driver does
21 * allows for safe reprogramming of the FPGA, assuming that the new FPGA image
23 * reprogramming the FPGA and re-enabled after the FPGA has been programmed.
26 #include <linux/fpga/fpga-bridge.h>
56 static int alt_fpga2sdram_enable_show(struct fpga_bridge *bridge) in alt_fpga2sdram_enable_show() argument
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| D | dfl-fme-br.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Bridge Driver for FPGA Management Engine (FME)
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
17 #include <linux/fpga/fpga-bridge.h>
20 #include "dfl-fme-pr.h"
28 static int fme_bridge_enable_set(struct fpga_bridge *bridge, bool enable) in fme_bridge_enable_set() argument
30 struct fme_br_priv *priv = bridge->priv; in fme_bridge_enable_set()
34 if (!priv->port_pdev) { in fme_bridge_enable_set()
35 port_pdev = dfl_fpga_cdev_find_port(priv->pdata->cdev, in fme_bridge_enable_set()
36 &priv->pdata->port_id, in fme_bridge_enable_set()
[all …]
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| /kernel/linux/linux-6.6/drivers/fpga/ |
| D | fpga-bridge.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Bridge Framework Driver
5 * Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
8 #include <linux/fpga/fpga-bridge.h>
23 * fpga_bridge_enable - Enable transactions on the bridge
25 * @bridge: FPGA bridge
29 int fpga_bridge_enable(struct fpga_bridge *bridge) in fpga_bridge_enable() argument
31 dev_dbg(&bridge->dev, "enable\n"); in fpga_bridge_enable()
33 if (bridge->br_ops && bridge->br_ops->enable_set) in fpga_bridge_enable()
34 return bridge->br_ops->enable_set(bridge, 1); in fpga_bridge_enable()
[all …]
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # FPGA framework configuration
6 menuconfig FPGA config
7 tristate "FPGA Configuration Framework"
10 kernel. The FPGA framework adds an FPGA manager class and FPGA
13 if FPGA
16 tristate "Altera SOCFPGA FPGA Manager"
19 FPGA manager driver support for Altera SOCFPGA.
26 FPGA manager driver support for Altera Arria10 SoCFPGA.
41 tristate "Altera FPGA Passive Serial over SPI"
[all …]
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| D | altera-hps2fpga.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA to/from HPS Bridge Driver for Altera SoCFPGA Devices
5 * Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
8 * fpga: altera-hps2fpga: fix HPS2FPGA bridge visibility to L3 masters
9 * Signed-off-by: Anatolij Gustschin <agust@denx.de>
14 * processor system (HPS) and the embedded FPGA.
17 * allows for safe reprogramming of the FPGA, assuming that the new FPGA image
19 * reprogramming the FPGA and re-enabled after the FPGA has been programmed.
23 #include <linux/fpga/fpga-bridge.h>
49 static int alt_hps2fpga_enable_show(struct fpga_bridge *bridge) in alt_hps2fpga_enable_show() argument
[all …]
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| D | altera-fpga2sdram.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA to SDRAM Bridge Driver for Altera SoCFPGA Devices
5 * Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
9 * This driver manages a bridge between an FPGA and the SDRAM used by the ARM
12 * The bridge contains 4 read ports, 4 write ports, and 6 command ports.
15 * nor can the FPGA access the SDRAM during reconfiguration. This driver does
21 * allows for safe reprogramming of the FPGA, assuming that the new FPGA image
23 * reprogramming the FPGA and re-enabled after the FPGA has been programmed.
26 #include <linux/fpga/fpga-bridge.h>
56 static int alt_fpga2sdram_enable_show(struct fpga_bridge *bridge) in alt_fpga2sdram_enable_show() argument
[all …]
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| D | dfl-fme-br.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Bridge Driver for FPGA Management Engine (FME)
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
17 #include <linux/fpga/fpga-bridge.h>
20 #include "dfl-fme-pr.h"
28 static int fme_bridge_enable_set(struct fpga_bridge *bridge, bool enable) in fme_bridge_enable_set() argument
30 struct fme_br_priv *priv = bridge->priv; in fme_bridge_enable_set()
34 if (!priv->port_pdev) { in fme_bridge_enable_set()
35 port_pdev = dfl_fpga_cdev_find_port(priv->pdata->cdev, in fme_bridge_enable_set()
36 &priv->pdata->port_id, in fme_bridge_enable_set()
[all …]
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| /kernel/linux/linux-5.10/Documentation/driver-api/fpga/ |
| D | fpga-bridge.rst | 1 FPGA Bridge
4 API to implement a new FPGA bridge
7 * struct fpga_bridge — The FPGA Bridge structure
8 * struct fpga_bridge_ops — Low level Bridge driver ops
9 * devm_fpga_bridge_create() — Allocate and init a bridge struct
10 * fpga_bridge_register() — Register a bridge
11 * fpga_bridge_unregister() — Unregister a bridge
13 .. kernel-doc:: include/linux/fpga/fpga-bridge.h
16 .. kernel-doc:: include/linux/fpga/fpga-bridge.h
19 .. kernel-doc:: drivers/fpga/fpga-bridge.c
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| D | fpga-region.rst | 1 FPGA Region
5 --------
7 This document is meant to be a brief overview of the FPGA region API usage. A
12 an FPGA Manager and a bridge (or bridges) with a reprogrammable region of an
13 FPGA or the whole FPGA. The API provides a way to register a region and to
16 Currently the only layer above fpga-region.c in the kernel is the Device Tree
17 support (of-fpga-region.c) described in [#f1]_. The DT support layer uses regions
18 to program the FPGA and then DT to handle enumeration. The common region code
22 An fpga-region can be set up to know the following things:
24 * which FPGA manager to use to do the programming
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| D | intro.rst | 4 The FPGA subsystem supports reprogramming FPGAs dynamically under
5 Linux. Some of the core intentions of the FPGA subsystems are:
7 * The FPGA subsystem is vendor agnostic.
9 * The FPGA subsystem separates upper layers (userspace interfaces and
11 FPGA.
16 other users. Write the linux-fpga mailing list and maintainers and
23 FPGA Manager
24 ------------
26 If you are adding a new FPGA or a new method of programming an FPGA,
27 this is the subsystem for you. Low level FPGA manager drivers contain
[all …]
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| /kernel/linux/linux-6.6/include/linux/fpga/ |
| D | fpga-bridge.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/fpga/fpga-mgr.h>
12 * struct fpga_bridge_ops - ops for low level FPGA bridge drivers
13 * @enable_show: returns the FPGA bridge's status
14 * @enable_set: set an FPGA bridge as enabled or disabled
15 * @fpga_bridge_remove: set FPGA into a specific state during driver remove
19 int (*enable_show)(struct fpga_bridge *bridge);
20 int (*enable_set)(struct fpga_bridge *bridge, bool enable);
21 void (*fpga_bridge_remove)(struct fpga_bridge *bridge);
26 * struct fpga_bridge_info - collection of parameters an FPGA Bridge
[all …]
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| /kernel/linux/linux-6.6/Documentation/driver-api/fpga/ |
| D | fpga-bridge.rst | 1 FPGA Bridge
4 API to implement a new FPGA bridge
7 * struct fpga_bridge - The FPGA Bridge structure
8 * struct fpga_bridge_ops - Low level Bridge driver ops
9 * __fpga_bridge_register() - Create and register a bridge
10 * fpga_bridge_unregister() - Unregister a bridge
13 the module that registers the FPGA bridge as the owner.
15 .. kernel-doc:: include/linux/fpga/fpga-bridge.h
18 .. kernel-doc:: include/linux/fpga/fpga-bridge.h
21 .. kernel-doc:: drivers/fpga/fpga-bridge.c
[all …]
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| D | fpga-region.rst | 1 FPGA Region
5 --------
7 This document is meant to be a brief overview of the FPGA region API usage. A
12 an FPGA Manager and a bridge (or bridges) with a reprogrammable region of an
13 FPGA or the whole FPGA. The API provides a way to register a region and to
16 Currently the only layer above fpga-region.c in the kernel is the Device Tree
17 support (of-fpga-region.c) described in [#f1]_. The DT support layer uses regions
18 to program the FPGA and then DT to handle enumeration. The common region code
22 An fpga-region can be set up to know the following things:
24 * which FPGA manager to use to do the programming
[all …]
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| D | intro.rst | 4 The FPGA subsystem supports reprogramming FPGAs dynamically under
5 Linux. Some of the core intentions of the FPGA subsystems are:
7 * The FPGA subsystem is vendor agnostic.
9 * The FPGA subsystem separates upper layers (userspace interfaces and
11 FPGA.
16 other users. Write the linux-fpga mailing list and maintainers and
23 FPGA Manager
24 ------------
26 If you are adding a new FPGA or a new method of programming an FPGA,
27 this is the subsystem for you. Low level FPGA manager drivers contain
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/fpga/ |
| D | fpga-region.txt | 1 FPGA Region Device Tree Binding
6 - Introduction
7 - Terminology
8 - Sequence
9 - FPGA Region
10 - Supported Use Models
11 - Device Tree Examples
12 - Constraints
18 FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in
19 the Device Tree. FPGA Regions provide a way to program FPGAs under device tree
[all …]
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| D | altera-hps2fpga-bridge.txt | 1 Altera FPGA/HPS Bridge Driver
4 - regs : base address and size for AXI bridge module
5 - compatible : Should contain one of:
6 "altr,socfpga-lwhps2fpga-bridge",
7 "altr,socfpga-hps2fpga-bridge", or
8 "altr,socfpga-fpga2hps-bridge"
9 - resets : Phandle and reset specifier for this bridge's reset
10 - clocks : Clocks used by this module.
12 See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
15 fpga_bridge0: fpga-bridge@ff400000 {
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| D | xilinx-pr-decoupler.txt | 4 decouplers / fpga bridges.
6 changes from passing through the bridge. The controller can also
8 bridge normally.
15 - compatible : Should contain "xlnx,pr-decoupler-1.00" followed by
16 "xlnx,pr-decoupler"
17 - regs : base address and size for decoupler module
18 - clocks : input clock to IP
19 - clock-names : should contain "aclk"
21 See Documentation/devicetree/bindings/fpga/fpga-region.txt and
22 Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/fpga/ |
| D | fpga-region.txt | 1 FPGA Region Device Tree Binding
6 - Introduction
7 - Terminology
8 - Sequence
9 - FPGA Region
10 - Supported Use Models
11 - Device Tree Examples
12 - Constraints
18 FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in
19 the Device Tree. FPGA Regions provide a way to program FPGAs under device tree
[all …]
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| D | altera-hps2fpga-bridge.txt | 1 Altera FPGA/HPS Bridge Driver
4 - regs : base address and size for AXI bridge module
5 - compatible : Should contain one of:
6 "altr,socfpga-lwhps2fpga-bridge",
7 "altr,socfpga-hps2fpga-bridge", or
8 "altr,socfpga-fpga2hps-bridge"
9 - resets : Phandle and reset specifier for this bridge's reset
10 - clocks : Clocks used by this module.
12 See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
15 fpga_bridge0: fpga-bridge@ff400000 {
[all …]
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| /kernel/linux/linux-5.10/include/linux/fpga/ |
| D | fpga-bridge.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/fpga/fpga-mgr.h>
12 * struct fpga_bridge_ops - ops for low level FPGA bridge drivers
13 * @enable_show: returns the FPGA bridge's status
14 * @enable_set: set a FPGA bridge as enabled or disabled
15 * @fpga_bridge_remove: set FPGA into a specific state during driver remove
19 int (*enable_show)(struct fpga_bridge *bridge);
20 int (*enable_set)(struct fpga_bridge *bridge, bool enable);
21 void (*fpga_bridge_remove)(struct fpga_bridge *bridge);
26 * struct fpga_bridge - FPGA bridge structure
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| /kernel/linux/linux-6.6/drivers/fpga/tests/ |
| D | fpga-region-test.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit test for the FPGA Region
11 #include <linux/fpga/fpga-bridge.h>
12 #include <linux/fpga/fpga-mgr.h>
13 #include <linux/fpga/fpga-region.h>
30 struct fpga_bridge *bridge; member
40 struct mgr_stats *stats = mgr->priv; in op_write()
42 stats->write_count++; in op_write()
48 * Fake FPGA manager that implements only the write op to count the number
57 static int op_enable_set(struct fpga_bridge *bridge, bool enable) in op_enable_set() argument
[all …]
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| D | fpga-bridge-test.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit test for the FPGA Bridge
12 #include <linux/fpga/fpga-bridge.h>
21 struct fpga_bridge *bridge; member
26 static int op_enable_set(struct fpga_bridge *bridge, bool enable) in op_enable_set() argument
28 struct bridge_stats *stats = bridge->priv; in op_enable_set()
30 stats->enable = enable; in op_enable_set()
36 * Fake FPGA bridge that implements only the enable_set op to track
44 * register_test_bridge() - Register a fake FPGA bridge for testing.
47 * Return: Context of the newly registered FPGA bridge.
[all …]
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