Searched +full:iommu +full:- +full:addresses (Results 1 – 25 of 284) sorted by relevance
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/reserved-memory/ |
| D | reserved-memory.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reserved-memory/reserved-memory.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: /reserved-memory Child Node Common
10 - devicetree-spec@vger.kernel.org
13 Reserved memory is specified as a node under the /reserved-memory node. The
19 Each child of the reserved-memory node specifies one or more regions
25 Following the generic-names recommended practice, node names should
26 reflect the purpose of the node (ie. "framebuffer" or "dma-pool").
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/iommu/ |
| D | rockchip,iommu.txt | 1 Rockchip IOMMU
4 A Rockchip DRM iommu translates io virtual addresses to physical addresses for
9 - compatible : Should be "rockchip,iommu"
10 - reg : Address space for the configuration registers
11 - interrupts : Interrupt specifier for the IOMMU instance
12 - interrupt-names : Interrupt name for the IOMMU instance
13 - #iommu-cells : Should be <0>. This indicates the iommu is a
14 "single-master" device, and needs no additional information
16 Documentation/devicetree/bindings/iommu/iommu.txt
17 - clocks : A list of clocks required for the IOMMU to be accessible by
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| D | iommu.txt | 5 IOMMU device node:
8 An IOMMU can provide the following services:
13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
19 through the IOMMU and faulting when encountering accesses to unmapped
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
31 master IOMMU devices can translate accesses from more than one master.
33 The device tree node of the IOMMU device's parent bus must contain a valid
34 "dma-ranges" property that describes how the physical address space of the
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/iommu/ |
| D | rockchip,iommu.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/rockchip,iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip IOMMU
10 - Heiko Stuebner <heiko@sntech.de>
13 A Rockchip DRM iommu translates io virtual addresses to physical addresses for
17 For information on assigning IOMMU controller to its peripheral devices,
18 see generic IOMMU bindings.
23 - rockchip,iommu
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| D | iommu.txt | 5 IOMMU device node:
8 An IOMMU can provide the following services:
13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
19 through the IOMMU and faulting when encountering accesses to unmapped
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
31 master IOMMU devices can translate accesses from more than one master.
33 The device tree node of the IOMMU device's parent bus must contain a valid
34 "dma-ranges" property that describes how the physical address space of the
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| /kernel/linux/linux-5.10/Documentation/x86/ |
| D | sva.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 same virtual addresses avoiding the need for software to translate virtual
12 addresses to physical addresses. SVA is what PCIe calls Shared Virtual
15 In addition to the convenience of using application virtual addresses
19 application page-faults. For more information please refer to the PCIe
22 Use of SVA requires IOMMU support in the platform. IOMMU is also
24 to cache translations for virtual addresses. The IOMMU driver uses the
34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
40 ID (PASID), which is a 20-bit number defined by the PCIe SIG.
43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe
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| /kernel/linux/linux-6.6/Documentation/arch/x86/ |
| D | sva.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 same virtual addresses avoiding the need for software to translate virtual
12 addresses to physical addresses. SVA is what PCIe calls Shared Virtual
15 In addition to the convenience of using application virtual addresses
19 application page-faults. For more information please refer to the PCIe
22 Use of SVA requires IOMMU support in the platform. IOMMU is also
24 to cache translations for virtual addresses. The IOMMU driver uses the
34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
40 ID (PASID), which is a 20-bit number defined by the PCIe SIG.
43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe
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| D | iommu.rst | 2 x86 IOMMU Support
7 - Intel: http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-dire…
8 - AMD: https://www.amd.com/system/files/TechDocs/48882_IOMMU.pdf
13 -----------
16 device scope relationships between devices and which IOMMU controls
21 - DMAR - Intel DMA Remapping table
22 - DRHD - Intel DMA Remapping Hardware Unit Definition
23 - RMRR - Intel Reserved Memory Region Reporting Structure
24 - IVRS - AMD I/O Virtualization Reporting Structure
25 - IVDB - AMD I/O Virtualization Definition Block
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| /kernel/linux/linux-6.6/Documentation/arch/s390/ |
| D | vfio-ccw.rst | 2 vfio-ccw: the basic infrastructure
6 ------------
9 Linux/s390. Motivation for vfio-ccw is to passthrough subchannels to a
16 - Channel programs run asynchronously on a separate (co)processor.
17 - The channel subsystem will access any memory designated by the caller
18 in the channel program directly, i.e. there is no iommu involved.
22 added to an iommu group, so as to make itself able to be managed by the
31 - A good start to know Channel I/O in general:
33 - s390 architecture:
34 s390 Principles of Operation manual (IBM Form. No. SA22-7832)
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| /kernel/linux/linux-5.10/Documentation/s390/ |
| D | vfio-ccw.rst | 2 vfio-ccw: the basic infrastructure
6 ------------
9 Linux/s390. Motivation for vfio-ccw is to passthrough subchannels to a
16 - Channel programs run asynchronously on a separate (co)processor.
17 - The channel subsystem will access any memory designated by the caller
18 in the channel program directly, i.e. there is no iommu involved.
22 added to an iommu group, so as to make itself able to be managed by the
31 - A good start to know Channel I/O in general:
33 - s390 architecture:
34 s390 Principles of Operation manual (IBM Form. No. SA22-7832)
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| /kernel/linux/linux-6.6/drivers/iommu/intel/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 # Intel IOMMU support
13 bool "Support for Intel IOMMU using DMA Remapping Devices"
34 bool "Export Intel IOMMU internals in Debugfs"
43 Expose Intel IOMMU internals in Debugfs.
45 This option is -NOT- intended for production environments, and should
46 only be enabled for debugging Intel IOMMU.
49 bool "Support for Shared Virtual Memory with Intel IOMMU"
72 option permits the IOMMU driver to set a unity map for
73 all the OS-visible memory. Hence the driver can continue
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| /kernel/linux/linux-5.10/drivers/iommu/intel/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 # Intel IOMMU support
7 bool "Support for Intel IOMMU using DMA Remapping Devices"
24 bool "Export Intel IOMMU internals in Debugfs"
31 Expose Intel IOMMU internals in Debugfs.
33 This option is -NOT- intended for production environments, and should
34 only be enabled for debugging Intel IOMMU.
37 bool "Support for Shared Virtual Memory with Intel IOMMU"
63 option permits the IOMMU driver to set a unity map for
64 all the OS-visible memory. Hence the driver can continue
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| D | pasid.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * pasid.h - PASID idr, table and entry header
24 #define is_pasid_enabled(entry) (((entry)->lo >> 3) & 0x1)
25 #define get_pasid_dir_size(entry) (1 << ((((entry)->lo >> 9) & 0x7) + 7))
38 * Domain ID reserved for pasid entries programmed for first-level
39 * only and pass-through transfer modes.
45 * can be used for access to kernel addresses. It is valid only for
54 * The PASID_FLAG_FL5LP flag Indicates using 5-level paging for first-
55 * level translation, otherwise, 4-level paging will be used.
83 return READ_ONCE(pde->val) & PASID_PTE_PRESENT; in pasid_pde_is_present()
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| /kernel/linux/linux-5.10/include/linux/ |
| D | remoteproc.h | 47 * struct resource_table - firmware resource table header
81 * struct fw_rsc_hdr - firmware resource entry header
95 * enum fw_resource_type - types of resource entries
99 * @RSC_DEVMEM: request to iommu_map a memory-based peripheral.
126 #define FW_RSC_ADDR_ANY (-1)
129 * struct fw_rsc_carveout - physically contiguous memory request
133 * @flags: iommu protection flags
135 * @name: human-readable name of the requested memory region
146 * needed to map it (in case @rproc is using an IOMMU). Reducing the TLB
149 * If the firmware is compiled with static addresses, then @da should specify
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| D | iommu.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
17 #include <uapi/linux/iommu.h>
31 * if the IOMMU page table format is equivalent.
44 /* iommu fault flags */
60 #define __IOMMU_DOMAIN_DMA_API (1U << 1) /* Domain for use in DMA-API
65 * This are the possible domain-types
67 * IOMMU_DOMAIN_BLOCKED - All DMA is blocked, can be used to isolate
69 * IOMMU_DOMAIN_IDENTITY - DMA addresses are system physical addresses
70 * IOMMU_DOMAIN_UNMANAGED - DMA mappings managed by IOMMU-API user, used
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| /kernel/linux/linux-6.6/include/linux/ |
| D | iommu.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
16 #include <uapi/linux/iommu.h>
30 * if the IOMMU page table format is equivalent.
45 /* iommu fault flags */
61 #define __IOMMU_DOMAIN_DMA_API (1U << 1) /* Domain for use in DMA-API
64 #define __IOMMU_DOMAIN_DMA_FQ (1U << 3) /* DMA-API uses flush queue */
70 * This are the possible domain-types
72 * IOMMU_DOMAIN_BLOCKED - All DMA is blocked, can be used to isolate
74 * IOMMU_DOMAIN_IDENTITY - DMA addresses are system physical addresses
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| D | remoteproc.h | 47 * struct resource_table - firmware resource table header
81 * struct fw_rsc_hdr - firmware resource entry header
95 * enum fw_resource_type - types of resource entries
99 * @RSC_DEVMEM: request to iommu_map a memory-based peripheral.
126 #define FW_RSC_ADDR_ANY (-1)
129 * struct fw_rsc_carveout - physically contiguous memory request
133 * @flags: iommu protection flags
135 * @name: human-readable name of the requested memory region
146 * needed to map it (in case @rproc is using an IOMMU). Reducing the TLB
149 * If the firmware is compiled with static addresses, then @da should specify
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| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/ |
| D | msm_iommu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/adreno-smmu-priv.h>
8 #include <linux/io-pgtable.h>
35 /* based on iommu_pgsize() in iommu.c: */
46 pgsizes = pagetable->pgsize_bitmap & GENMASK(__fls(size), 0); in calc_pgsize()
62 pgsizes = pagetable->pgsize_bitmap & ~GENMASK(pgsize_idx, 0); in calc_pgsize()
71 * and physical addresses are similarly offset within the larger page. in calc_pgsize()
73 if ((iova ^ paddr) & (pgsize_next - 1)) in calc_pgsize()
77 offset = pgsize_next - (addr_merge & (pgsize_next - 1)); in calc_pgsize()
95 struct io_pgtable_ops *ops = pagetable->pgtbl_ops; in msm_iommu_pagetable_unmap()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/ |
| D | msm_iommu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/adreno-smmu-priv.h>
8 #include <linux/io-pgtable.h>
36 struct io_pgtable_ops *ops = pagetable->pgtbl_ops; in msm_iommu_pagetable_unmap()
41 unmapped += ops->unmap(ops, iova, 4096, NULL); in msm_iommu_pagetable_unmap()
43 size -= 4096; in msm_iommu_pagetable_unmap()
46 iommu_flush_iotlb_all(to_msm_iommu(pagetable->parent)->domain); in msm_iommu_pagetable_unmap()
48 return (unmapped == size) ? 0 : -EINVAL; in msm_iommu_pagetable_unmap()
55 struct io_pgtable_ops *ops = pagetable->pgtbl_ops; in msm_iommu_pagetable_map()
62 size_t size = sg->length; in msm_iommu_pagetable_map()
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| /kernel/linux/linux-6.6/arch/sparc/include/asm/ |
| D | iommu_32.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* iommu.h: Definitions for the sun4m IOMMU.
12 /* The iommu handles all virtual to physical address translations
15 * translated by the on chip SRMMU. The iommu and the srmmu do
18 * Basically the iommu handles all dvma sbus activity.
21 /* The IOMMU registers occupy three pages in IO space. */
24 volatile unsigned long control; /* IOMMU control */
31 volatile unsigned long afsr; /* Async-fault status register */
32 volatile unsigned long afar; /* Async-fault physical address */
34 volatile unsigned long sbuscfg0; /* SBUS configuration registers, per-slot */
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| /kernel/linux/linux-5.10/arch/sparc/include/asm/ |
| D | iommu_32.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* iommu.h: Definitions for the sun4m IOMMU.
12 /* The iommu handles all virtual to physical address translations
15 * translated by the on chip SRMMU. The iommu and the srmmu do
18 * Basically the iommu handles all dvma sbus activity.
21 /* The IOMMU registers occupy three pages in IO space. */
24 volatile unsigned long control; /* IOMMU control */
31 volatile unsigned long afsr; /* Async-fault status register */
32 volatile unsigned long afar; /* Async-fault physical address */
34 volatile unsigned long sbuscfg0; /* SBUS configuration registers, per-slot */
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdkfd/ |
| D | kfd_flat_memory.c | 43 * Access to ATC/IOMMU mapped memory w/ associated extension of VA to 48b
56 * System Unified Address - SUA
58 * The standard usage for GPU virtual addresses are that they are mapped by
66 * the operating system. This is via a technique and hardware called ATC/IOMMU.
80 * HSA64 - ATC/IOMMU 64b
89 * ATC/IOMMU, but it also has access to the GPUVM address space. The “system
97 * IOMMU path.
109 * ATC==1 means the 48b address is intended to be translated via IOMMU
137 * In all cases (no matter where the 64b -> 49b conversion is done), the gfxip
188 * HSA32 - ATC/IOMMU 32b
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| /kernel/linux/linux-5.10/Documentation/misc-devices/ |
| D | uacce.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 ---------------------
6 Uacce (Unified/User-space-access-intended Accelerator Framework) targets to
14 IOMMU share the same CPU page tables and as a result the same translation
29 | MMU | | IOMMU |
42 ------------
44 Uacce is the kernel module, taking charge of iommu and address sharing.
47 The uacce device, built around the IOMMU SVA API, can access multiple
51 FIFO-like interface. And it maintains a unified address space between the
58 | WarpDrive library | ------------> | user driver |
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| /kernel/linux/linux-6.6/Documentation/misc-devices/ |
| D | uacce.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 ---------------------
6 Uacce (Unified/User-space-access-intended Accelerator Framework) targets to
14 IOMMU share the same CPU page tables and as a result the same translation
29 | MMU | | IOMMU |
42 ------------
44 Uacce is the kernel module, taking charge of iommu and address sharing.
47 The uacce device, built around the IOMMU SVA API, can access multiple
51 FIFO-like interface. And it maintains a unified address space between the
58 | WarpDrive library | ------------> | user driver |
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| /kernel/linux/linux-5.10/drivers/iommu/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 # The IOVA library may also be used by non-IOMMU_API users
6 # The IOASID library may also be used by non-IOMMU_API users
15 bool "IOMMU Hardware Support"
26 menu "Generic IOMMU Pagetable Support"
39 sizes at both stage-1 and stage-2, as well as address spaces
40 up to 48-bits in size.
46 Enable self-tests for LPAE page table allocator. This performs
47 a series of page-table consistency checks during boot.
56 Enable support for the ARM Short-descriptor pagetable format.
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