| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | brcm,l2-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,l2-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <f.fainelli@gmail.com>
13 - $ref: /schemas/interrupt-controller.yaml#
18 - items:
19 - enum:
20 - brcm,hif-spi-l2-intc
21 - brcm,upg-aux-aon-l2-intc
[all …]
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| D | brcm,bcm7120-l2-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM7120-style Level 2 and Broadcom BCM3380 Level 1 / Level 2
10 - Florian Fainelli <f.fainelli@gmail.com>
14 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
19 - outputs multiple interrupts signals towards its interrupt controller parent
21 - controls how some of the interrupts will be flowing, whether they will
26 - has one 32-bit enable word and one 32-bit status word
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | brcm,l2-intc.txt | 5 - compatible: should be one of:
6 "brcm,hif-spi-l2-intc" or
7 "brcm,upg-aux-aon-l2-intc" or
8 "brcm,l2-intc" for latched interrupt controllers
9 should be "brcm,bcm7271-l2-intc" for level interrupt controllers
10 - reg: specifies the base physical address and size of the registers
11 - interrupt-controller: identifies the node as an interrupt controller
12 - #interrupt-cells: specifies the number of cells needed to encode an
14 - interrupts: specifies the interrupt line in the interrupt-parent irq space
19 - brcm,irq-can-wake: If present, this means the L2 controller can be used as a
[all …]
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| D | brcm,bcm3380-l2-intc.txt | 1 Broadcom BCM3380-style Level 1 / Level 2 interrupt controller
6 - outputs a single interrupt signal to its interrupt controller parent
8 - contains one or more enable/status word pairs, which often appear at
11 - no atomic set/clear operations
15 - compatible: should be "brcm,bcm3380-l2-intc"
16 - reg: specifies one or more enable/status pairs, in the following format:
18 - interrupt-controller: identifies the node as an interrupt controller
19 - #interrupt-cells: specifies the number of cells needed to encode an interrupt
21 - interrupts: specifies the interrupt line in the interrupt-parent controller
26 - brcm,irq-can-wake: if present, this means the L2 controller can be used as a
[all …]
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| D | brcm,bcm7120-l2-intc.txt | 1 Broadcom BCM7120-style Level 2 interrupt controller
4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
9 - outputs multiple interrupts signals towards its interrupt controller parent
11 - controls how some of the interrupts will be flowing, whether they will
16 - has one 32-bit enable word and one 32-bit status word
18 - no atomic set/clear operations
20 - not all bits within the interrupt controller actually map to an interrupt
26 0 -----[ MUX ] ------------|==========> GIC interrupt 75
27 \-----------\
29 1 -----[ MUX ] --------)---|==========> GIC interrupt 76
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/cpufreq/ |
| D | brcm,stb-avs-cpu-freq.txt | 4 A total of three DT nodes are required. One node (brcm,avs-cpu-data-mem)
6 second node (brcm,avs-cpu-l2-intr) is required to trigger an interrupt on
13 has been processed. See [2] for more information on the brcm,l2-intc node.
15 [1] The AVS CPU is an independent co-processor that runs proprietary
19 [2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml
22 Node brcm,avs-cpu-data-mem
23 --------------------------
26 - compatible: must include: brcm,avs-cpu-data-mem and
27 should include: one of brcm,bcm7271-avs-cpu-data-mem or
28 brcm,bcm7268-avs-cpu-data-mem
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/cpufreq/ |
| D | brcm,stb-avs-cpu-freq.txt | 4 A total of three DT nodes are required. One node (brcm,avs-cpu-data-mem)
6 second node (brcm,avs-cpu-l2-intr) is required to trigger an interrupt on
13 has been processed. See [2] for more information on the brcm,l2-intc node.
15 [1] The AVS CPU is an independent co-processor that runs proprietary
19 [2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
22 Node brcm,avs-cpu-data-mem
23 --------------------------
26 - compatible: must include: brcm,avs-cpu-data-mem and
27 should include: one of brcm,bcm7271-avs-cpu-data-mem or
28 brcm,bcm7268-avs-cpu-data-mem
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | arm-realview-pbx-a9.dts | 23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
28 * This is the RealView Platform Baseboard Explore for Cortex-A9
31 model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
35 #address-cells = <1>;
36 #size-cells = <0>;
37 enable-method = "arm,realview-smp";
39 cpu-map {
51 compatible = "arm,cortex-a9";
53 next-level-cache = <&L2>;
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/arm/ |
| D | arm-realview-pbx-a9.dts | 23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
28 * This is the RealView Platform Baseboard Explore for Cortex-A9
31 model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
35 #address-cells = <1>;
36 #size-cells = <0>;
37 enable-method = "arm,realview-smp";
39 cpu-map {
51 compatible = "arm,cortex-a9";
53 next-level-cache = <&L2>;
[all …]
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| /kernel/linux/linux-6.6/drivers/irqchip/ |
| D | irq-brcmstb-l2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014-2024 Broadcom
34 /* Register offsets in the L2 latched interrupt controller */
44 /* Register offsets in the L2 level interrupt controller */
48 .cpu_clear = -1, /* Register not present */
54 /* L2 intc private data structure */
65 * brcmstb_l2_mask_and_ack - Mask and ack pending interrupt
81 u32 mask = d->mask; in brcmstb_l2_mask_and_ack()
84 irq_reg_writel(gc, mask, ct->regs.disable); in brcmstb_l2_mask_and_ack()
85 *ct->mask_cache &= ~mask; in brcmstb_l2_mask_and_ack()
[all …]
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| /kernel/linux/linux-5.10/arch/arc/kernel/ |
| D | intc-compact.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com)
18 * -Platform independent, needed for each CPU (not foldable into init_IRQ)
19 * -Called very early (start_kernel -> setup_arch -> setup_processor)
22 * -Optionally, setup the High priority Interrupts as Level 2 IRQs
38 pr_info("Level-2 interrupts bitset %x\n", level_mask); in arc_init_IRQ()
54 * ARC700 core includes a simple on-chip intc supporting
55 * -per IRQ enable/disable
56 * -2 levels of interrupts (high/low)
57 * -all interrupts being level triggered
[all …]
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| /kernel/linux/linux-6.6/arch/arc/kernel/ |
| D | intc-compact.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com)
18 * -Platform independent, needed for each CPU (not foldable into init_IRQ)
19 * -Called very early (start_kernel -> setup_arch -> setup_processor)
22 * -Optionally, setup the High priority Interrupts as Level 2 IRQs
38 pr_info("Level-2 interrupts bitset %x\n", level_mask); in arc_init_IRQ()
54 * ARC700 core includes a simple on-chip intc supporting
55 * -per IRQ enable/disable
56 * -2 levels of interrupts (high/low)
57 * -all interrupts being level triggered
[all …]
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| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-brcmstb-l2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014-2024 Broadcom
35 /* Register offsets in the L2 latched interrupt controller */
45 /* Register offsets in the L2 level interrupt controller */
49 .cpu_clear = -1, /* Register not present */
55 /* L2 intc private data structure */
66 * brcmstb_l2_mask_and_ack - Mask and ack pending interrupt
82 u32 mask = d->mask; in brcmstb_l2_mask_and_ack()
85 irq_reg_writel(gc, mask, ct->regs.disable); in brcmstb_l2_mask_and_ack()
86 *ct->mask_cache &= ~mask; in brcmstb_l2_mask_and_ack()
[all …]
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| /kernel/linux/linux-5.10/arch/mips/boot/dts/brcm/ |
| D | bcm7358.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
24 cpu_intc: interrupt-controller {
25 #address-cells = <0>;
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
[all …]
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| D | bcm3384_zephyr.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 mips-hpt-frequency = <100000000>;
35 #address-cells = <0>;
36 compatible = "mti,cpu-interrupt-controller";
38 interrupt-controller;
39 #interrupt-cells = <1>;
[all …]
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| D | bcm7360.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
24 cpu_intc: interrupt-controller {
25 #address-cells = <0>;
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
[all …]
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| D | bcm7362.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
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| D | bcm7346.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <163125000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
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| D | bcm7425.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <163125000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
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| /kernel/linux/linux-6.6/arch/mips/boot/dts/brcm/ |
| D | bcm7358.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
24 cpu_intc: interrupt-controller {
25 #address-cells = <0>;
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
[all …]
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| D | bcm3384_zephyr.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 mips-hpt-frequency = <100000000>;
35 #address-cells = <0>;
36 compatible = "mti,cpu-interrupt-controller";
38 interrupt-controller;
39 #interrupt-cells = <1>;
[all …]
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| D | bcm7360.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
24 cpu_intc: interrupt-controller {
25 #address-cells = <0>;
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
[all …]
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| D | bcm7362.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
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| D | bcm7346.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <163125000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/ |
| D | bcm2836.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #include "bcm2835-common.dtsi"
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
13 local_intc: interrupt-controller@40000000 {
14 compatible = "brcm,bcm2836-l1-intc";
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
22 arm-pmu {
23 compatible = "arm,cortex-a7-pmu";
[all …]
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