| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/iio/frequency/ |
| D | adi,adrf6780.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
21 - adi,adrf6780
26 spi-max-frequency:
34 clock-names:
36 - const: lo_in
38 clock-output-names:
41 adi,vga-buff-en:
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/misc/ |
| D | fsl,qoriq-mc.txt | 3 The Freescale Management Complex (fsl-mc) is a hardware resource
5 network-oriented packet processing applications. After the fsl-mc
12 For an overview of the DPAA2 architecture and fsl-mc bus see:
16 same hardware "isolation context" and a 10-bit value called an ICID
21 between ICIDs and IOMMUs, so an iommu-map property is used to define
28 For arm-smmu binding, see:
31 The MSI writes are accompanied by sideband data which is derived from the ICID.
32 The msi-map property is used to associate the devices with both the ITS
33 controller and the sideband data which accompanies the writes.
36 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/misc/ |
| D | fsl,qoriq-mc.txt | 3 The Freescale Management Complex (fsl-mc) is a hardware resource
5 network-oriented packet processing applications. After the fsl-mc
12 For an overview of the DPAA2 architecture and fsl-mc bus see:
16 same hardware "isolation context" and a 10-bit value called an ICID
21 between ICIDs and IOMMUs, so an iommu-map property is used to define
28 For arm-smmu binding, see:
31 The MSI writes are accompanied by sideband data which is derived from the ICID.
32 The msi-map property is used to associate the devices with both the ITS
33 controller and the sideband data which accompanies the writes.
36 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
[all …]
|
| /kernel/linux/linux-6.6/drivers/iio/frequency/ |
| D | adrf6780.c | 1 // SPDX-License-Identifier: GPL-2.0-only
97 st->data[0] = 0x80 | (reg << 1); in __adrf6780_spi_read()
98 st->data[1] = 0x0; in __adrf6780_spi_read()
99 st->data[2] = 0x0; in __adrf6780_spi_read()
101 t.rx_buf = &st->data[0]; in __adrf6780_spi_read()
102 t.tx_buf = &st->data[0]; in __adrf6780_spi_read()
105 ret = spi_sync_transfer(st->spi, &t, 1); in __adrf6780_spi_read()
109 *val = (get_unaligned_be24(&st->data[0]) >> 1) & GENMASK(15, 0); in __adrf6780_spi_read()
119 mutex_lock(&st->lock); in adrf6780_spi_read()
121 mutex_unlock(&st->lock); in adrf6780_spi_read()
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/ethernet/intel/ice/ |
| D | ice_ptp_hw.c | 1 // SPDX-License-Identifier: GPL-2.0
16 * +---------------+ +---------------+ +---------------+
18 * +---------------+ +---------------+ +---------------+
24 * +---------------+ +---------------+
26 * +---------------+ +---------------+
37 * - 823.4375 MHz
38 * - 783.36 MHz
39 * - 796.875 MHz
40 * - 816 MHz
41 * - 830.078125 MHz
[all …]
|
| /kernel/linux/linux-5.10/drivers/edac/ |
| D | pnd2_edac.c | 1 // SPDX-License-Identifier: GPL-2.0-only
32 #include <asm/intel-family.h>
109 #define SELECTOR_DISABLED (-1)
123 #define GET_BITFIELD(v, lo, hi) (((v) & GENMASK_ULL(hi, lo)) >> (lo)) argument
128 * side-band mailbox style interface in a hidden PCI device
166 ret = -EAGAIN; in _apl_rd_reg()
177 if (retries-- == 0) { in _apl_rd_reg()
178 ret = -EBUSY; in _apl_rd_reg()
214 struct b_cr_mchbar_lo_pci lo; in get_mem_ctrl_hub_base_addr() local
220 pci_read_config_dword(pdev, 0x48, (u32 *)&lo); in get_mem_ctrl_hub_base_addr()
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/ethernet/qlogic/qlcnic/ |
| D | qlcnic_init.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2009-2013 QLogic Corporation
89 recv_ctx = adapter->recv_ctx; in qlcnic_release_rx_buffers()
90 for (ring = 0; ring < adapter->max_rds_rings; ring++) { in qlcnic_release_rx_buffers()
91 rds_ring = &recv_ctx->rds_rings[ring]; in qlcnic_release_rx_buffers()
92 for (i = 0; i < rds_ring->num_desc; ++i) { in qlcnic_release_rx_buffers()
93 rx_buf = &(rds_ring->rx_buf_arr[i]); in qlcnic_release_rx_buffers()
94 if (rx_buf->skb == NULL) in qlcnic_release_rx_buffers()
97 pci_unmap_single(adapter->pdev, in qlcnic_release_rx_buffers()
98 rx_buf->dma, in qlcnic_release_rx_buffers()
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/ethernet/qlogic/qlcnic/ |
| D | qlcnic_init.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2009-2013 QLogic Corporation
89 recv_ctx = adapter->recv_ctx; in qlcnic_release_rx_buffers()
90 for (ring = 0; ring < adapter->max_rds_rings; ring++) { in qlcnic_release_rx_buffers()
91 rds_ring = &recv_ctx->rds_rings[ring]; in qlcnic_release_rx_buffers()
92 for (i = 0; i < rds_ring->num_desc; ++i) { in qlcnic_release_rx_buffers()
93 rx_buf = &(rds_ring->rx_buf_arr[i]); in qlcnic_release_rx_buffers()
94 if (rx_buf->skb == NULL) in qlcnic_release_rx_buffers()
97 dma_unmap_single(&adapter->pdev->dev, rx_buf->dma, in qlcnic_release_rx_buffers()
98 rds_ring->dma_size, DMA_FROM_DEVICE); in qlcnic_release_rx_buffers()
[all …]
|
| /kernel/linux/linux-6.6/drivers/edac/ |
| D | pnd2_edac.c | 1 // SPDX-License-Identifier: GPL-2.0-only
34 #include <asm/intel-family.h>
111 #define SELECTOR_DISABLED (-1)
125 #define GET_BITFIELD(v, lo, hi) (((v) & GENMASK_ULL(hi, lo)) >> (lo)) argument
130 * side-band mailbox style interface in a hidden PCI device
168 ret = -EAGAIN; in _apl_rd_reg()
179 if (retries-- == 0) { in _apl_rd_reg()
180 ret = -EBUSY; in _apl_rd_reg()
216 struct b_cr_mchbar_lo_pci lo; in get_mem_ctrl_hub_base_addr() local
222 pci_read_config_dword(pdev, 0x48, (u32 *)&lo); in get_mem_ctrl_hub_base_addr()
[all …]
|
| /kernel/linux/linux-6.6/drivers/crypto/caam/ |
| D | regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * CAAM hardware register-level view
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
15 #include <linux/io-64-nonatomic-hi-lo.h>
18 * Architecture-specific register access methods
20 * CAAM's bus-addressable registers are 64 bits internally.
21 * They have been wired to be safely accessible on 32-bit
24 * can be treated as two 32-bit entities, or finally (c) if they
25 * must be treated as a single 64-bit value, then this can safely
26 * be done with two 32-bit cycles.
[all …]
|
| /kernel/linux/linux-5.10/drivers/crypto/caam/ |
| D | regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * CAAM hardware register-level view
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
15 #include <linux/io-64-nonatomic-hi-lo.h>
18 * Architecture-specific register access methods
20 * CAAM's bus-addressable registers are 64 bits internally.
21 * They have been wired to be safely accessible on 32-bit
24 * can be treated as two 32-bit entities, or finally (c) if they
25 * must be treated as a single 64-bit value, then this can safely
26 * be done with two 32-bit cycles.
[all …]
|
| /kernel/linux/linux-6.6/drivers/dma/xilinx/ |
| D | xilinx_dma.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
11 * core that provides high-bandwidth direct memory access between memory
12 * and AXI4-Stream type video target peripherals. The core provides efficient
18 * registers are accessed through an AXI4-Lite slave interface.
21 * provides high-bandwidth one dimensional direct memory access between memory
22 * and AXI4-Stream target peripherals. It supports one receive and one
25 * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory
26 * Access (DMA) between a memory-mapped source address and a memory-mapped
30 * Xilinx IP that provides high-bandwidth direct memory access between
[all …]
|
| /kernel/linux/linux-5.10/drivers/dma/xilinx/ |
| D | xilinx_dma.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
11 * core that provides high-bandwidth direct memory access between memory
12 * and AXI4-Stream type video target peripherals. The core provides efficient
18 * registers are accessed through an AXI4-Lite slave interface.
21 * provides high-bandwidth one dimensional direct memory access between memory
22 * and AXI4-Stream target peripherals. It supports one receive and one
25 * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory
26 * Access (DMA) between a memory-mapped source address and a memory-mapped
30 * Xilinx IP that provides high-bandwidth direct memory access between
[all …]
|
| /kernel/linux/linux-5.10/drivers/scsi/qla4xxx/ |
| D | ql4_nx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2003-2013 QLogic Corporation
14 #include <linux/io-64-nonatomic-lo-hi.h>
40 if ((off < ha->first_page_group_end) && in qla4_8xxx_pci_base_offsetfset()
41 (off >= ha->first_page_group_start)) in qla4_8xxx_pci_base_offsetfset()
42 return (void __iomem *)(ha->nx_pcibase + off); in qla4_8xxx_pci_base_offsetfset()
363 ha->crb_win = CRB_HI(*off); in qla4_82xx_pci_set_crbwindow_2M()
364 writel(ha->crb_win, in qla4_82xx_pci_set_crbwindow_2M()
365 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); in qla4_82xx_pci_set_crbwindow_2M()
369 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); in qla4_82xx_pci_set_crbwindow_2M()
[all …]
|
| /kernel/linux/linux-6.6/drivers/scsi/qla4xxx/ |
| D | ql4_nx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2003-2013 QLogic Corporation
14 #include <linux/io-64-nonatomic-lo-hi.h>
40 if ((off < ha->first_page_group_end) && in qla4_8xxx_pci_base_offsetfset()
41 (off >= ha->first_page_group_start)) in qla4_8xxx_pci_base_offsetfset()
42 return (void __iomem *)(ha->nx_pcibase + off); in qla4_8xxx_pci_base_offsetfset()
363 ha->crb_win = CRB_HI(*off); in qla4_82xx_pci_set_crbwindow_2M()
364 writel(ha->crb_win, in qla4_82xx_pci_set_crbwindow_2M()
365 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); in qla4_82xx_pci_set_crbwindow_2M()
369 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); in qla4_82xx_pci_set_crbwindow_2M()
[all …]
|
| /kernel/linux/linux-6.6/drivers/scsi/qla2xxx/ |
| D | qla_nx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2003-2014 QLogic Corporation
8 #include <linux/io-64-nonatomic-lo-hi.h>
14 #define MASK(n) ((1ULL<<(n))-1)
340 [QLA8XXX_DEV_COLD] = "Cold/Re-init",
364 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_pci_set_crbwindow_2M()
366 ha->crb_win = CRB_HI(off_in); in qla82xx_pci_set_crbwindow_2M()
367 writel(ha->crb_win, CRB_WINDOW_2M + ha->nx_pcibase); in qla82xx_pci_set_crbwindow_2M()
372 win_read = rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase); in qla82xx_pci_set_crbwindow_2M()
373 if (win_read != ha->crb_win) { in qla82xx_pci_set_crbwindow_2M()
[all …]
|
| /kernel/linux/linux-5.10/drivers/scsi/qla2xxx/ |
| D | qla_nx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2003-2014 QLogic Corporation
8 #include <linux/io-64-nonatomic-lo-hi.h>
14 #define MASK(n) ((1ULL<<(n))-1)
364 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_pci_set_crbwindow_2M()
366 ha->crb_win = CRB_HI(off_in); in qla82xx_pci_set_crbwindow_2M()
367 writel(ha->crb_win, CRB_WINDOW_2M + ha->nx_pcibase); in qla82xx_pci_set_crbwindow_2M()
372 win_read = rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase); in qla82xx_pci_set_crbwindow_2M()
373 if (win_read != ha->crb_win) { in qla82xx_pci_set_crbwindow_2M()
377 __func__, ha->crb_win, win_read, off_in); in qla82xx_pci_set_crbwindow_2M()
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/ |
| D | i915_reg.h | 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
44 * registers that are defined solely for the use by function-like macros.
52 * should be defined using function-like macros.
58 * with underscore, followed by a function-like macro choosing the right
68 * function-like macros may be used to define bit fields, but do note that the
87 * Try to re-use existing register macro definitions. Only add new macros for
120 * REG_BIT() - Prepare a u32 bit value
121 * @__n: 0-based bit number
133 * REG_GENMASK() - Prepare a continuous u32 bitmask
134 * @__high: 0-based high bit
[all …]
|