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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/
Drockchip,rk3399-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-ep.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie-ep
22 reg-names:
24 - const: apb-base
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Dcdns-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: cdns-pcie.yaml#
14 - $ref: pci-ep.yaml#
17 cdns,max-outbound-regions:
18 description: maximum number of outbound regions
Dcdns-pcie-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: cdns-pcie.yaml#
17 cdns,max-outbound-regions:
18 description: maximum number of outbound regions
25 cdns,no-bar-match-nbits:
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Dcdns,cdns-pcie-ep.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: cdns-pcie-ep.yaml#
17 const: cdns,cdns-pcie-ep
22 reg-names:
24 - const: reg
25 - const: mem
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Dbaikal,bt1-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 PCIe Root Port Controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 Embedded into Baikal-T1 SoC Root Complex controller with a single port
14 activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured
18 performed by software. There four in- and four outbound iATU regions
22 - $ref: /schemas/pci/snps,dw-pcie.yaml#
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Dsnps,dw-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dcdns-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/pci/cdns-pcie-ep.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: "cdns-pcie.yaml#"
16 cdns,max-outbound-regions:
17 description: maximum number of outbound regions
24 - cdns,max-outbound-regions
Drockchip-pcie-ep.txt4 - compatible: Should contain "rockchip,rk3399-pcie-ep"
5 - reg: Two register ranges as listed in the reg-names property
6 - reg-names: Must include the following names
7 - "apb-base"
8 - "mem-base"
9 - clocks: Must contain an entry for each entry in clock-names.
10 See ../clocks/clock-bindings.txt for details.
11 - clock-names: Must include the following entries:
12 - "aclk"
13 - "aclk-perf"
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Dti,j721e-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: "cdns-pcie-ep.yaml#"
19 - ti,j721e-pcie-ep
24 reg-names:
26 - const: intd_cfg
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Dcdns-pcie-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: "/schemas/pci/pci-bus.yaml#"
14 - $ref: "cdns-pcie.yaml#"
17 cdns,max-outbound-regions:
18 description: maximum number of outbound regions
25 cdns,no-bar-match-nbits:
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Dcdns,cdns-pcie-ep.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: "cdns-pcie-ep.yaml#"
14 - $ref: "pci-ep.yaml#"
18 const: cdns,cdns-pcie-ep
23 reg-names:
25 - const: reg
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Ddesignware-pcie.txt4 - compatible:
5 "snps,dw-pcie" for RC mode;
6 "snps,dw-pcie-ep" for EP mode;
7 - reg: For designware cores version < 4.80 contains the configuration
10 - reg-names: Must be "config" for the PCIe configuration space and "atu" for
15 - #address-cells: set to <3>
16 - #size-cells: set to <2>
17 - device_type: set to "pci"
18 - ranges: ranges for the PCI memory and I/O regions
19 - #interrupt-cells: set to <1>
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/kernel/linux/linux-5.10/drivers/pci/controller/
Dpcie-rockchip-ep.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
15 #include <linux/pci-epc.h>
17 #include <linux/pci-epf.h>
20 #include "pcie-rockchip.h"
23 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
26 * @max_regions: maximum number of regions supported by hardware
27 * @ob_region_map: bitmask of mapped outbound regions
28 * @ob_addr: base addresses in the AXI bus where the outbound regions start
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Dpcie-iproc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
16 #include <linux/irqchip/arm-gic-v3.h>
24 #include "pcie-iproc.h"
70 /* derive the enum index of the outbound/inbound mapping registers */
74 * Maximum number of outbound mapping window sizes that can be supported by any
99 * iProc PCIe outbound mapping controller specific parameters
101 * @window_sizes: list of supported outbound mapping window sizes in MB
102 * @nr_sizes: number of supported outbound mapping window sizes
169 * @imap_addr_offset: register offset between the upper and lower 32-bit
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/kernel/linux/linux-6.6/drivers/pci/controller/
Dpcie-rockchip-ep.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
15 #include <linux/pci-epc.h>
17 #include <linux/pci-epf.h>
20 #include "pcie-rockchip.h"
23 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
26 * @max_regions: maximum number of regions supported by hardware
27 * @ob_region_map: bitmask of mapped outbound regions
28 * @ob_addr: base addresses in the AXI bus where the outbound regions start
[all …]
Dpcie-iproc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/pci-ecam.h>
17 #include <linux/irqchip/arm-gic-v3.h>
24 #include "pcie-iproc.h"
62 /* derive the enum index of the outbound/inbound mapping registers */
66 * Maximum number of outbound mapping window sizes that can be supported by any
91 * struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific
93 * @window_sizes: list of supported outbound mapping window sizes in MB
94 * @nr_sizes: number of supported outbound mapping window sizes
[all …]
/kernel/linux/linux-5.10/drivers/scsi/pm8001/
Dpm8001_defs.h2 * PMC-Sierra 8001/8081/8088/8089 SAS/SATA based host adapters driver
4 * Copyright (c) 2008-2009 USI Co., Ltd.
18 * 3. Neither the names of the above-listed copyright holders nor the names
68 DATA_DIR_OUT = 0x02, /* OUTBOUND */
77 /* driver compile-time configuration */
78 #define PM8001_MAX_CCB 1024 /* max ccbs supported */
84 /* Inbound/Outbound queue size */
89 #define PM8001_MAX_PHYS 16 /* max. possible phys */
90 #define PM8001_MAX_PORTS 16 /* max. possible ports */
91 #define PM8001_MAX_DEVICES 2048 /* max supported device */
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/kernel/linux/linux-6.6/drivers/scsi/pm8001/
Dpm8001_defs.h2 * PMC-Sierra 8001/8081/8088/8089 SAS/SATA based host adapters driver
4 * Copyright (c) 2008-2009 USI Co., Ltd.
18 * 3. Neither the names of the above-listed copyright holders nor the names
68 DATA_DIR_OUT = 0x02, /* OUTBOUND */
77 /* driver compile-time configuration */
78 #define PM8001_MAX_CCB 1024 /* max ccbs supported */
84 /* Inbound/Outbound queue size */
89 #define PM8001_MAX_PHYS 16 /* max. possible phys */
90 #define PM8001_MAX_PORTS 16 /* max. possible ports */
91 #define PM8001_MAX_DEVICES 2048 /* max supported device */
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/kernel/linux/linux-5.10/drivers/pci/controller/cadence/
Dpcie-cadence-ep.c1 // SPDX-License-Identifier: GPL-2.0
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
9 #include <linux/pci-epc.h>
13 #include "pcie-cadence.h"
23 struct cdns_pcie *pcie = &ep->pcie; in cdns_pcie_ep_write_header()
25 cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); in cdns_pcie_ep_write_header()
26 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid); in cdns_pcie_ep_write_header()
27 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code); in cdns_pcie_ep_write_header()
29 hdr->subclass_code | hdr->baseclass_code << 8); in cdns_pcie_ep_write_header()
31 hdr->cache_line_size); in cdns_pcie_ep_write_header()
[all …]
/kernel/linux/linux-6.6/drivers/rapidio/devices/
Dtsi721.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * RapidIO mport driver for Tsi721 PCIExpress-to-SRIO bridge
19 #include <linux/dma-mapping.h>
32 static int pcie_mrrs = -1;
47 * tsi721_lcread - read from local SREP config space
55 * success or %-EINVAL on failure.
60 struct tsi721_device *priv = mport->priv; in tsi721_lcread()
63 return -EINVAL; /* only 32-bit access is supported */ in tsi721_lcread()
65 *data = ioread32(priv->regs + offset); in tsi721_lcread()
71 * tsi721_lcwrite - write into local SREP config space
[all …]
/kernel/linux/linux-5.10/drivers/rapidio/devices/
Dtsi721.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * RapidIO mport driver for Tsi721 PCIExpress-to-SRIO bridge
19 #include <linux/dma-mapping.h>
32 static int pcie_mrrs = -1;
47 * tsi721_lcread - read from local SREP config space
55 * success or %-EINVAL on failure.
60 struct tsi721_device *priv = mport->priv; in tsi721_lcread()
63 return -EINVAL; /* only 32-bit access is supported */ in tsi721_lcread()
65 *data = ioread32(priv->regs + offset); in tsi721_lcread()
71 * tsi721_lcwrite - write into local SREP config space
[all …]
/kernel/linux/linux-5.10/include/linux/
Drio.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
24 #define RIO_NO_HOPCOUNT -1
56 * 0 RapidIO outbound doorbells
57 * 1-15 RapidIO memory regions
63 * 2 RapidIO outbound mailboxes
89 * struct rio_switch - RIO switch info
92 * @port_ok: Status of each port (one bit per port) - OK=1 or UNINIT=0
93 * @ops: pointer to switch-specific operations
95 * @nextdev: Array of per-port pointers to the next attached device
107 * struct rio_switch_ops - Per-switch operations
[all …]
/kernel/linux/linux-6.6/include/linux/
Drio.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
24 #define RIO_NO_HOPCOUNT -1
56 * 0 RapidIO outbound doorbells
57 * 1-15 RapidIO memory regions
63 * 2 RapidIO outbound mailboxes
89 * struct rio_switch - RIO switch info
92 * @port_ok: Status of each port (one bit per port) - OK=1 or UNINIT=0
93 * @ops: pointer to switch-specific operations
95 * @nextdev: Array of per-port pointers to the next attached device
107 * struct rio_switch_ops - Per-switch operations
[all …]
/kernel/linux/linux-6.6/drivers/pci/controller/cadence/
Dpcie-cadence-ep.c1 // SPDX-License-Identifier: GPL-2.0
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
9 #include <linux/pci-epc.h>
13 #include "pcie-cadence.h"
29 fn = fn + first_vf_offset + ((vfn - 1) * stride); in cdns_pcie_get_fn_from_vfn()
39 struct cdns_pcie *pcie = &ep->pcie; in cdns_pcie_ep_write_header()
43 dev_err(&epc->dev, "Only Virtual Function #1 has deviceID\n"); in cdns_pcie_ep_write_header()
44 return -EINVAL; in cdns_pcie_ep_write_header()
47 cdns_pcie_ep_fn_writew(pcie, fn, reg, hdr->deviceid); in cdns_pcie_ep_write_header()
51 cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); in cdns_pcie_ep_write_header()
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/
Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/mux/ti-serdes.h>
12 cmn_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
18 cmn_refclk1: clock-cmnrefclk1 {
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