| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/misc/ |
| D | qcom,fastrpc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 The FastRPC implements an IPC (Inter-Processor Communication)
25 - adsp
26 - mdsp
27 - sdsp
28 - cdsp
30 memory-region:
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| /kernel/linux/linux-5.10/drivers/iommu/ |
| D | ipmmu-vmsa.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * IOMMU API for Renesas VMSA-compatible IPMMU
6 * Copyright (C) 2014-2020 Renesas Electronics Corporation
11 #include <linux/dma-iommu.h>
12 #include <linux/dma-mapping.h>
18 #include <linux/io-pgtable.h>
30 #include <asm/dma-iommu.h>
33 #define arm_iommu_attach_device(...) -ENODEV
39 #define IPMMU_CTX_INVALID -1
96 /* -----------------------------------------------------------------------------
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| /kernel/linux/linux-6.6/drivers/iommu/ |
| D | ipmmu-vmsa.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * IOMMU API for Renesas VMSA-compatible IPMMU
6 * Copyright (C) 2014-2020 Renesas Electronics Corporation
11 #include <linux/dma-mapping.h>
18 #include <linux/io-pgtable.h>
29 #include <asm/dma-iommu.h>
32 #define arm_iommu_attach_device(...) -ENODEV
37 #define IPMMU_CTX_INVALID -1
94 /* -----------------------------------------------------------------------------
101 #define IMCTR 0x0000 /* R-Car Gen2/3 */
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| /kernel/linux/linux-5.10/drivers/s390/crypto/ |
| D | zcrypt_ccamisc.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
17 #define TOKTYPE_NON_CCA 0x00 /* Non-CCA key token */
41 /* inside view of a CCA secure key token (only type 0x01 version 0x04) */
81 /* AES-128 512 640 */
82 /* AES-192 576 640 */
83 /* AES-256 640 640 */
97 /* inside view of an CCA secure ECC private key */
107 u8 htype; /* hash method, 0x02 for SHA-256 */
133 * Simple check if the token is a valid CCA secure AES data key
141 * Simple check if the token is a valid CCA secure AES cipher key
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| /kernel/linux/linux-6.6/Documentation/trace/coresight/ |
| D | coresight-cpu-debug.rst | 9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
20 to sample CPU program counter, secure state and exception level, etc; usually
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
32 registers to decide if sample-based profiling is implemented or not. On some
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| /kernel/linux/linux-5.10/Documentation/trace/coresight/ |
| D | coresight-cpu-debug.rst | 9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
20 to sample CPU program counter, secure state and exception level, etc; usually
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
32 registers to decide if sample-based profiling is implemented or not. On some
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mailbox/ |
| D | arm,mhu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jassi Brar <jaswinder.singh@linaro.org>
13 The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has 3
19 be a 'Secure' resource, hence can't be used by Linux running NS.
22 interrupt signal using a 32-bit register, with all 32-bits logically ORed
28 interrupt. Each of the 32-bits can be used as "doorbell" to alert the remote
37 - arm,mhu
38 - arm,mhu-doorbell
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| /kernel/linux/linux-6.6/drivers/s390/crypto/ |
| D | zcrypt_ccamisc.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
17 #define TOKTYPE_NON_CCA 0x00 /* Non-CCA key token */
41 /* inside view of a CCA secure key token (only type 0x01 version 0x04) */
81 /* AES-128 512 640 */
82 /* AES-192 576 640 */
83 /* AES-256 640 640 */
97 /* inside view of an CCA secure ECC private key */
107 u8 htype; /* hash method, 0x02 for SHA-256 */
133 * Simple check if the token is a valid CCA secure AES data key
141 * Simple check if the token is a valid CCA secure AES cipher key
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| D | pkey_api.c | 1 // SPDX-License-Identifier: GPL-2.0
168 return -EINVAL; in pkey_clr2protkey()
174 return -EINVAL; in pkey_clr2protkey()
181 return -ENODEV; in pkey_clr2protkey()
186 return -ENODEV; in pkey_clr2protkey()
205 * Find card and transform secure key into protected key.
211 u16 cardnr, domain; in pkey_skey2pkey() local
224 rc = cca_findcard(key, &cardnr, &domain, verify); in pkey_skey2pkey()
229 switch (hdr->version) { in pkey_skey2pkey()
231 rc = cca_sec2protkey(cardnr, domain, key, in pkey_skey2pkey()
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| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-gic-v3.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
23 #include <linux/irqchip/arm-gic-common.h>
24 #include <linux/irqchip/arm-gic-v3.h>
25 #include <linux/irqchip/irq-partition-percpu.h>
32 #include "irq-gic-common.h"
53 struct irq_domain *domain; member
71 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
75 * When security is enabled, non-secure priority values from the (re)distributor
79 * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure
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| /kernel/linux/linux-6.6/drivers/irqchip/ |
| D | irq-gic-v3.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
24 #include <linux/irqchip/arm-gic-common.h>
25 #include <linux/irqchip/arm-gic-v3.h>
26 #include <linux/irqchip/irq-partition-percpu.h>
29 #include <linux/arm-smccc.h>
36 #include "irq-gic-common.h"
59 struct irq_domain *domain; member
83 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
87 * When security is enabled, non-secure priority values from the (re)distributor
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | fujitsu,mb86s70-crg11.txt | 2 -----------------------------------
5 - compatible : Shall contain "fujitsu,mb86s70-crg11"
6 - #clock-cells : Shall be 3 {cntrlr domain port}
13 compatible = "fujitsu,mb86s70-crg11";
14 #clock-cells = <3>;
18 #mbox-cells = <1>;
21 interrupts = <0 36 4>, /* LP Non-Sec */
22 <0 35 4>, /* HP Non-Sec */
23 <0 37 4>; /* Secure */
24 clocks = <&clock 0 2 1>; /* Cntrlr:0 Domain:2 Port:1 */
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | fujitsu,mb86s70-crg11.txt | 2 -----------------------------------
5 - compatible : Shall contain "fujitsu,mb86s70-crg11"
6 - #clock-cells : Shall be 3 {cntrlr domain port}
13 compatible = "fujitsu,mb86s70-crg11";
14 #clock-cells = <3>;
18 #mbox-cells = <1>;
21 interrupts = <0 36 4>, /* LP Non-Sec */
22 <0 35 4>, /* HP Non-Sec */
23 <0 37 4>; /* Secure */
24 clocks = <&clock 0 2 1>; /* Cntrlr:0 Domain:2 Port:1 */
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24 - items:
25 - enum:
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| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | omap-wakeupgen.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * implemented in MPU always ON power domain. During normal operation,
28 #include "omap-wakeupgen.h"
29 #include "omap-secure.h"
32 #include "omap4-sar-layout.h"
138 _wakeupgen_clear(d->hwirq, irq_target_cpu[d->hwirq]); in wakeupgen_mask()
151 _wakeupgen_set(d->hwirq, irq_target_cpu[d->hwirq]); in wakeupgen_unmask()
179 if (inverted && d->hwirq != SYS_NIRQ1_EXT_SYS_IRQ_1 && in wakeupgen_irq_set_type()
180 d->hwirq != SYS_NIRQ2_EXT_SYS_IRQ_2) in wakeupgen_irq_set_type()
182 d->hwirq); in wakeupgen_irq_set_type()
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| /kernel/linux/linux-6.6/arch/arm/mach-omap2/ |
| D | omap-wakeupgen.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * implemented in MPU always ON power domain. During normal operation,
28 #include "omap-wakeupgen.h"
29 #include "omap-secure.h"
32 #include "omap4-sar-layout.h"
138 _wakeupgen_clear(d->hwirq, irq_target_cpu[d->hwirq]); in wakeupgen_mask()
151 _wakeupgen_set(d->hwirq, irq_target_cpu[d->hwirq]); in wakeupgen_unmask()
179 if (inverted && d->hwirq != SYS_NIRQ1_EXT_SYS_IRQ_1 && in wakeupgen_irq_set_type()
180 d->hwirq != SYS_NIRQ2_EXT_SYS_IRQ_2) in wakeupgen_irq_set_type()
182 d->hwirq); in wakeupgen_irq_set_type()
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| /kernel/linux/linux-6.6/drivers/rtc/ |
| D | rtc-mxc_v2.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2004-2011 Freescale Semiconductor, Inc.
21 #define SRTC_LPCR_NSA BIT(11) /* lp non secure access */
22 #define SRTC_LPCR_NVE BIT(14) /* lp non valid state exit bit */
26 #define SRTC_LPSR_NVES BIT(14) /* lp non-valid state exit status */
29 #define SRTC_LPSCMR 0x00 /* LP Secure Counter MSB Reg */
30 #define SRTC_LPSCLR 0x04 /* LP Secure Counter LSB Reg */
31 #define SRTC_LPSAR 0x08 /* LP Secure Alarm Reg */
49 * To take care of the asynchronous CKIL clock, all writes from the IP domain
50 * will be synchronized to the CKIL domain.
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| /kernel/linux/linux-5.10/drivers/rtc/ |
| D | rtc-mxc_v2.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2004-2011 Freescale Semiconductor, Inc.
21 #define SRTC_LPCR_NSA BIT(11) /* lp non secure access */
22 #define SRTC_LPCR_NVE BIT(14) /* lp non valid state exit bit */
26 #define SRTC_LPSR_NVES BIT(14) /* lp non-valid state exit status */
29 #define SRTC_LPSCMR 0x00 /* LP Secure Counter MSB Reg */
30 #define SRTC_LPSCLR 0x04 /* LP Secure Counter LSB Reg */
31 #define SRTC_LPSAR 0x08 /* LP Secure Alarm Reg */
49 * To take care of the asynchronous CKIL clock, all writes from the IP domain
50 * will be synchronized to the CKIL domain.
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24 - items:
25 - const: arm,cortex-a15-timer
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| /kernel/linux/linux-6.6/arch/arm/mach-ux500/ |
| D | cpu-db8500.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2008-2009 ST-Ericsson SA
14 #include <linux/irqchip/arm-gic.h>
15 #include <linux/mfd/dbx500-prcmu.h>
16 #include <linux/platform_data/arm-ux500-pm.h>
25 #include <asm/hardware/cache-l2x0.h>
35 np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); in ux500_l2x0_unlock()
39 return -ENODEV; in ux500_l2x0_unlock()
42 * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions in ux500_l2x0_unlock()
61 * We can't write to secure registers as we are in non-secure in ux500_l2c310_write_sec()
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| /kernel/linux/linux-5.10/arch/arm/mach-ux500/ |
| D | cpu-db8500.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2008-2009 ST-Ericsson SA
14 #include <linux/irqchip/arm-gic.h>
15 #include <linux/mfd/dbx500-prcmu.h>
16 #include <linux/platform_data/arm-ux500-pm.h>
25 #include <asm/hardware/cache-l2x0.h>
29 #include "db8500-regs.h"
38 np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); in ux500_l2x0_unlock()
42 return -ENODEV; in ux500_l2x0_unlock()
45 * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions in ux500_l2x0_unlock()
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| /kernel/linux/linux-6.6/Documentation/arch/s390/ |
| D | vfio-ap.rst | 13 The AP adapter cards are exposed via the AP bus. The motivation for vfio-ap
45 sub-directory::
50 * AP domain
53 depending upon the adapter type and hardware configuration. A domain is
54 identified by a number from 0 to 255; however, the maximum domain number is
55 determined by machine model and/or adapter type.. A domain can be thought of
57 domain can be configured with a secure private key used for clear key
58 encryption. A domain is classified in one of two ways depending upon how it
65 usage domain; for example, to set the secure private key for the control
66 domain.
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| /kernel/linux/linux-5.10/Documentation/admin-guide/ |
| D | thunderbolt.rst | 1 .. SPDX-License-Identifier: GPL-2.0
25 -----------------------------------
27 should be a userspace tool that handles all the low-level details, keeps
31 found in ``Documentation/ABI/testing/sysfs-bus-thunderbolt``.
35 ``/etc/udev/rules.d/99-local.rules``::
63 secure
65 addition to UUID the device (if it supports secure connect) is sent
82 the Thunderbolt domain the host controller manages. There is typically
83 one domain per Thunderbolt host controller.
85 If the security level reads as ``user`` or ``secure`` the connected
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|
| /kernel/linux/linux-6.6/Documentation/admin-guide/ |
| D | thunderbolt.rst | 1 .. SPDX-License-Identifier: GPL-2.0
25 -----------------------------------
27 should be a userspace tool that handles all the low-level details, keeps
31 found in ``Documentation/ABI/testing/sysfs-bus-thunderbolt``.
35 ``/etc/udev/rules.d/99-local.rules``::
66 secure
68 addition to UUID the device (if it supports secure connect) is sent
89 the Thunderbolt domain the host controller manages. There is typically
90 one domain per Thunderbolt host controller.
92 If the security level reads as ``user`` or ``secure`` the connected
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| /kernel/linux/linux-6.6/Documentation/process/ |
| D | embargoed-hardware-issues.rst | 7 -----
23 -------
31 Linux kernel security team (:ref:`Documentation/admin-guide/
34 The team can be contacted by email at <hardware-security@kernel.org>. This
43 - PGP: https://www.kernel.org/static/files/hardware-security.asc
44 - S/MIME: https://www.kernel.org/static/files/hardware-security.crt
55 - Linus Torvalds (Linux Foundation Fellow)
56 - Greg Kroah-Hartman (Linux Foundation Fellow)
57 - Thomas Gleixner (Linux Foundation Fellow)
59 Operation of mailing-lists
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|