Searched +full:omap4 +full:- +full:mailbox (Results 1 – 25 of 60) sorted by relevance
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mailbox/ |
| D | ti,omap-mailbox.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: TI OMAP2+ and K3 Mailbox devices 10 - Suman Anna <s-anna@ti.com> 13 The OMAP Mailbox hardware facilitates communication between different 14 processors using a queued mailbox interrupt mechanism. The IP block is 19 Each mailbox IP block/cluster has a certain number of h/w fifo queues and 35 lines can also be routed to different processor sub-systems on DRA7xx as they [all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/remoteproc/ |
| D | ti,omap-remoteproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: OMAP4+ Remoteproc Devices 10 - Suman Anna <s-anna@ti.com> 13 The OMAP family of SoCs usually have one or more slave processor sub-systems 14 that are used to offload some of the processor-intensive tasks, or to manage 17 The processor cores in the sub-system are usually behind an IOMMU, and may 18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2 [all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/remoteproc/ |
| D | ti,omap-remoteproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: OMAP4+ Remoteproc Devices 10 - Suman Anna <s-anna@ti.com> 13 The OMAP family of SoCs usually have one or more slave processor sub-systems 14 that are used to offload some of the processor-intensive tasks, or to manage 17 The processor cores in the sub-system are usually behind an IOMMU, and may 18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2 [all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mailbox/ |
| D | omap-mailbox.txt | 1 OMAP2+ and K3 Mailbox 4 The OMAP mailbox hardware facilitates communication between different processors 5 using a queued mailbox interrupt mechanism. The IP block is external to the 10 Each mailbox IP block/cluster has a certain number of h/w fifo queues and output 25 routed to different processor sub-systems on DRA7xx as they are routed through 32 Mailbox Device Node: 34 A Mailbox device node is used to represent a Mailbox IP instance/cluster within 35 a SoC. The sub-mailboxes are represented as child nodes of this parent node. 38 -------------------- 39 - compatible: Should be one of the following, [all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/ti/ |
| D | k3-j784s4-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 10 compatible = "mmio-sram"; 12 #address-cells = <1>; 13 #size-cells = <1>; 16 atf-sram@0 { 20 tifs-sram@1f0000 { 24 l3cache-sram@200000 { 29 gic500: interrupt-controller@1800000 { 30 compatible = "arm,gic-v3"; [all …]
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| D | k3-j7200-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 9 serdes_refclk: serdes-refclk { 10 #clock-cells = <0>; 11 compatible = "fixed-clock"; 17 compatible = "mmio-sram"; 19 #address-cells = <1>; 20 #size-cells = <1>; 23 atf-sram@0 { 28 scm_conf: scm-conf@100000 { [all …]
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| D | k3-j721s2-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 8 #include <dt-bindings/phy/phy-cadence.h> 9 #include <dt-bindings/phy/phy-ti.h> 12 serdes_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 21 compatible = "mmio-sram"; 23 #address-cells = <1>; [all …]
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| D | k3-am62a-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 10 compatible = "mmio-sram"; 12 #address-cells = <1>; 13 #size-cells = <1>; 17 gic500: interrupt-controller@1800000 { 18 compatible = "arm,gic-v3"; 24 #address-cells = <2>; 25 #size-cells = <2>; 27 #interrupt-cells = <3>; [all …]
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| D | k3-am65-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ 7 #include <dt-bindings/phy/phy-am654-serdes.h> 11 compatible = "mmio-sram"; 13 #address-cells = <1>; 14 #size-cells = <1>; 17 atf-sram@0 { 21 sysfw-sram@f0000 { 25 l3cache-sram@100000 { 30 gic500: interrupt-controller@1800000 { [all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/ |
| D | k3-am65-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ 7 #include <dt-bindings/phy/phy-am654-serdes.h> 11 compatible = "mmio-sram"; 13 #address-cells = <1>; 14 #size-cells = <1>; 17 atf-sram@0 { 21 sysfw-sram@f0000 { 25 l3cache-sram@100000 { 30 gic500: interrupt-controller@1800000 { [all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/ |
| D | dm816x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 #include <dt-bindings/bus/ti-sysc.h> 4 #include <dt-bindings/clock/dm816.h> 5 #include <dt-bindings/gpio/gpio.h> 6 #include <dt-bindings/pinctrl/omap.h> 10 interrupt-parent = <&intc>; 11 #address-cells = <1>; 12 #size-cells = <1>; 26 #address-cells = <1>; 27 #size-cells = <0>; [all …]
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| D | dra7-l4.dtsi | 2 compatible = "ti,dra7-l4-cfg", "simple-pm-bus"; 3 power-domains = <&prm_coreaon>; 5 clock-names = "fck"; 9 reg-names = "ap", "la", "ia0"; 10 #address-cells = <1>; 11 #size-cells = <1>; 15 dma-ranges; 18 compatible = "simple-pm-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; [all …]
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| D | omap4.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ 6 #include <dt-bindings/bus/ti-sysc.h> 7 #include <dt-bindings/clock/omap4.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/pinctrl/omap.h> 11 #include <dt-bindings/clock/omap4.h> 14 compatible = "ti,omap4430", "ti,omap4"; 15 interrupt-parent = <&wakeupgen>; [all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | dm816x.dtsi | 7 #include <dt-bindings/bus/ti-sysc.h> 8 #include <dt-bindings/clock/dm816.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/pinctrl/omap.h> 14 interrupt-parent = <&intc>; 15 #address-cells = <1>; 16 #size-cells = <1>; 30 #address-cells = <1>; 31 #size-cells = <0>; 33 compatible = "arm,cortex-a8"; [all …]
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| D | dra7-l4.dtsi | 2 compatible = "ti,dra7-l4-cfg", "simple-bus"; 6 reg-names = "ap", "la", "ia0"; 7 #address-cells = <1>; 8 #size-cells = <1>; 14 compatible = "simple-bus"; 15 #address-cells = <1>; 16 #size-cells = <1>; 47 target-module@2000 { /* 0x4a002000, ap 3 08.0 */ 48 compatible = "ti,sysc-omap4", "ti,sysc"; 50 reg-names = "rev"; [all …]
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| D | omap4.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ 6 #include <dt-bindings/bus/ti-sysc.h> 7 #include <dt-bindings/clock/omap4.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/pinctrl/omap.h> 11 #include <dt-bindings/clock/omap4.h> 14 compatible = "ti,omap4430", "ti,omap4"; 15 interrupt-parent = <&wakeupgen>; [all …]
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| /kernel/linux/linux-6.6/drivers/phy/ti/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 58 the mailbox. The mailbox is present only in omap4 and the register to 59 power on the USB2 PHY is present in OMAP4 and OMAP5. OMAP5 has an
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| /kernel/linux/linux-5.10/drivers/phy/ti/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 58 the mailbox. The mailbox is present only in omap4 and the register to 59 power on the USB2 PHY is present in OMAP4 and OMAP5. OMAP5 has an
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| /kernel/linux/linux-5.10/drivers/remoteproc/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 41 This can be either built-in or a loadable module. 58 select MAILBOX 62 and DSP on OMAP4) via the remote processor framework. 64 Currently only supported on OMAP4. 67 use-cases to run on your platform (multimedia codecs are 92 Required for Suspend-to-RAM on AM33xx and AM43xx SoCs. Also needed 98 tristate "DA8xx/OMAP-L13x remoteproc support" 102 Say y here to support DA8xx/OMAP-L13x remote processors via the 106 use-cases to run on your platform (multimedia codecs are [all …]
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| /kernel/linux/linux-6.6/drivers/remoteproc/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 30 select MAILBOX 41 select MAILBOX 54 This can be either built-in or a loadable module. 71 select MAILBOX 75 and DSP on OMAP4) via the remote processor framework. 77 Currently only supported on OMAP4. 80 use-cases to run on your platform (multimedia codecs are 105 Required for Suspend-to-RAM on AM33xx and AM43xx SoCs. Also needed 111 tristate "DA8xx/OMAP-L13x remoteproc support" [all …]
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| /kernel/linux/linux-5.10/drivers/mailbox/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 2 menuconfig MAILBOX config 3 bool "Mailbox Hardware Support" 5 Mailbox is a framework to control hardware communication between 6 on-chip processors through queued messages and interrupt driven 9 if MAILBOX 12 tristate "ARM MHU Mailbox" 16 The controller has 3 mailbox channels, the last of which can be 20 tristate "i.MX Mailbox" 23 Mailbox implementation for i.MX Messaging Unit (MU). [all …]
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| /kernel/linux/linux-6.6/arch/arm/mach-omap2/ |
| D | omap_hwmod_81xx_data.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/ 11 #include <linux/platform_data/hsmmc-omap.h> 25 * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS" 78 #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE) 79 #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE) 80 #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE) 81 #define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE) 82 #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE) 83 #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE) [all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/ |
| D | omap-usb.txt | 4 - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb" 5 - ti,hwmods : must be "usb_otg_hs" 6 - multipoint : Should be "1" indicating the musb controller supports 7 multipoint. This is a MUSB configuration-specific setting. 8 - num-eps : Specifies the number of endpoints. This is also a 9 MUSB configuration-specific setting. Should be set to "16" 10 - ram-bits : Specifies the ram address size. Should be set to "12" 11 - interface-type : This is a board specific setting to describe the type of 14 - mode : Should be "3" to represent OTG. "1" signifies HOST and "2" 16 - power : Should be "50". This signifies the controller can supply up to [all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/ |
| D | omap-usb.txt | 4 - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb" 5 - ti,hwmods : must be "usb_otg_hs" 6 - multipoint : Should be "1" indicating the musb controller supports 7 multipoint. This is a MUSB configuration-specific setting. 8 - num-eps : Specifies the number of endpoints. This is also a 9 MUSB configuration-specific setting. Should be set to "16" 10 - ram-bits : Specifies the ram address size. Should be set to "12" 11 - interface-type : This is a board specific setting to describe the type of 14 - mode : Should be "3" to represent OTG. "1" signifies HOST and "2" 16 - power : Should be "50". This signifies the controller can supply up to [all …]
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| /kernel/linux/linux-6.6/drivers/mailbox/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 2 menuconfig MAILBOX config 3 bool "Mailbox Hardware Support" 5 Mailbox is a framework to control hardware communication between 6 on-chip processors through queued messages and interrupt driven 9 if MAILBOX 12 tristate "Apple Mailbox driver" 16 Apple SoCs have various co-processors required for certain 18 driver adds support for the mailbox controller used to 24 tristate "ARM MHU Mailbox" [all …]
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