1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM6 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy-am654-serdes.h> 8 9&cbass_main { 10 msmc_ram: sram@70000000 { 11 compatible = "mmio-sram"; 12 reg = <0x0 0x70000000 0x0 0x200000>; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 ranges = <0x0 0x0 0x70000000 0x200000>; 16 17 atf-sram@0 { 18 reg = <0x0 0x20000>; 19 }; 20 21 sysfw-sram@f0000 { 22 reg = <0xf0000 0x10000>; 23 }; 24 25 l3cache-sram@100000 { 26 reg = <0x100000 0x100000>; 27 }; 28 }; 29 30 gic500: interrupt-controller@1800000 { 31 compatible = "arm,gic-v3"; 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 #interrupt-cells = <3>; 36 interrupt-controller; 37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 38 <0x00 0x01880000 0x00 0x90000>, /* GICR */ 39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 41 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 42 /* 43 * vcpumntirq: 44 * virtual CPU interface maintenance interrupt 45 */ 46 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 47 48 gic_its: msi-controller@1820000 { 49 compatible = "arm,gic-v3-its"; 50 reg = <0x00 0x01820000 0x00 0x10000>; 51 socionext,synquacer-pre-its = <0x1000000 0x400000>; 52 msi-controller; 53 #msi-cells = <1>; 54 }; 55 }; 56 57 serdes0: serdes@900000 { 58 compatible = "ti,phy-am654-serdes"; 59 reg = <0x0 0x900000 0x0 0x2000>; 60 reg-names = "serdes"; 61 #phy-cells = <2>; 62 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 63 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>; 64 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk"; 65 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; 66 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; 67 ti,serdes-clk = <&serdes0_clk>; 68 #clock-cells = <1>; 69 mux-controls = <&serdes_mux 0>; 70 }; 71 72 serdes1: serdes@910000 { 73 compatible = "ti,phy-am654-serdes"; 74 reg = <0x0 0x910000 0x0 0x2000>; 75 reg-names = "serdes"; 76 #phy-cells = <2>; 77 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 78 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>; 79 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk"; 80 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>; 81 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>; 82 ti,serdes-clk = <&serdes1_clk>; 83 #clock-cells = <1>; 84 mux-controls = <&serdes_mux 1>; 85 }; 86 87 main_uart0: serial@2800000 { 88 compatible = "ti,am654-uart"; 89 reg = <0x00 0x02800000 0x00 0x100>; 90 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 91 clock-frequency = <48000000>; 92 current-speed = <115200>; 93 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 94 status = "disabled"; 95 }; 96 97 main_uart1: serial@2810000 { 98 compatible = "ti,am654-uart"; 99 reg = <0x00 0x02810000 0x00 0x100>; 100 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 101 clock-frequency = <48000000>; 102 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 103 status = "disabled"; 104 }; 105 106 main_uart2: serial@2820000 { 107 compatible = "ti,am654-uart"; 108 reg = <0x00 0x02820000 0x00 0x100>; 109 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 110 clock-frequency = <48000000>; 111 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 112 status = "disabled"; 113 }; 114 115 crypto: crypto@4e00000 { 116 compatible = "ti,am654-sa2ul"; 117 reg = <0x0 0x4e00000 0x0 0x1200>; 118 power-domains = <&k3_pds 136 TI_SCI_PD_SHARED>; 119 #address-cells = <2>; 120 #size-cells = <2>; 121 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 122 123 dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>, 124 <&main_udmap 0x4003>; 125 dma-names = "tx", "rx1", "rx2"; 126 127 rng: rng@4e10000 { 128 compatible = "inside-secure,safexcel-eip76"; 129 reg = <0x0 0x4e10000 0x0 0x7d>; 130 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 131 status = "disabled"; /* Used by OP-TEE */ 132 }; 133 }; 134 135 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 136 main_timerio_input: pinctrl@104200 { 137 compatible = "pinctrl-single"; 138 reg = <0x0 0x104200 0x0 0x30>; 139 #pinctrl-cells = <1>; 140 pinctrl-single,register-width = <32>; 141 pinctrl-single,function-mask = <0x0000001ff>; 142 }; 143 144 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 145 main_timerio_output: pinctrl@104280 { 146 compatible = "pinctrl-single"; 147 reg = <0x0 0x104280 0x0 0x20>; 148 #pinctrl-cells = <1>; 149 pinctrl-single,register-width = <32>; 150 pinctrl-single,function-mask = <0x0000000f>; 151 }; 152 153 main_pmx0: pinctrl@11c000 { 154 compatible = "pinctrl-single"; 155 reg = <0x0 0x11c000 0x0 0x2e4>; 156 #pinctrl-cells = <1>; 157 pinctrl-single,register-width = <32>; 158 pinctrl-single,function-mask = <0xffffffff>; 159 }; 160 161 main_pmx1: pinctrl@11c2e8 { 162 compatible = "pinctrl-single"; 163 reg = <0x0 0x11c2e8 0x0 0x24>; 164 #pinctrl-cells = <1>; 165 pinctrl-single,register-width = <32>; 166 pinctrl-single,function-mask = <0xffffffff>; 167 }; 168 169 main_i2c0: i2c@2000000 { 170 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 171 reg = <0x0 0x2000000 0x0 0x100>; 172 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 173 #address-cells = <1>; 174 #size-cells = <0>; 175 clock-names = "fck"; 176 clocks = <&k3_clks 110 1>; 177 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 178 status = "disabled"; 179 }; 180 181 main_i2c1: i2c@2010000 { 182 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 183 reg = <0x0 0x2010000 0x0 0x100>; 184 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 185 #address-cells = <1>; 186 #size-cells = <0>; 187 clock-names = "fck"; 188 clocks = <&k3_clks 111 1>; 189 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 190 status = "disabled"; 191 }; 192 193 main_i2c2: i2c@2020000 { 194 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 195 reg = <0x0 0x2020000 0x0 0x100>; 196 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 clock-names = "fck"; 200 clocks = <&k3_clks 112 1>; 201 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 202 status = "disabled"; 203 }; 204 205 main_i2c3: i2c@2030000 { 206 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 207 reg = <0x0 0x2030000 0x0 0x100>; 208 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 clock-names = "fck"; 212 clocks = <&k3_clks 113 1>; 213 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 214 status = "disabled"; 215 }; 216 217 ecap0: pwm@3100000 { 218 compatible = "ti,am654-ecap", "ti,am3352-ecap"; 219 #pwm-cells = <3>; 220 reg = <0x0 0x03100000 0x0 0x60>; 221 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 222 clocks = <&k3_clks 39 0>; 223 clock-names = "fck"; 224 status = "disabled"; 225 }; 226 227 main_spi0: spi@2100000 { 228 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 229 reg = <0x0 0x2100000 0x0 0x400>; 230 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&k3_clks 137 1>; 232 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>; 233 #address-cells = <1>; 234 #size-cells = <0>; 235 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 236 dma-names = "tx0", "rx0"; 237 status = "disabled"; 238 }; 239 240 main_spi1: spi@2110000 { 241 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 242 reg = <0x0 0x2110000 0x0 0x400>; 243 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&k3_clks 138 1>; 245 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 assigned-clocks = <&k3_clks 137 1>; 249 assigned-clock-rates = <48000000>; 250 status = "disabled"; 251 }; 252 253 main_spi2: spi@2120000 { 254 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 255 reg = <0x0 0x2120000 0x0 0x400>; 256 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&k3_clks 139 1>; 258 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>; 259 #address-cells = <1>; 260 #size-cells = <0>; 261 status = "disabled"; 262 }; 263 264 main_spi3: spi@2130000 { 265 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 266 reg = <0x0 0x2130000 0x0 0x400>; 267 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&k3_clks 140 1>; 269 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 status = "disabled"; 273 }; 274 275 main_spi4: spi@2140000 { 276 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 277 reg = <0x0 0x2140000 0x0 0x400>; 278 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&k3_clks 141 1>; 280 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 281 #address-cells = <1>; 282 #size-cells = <0>; 283 status = "disabled"; 284 }; 285 286 main_timer0: timer@2400000 { 287 compatible = "ti,am654-timer"; 288 reg = <0x00 0x2400000 0x00 0x400>; 289 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&k3_clks 23 0>; 291 clock-names = "fck"; 292 assigned-clocks = <&k3_clks 23 0>; 293 assigned-clock-parents = <&k3_clks 23 1>; 294 power-domains = <&k3_pds 23 TI_SCI_PD_EXCLUSIVE>; 295 ti,timer-pwm; 296 }; 297 298 main_timer1: timer@2410000 { 299 compatible = "ti,am654-timer"; 300 reg = <0x00 0x2410000 0x00 0x400>; 301 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&k3_clks 24 0>; 303 clock-names = "fck"; 304 assigned-clocks = <&k3_clks 24 0>; 305 assigned-clock-parents = <&k3_clks 24 1>; 306 power-domains = <&k3_pds 24 TI_SCI_PD_EXCLUSIVE>; 307 ti,timer-pwm; 308 }; 309 310 main_timer2: timer@2420000 { 311 compatible = "ti,am654-timer"; 312 reg = <0x00 0x2420000 0x00 0x400>; 313 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&k3_clks 27 0>; 315 clock-names = "fck"; 316 assigned-clocks = <&k3_clks 27 0>; 317 assigned-clock-parents = <&k3_clks 27 1>; 318 power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>; 319 ti,timer-pwm; 320 }; 321 322 main_timer3: timer@2430000 { 323 compatible = "ti,am654-timer"; 324 reg = <0x00 0x2430000 0x00 0x400>; 325 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&k3_clks 28 0>; 327 clock-names = "fck"; 328 assigned-clocks = <&k3_clks 28 0>; 329 assigned-clock-parents = <&k3_clks 28 1>; 330 power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>; 331 ti,timer-pwm; 332 }; 333 334 main_timer4: timer@2440000 { 335 compatible = "ti,am654-timer"; 336 reg = <0x00 0x2440000 0x00 0x400>; 337 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&k3_clks 29 0>; 339 clock-names = "fck"; 340 assigned-clocks = <&k3_clks 29 0>; 341 assigned-clock-parents = <&k3_clks 29 1>; 342 power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>; 343 ti,timer-pwm; 344 }; 345 346 main_timer5: timer@2450000 { 347 compatible = "ti,am654-timer"; 348 reg = <0x00 0x2450000 0x00 0x400>; 349 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 350 clocks = <&k3_clks 30 0>; 351 clock-names = "fck"; 352 assigned-clocks = <&k3_clks 30 0>; 353 assigned-clock-parents = <&k3_clks 30 1>; 354 power-domains = <&k3_pds 30 TI_SCI_PD_EXCLUSIVE>; 355 ti,timer-pwm; 356 }; 357 358 main_timer6: timer@2460000 { 359 compatible = "ti,am654-timer"; 360 reg = <0x00 0x2460000 0x00 0x400>; 361 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&k3_clks 31 0>; 363 assigned-clocks = <&k3_clks 31 0>; 364 assigned-clock-parents = <&k3_clks 31 1>; 365 clock-names = "fck"; 366 power-domains = <&k3_pds 31 TI_SCI_PD_EXCLUSIVE>; 367 ti,timer-pwm; 368 }; 369 370 main_timer7: timer@2470000 { 371 compatible = "ti,am654-timer"; 372 reg = <0x00 0x2470000 0x00 0x400>; 373 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&k3_clks 32 0>; 375 clock-names = "fck"; 376 assigned-clocks = <&k3_clks 32 0>; 377 assigned-clock-parents = <&k3_clks 32 1>; 378 power-domains = <&k3_pds 32 TI_SCI_PD_EXCLUSIVE>; 379 ti,timer-pwm; 380 }; 381 382 main_timer8: timer@2480000 { 383 compatible = "ti,am654-timer"; 384 reg = <0x00 0x2480000 0x00 0x400>; 385 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&k3_clks 33 0>; 387 clock-names = "fck"; 388 assigned-clocks = <&k3_clks 33 0>; 389 assigned-clock-parents = <&k3_clks 33 1>; 390 power-domains = <&k3_pds 33 TI_SCI_PD_EXCLUSIVE>; 391 ti,timer-pwm; 392 }; 393 394 main_timer9: timer@2490000 { 395 compatible = "ti,am654-timer"; 396 reg = <0x00 0x2490000 0x00 0x400>; 397 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&k3_clks 34 0>; 399 clock-names = "fck"; 400 assigned-clocks = <&k3_clks 34 0>; 401 assigned-clock-parents = <&k3_clks 34 1>; 402 power-domains = <&k3_pds 34 TI_SCI_PD_EXCLUSIVE>; 403 ti,timer-pwm; 404 }; 405 406 main_timer10: timer@24a0000 { 407 compatible = "ti,am654-timer"; 408 reg = <0x00 0x24a0000 0x00 0x400>; 409 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&k3_clks 25 0>; 411 clock-names = "fck"; 412 assigned-clocks = <&k3_clks 25 0>; 413 assigned-clock-parents = <&k3_clks 25 1>; 414 power-domains = <&k3_pds 25 TI_SCI_PD_EXCLUSIVE>; 415 ti,timer-pwm; 416 }; 417 418 main_timer11: timer@24b0000 { 419 compatible = "ti,am654-timer"; 420 reg = <0x00 0x24b0000 0x00 0x400>; 421 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&k3_clks 26 0>; 423 clock-names = "fck"; 424 assigned-clocks = <&k3_clks 26 0>; 425 assigned-clock-parents = <&k3_clks 26 1>; 426 power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; 427 ti,timer-pwm; 428 }; 429 430 sdhci0: mmc@4f80000 { 431 compatible = "ti,am654-sdhci-5.1"; 432 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; 433 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; 434 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>; 435 clock-names = "clk_ahb", "clk_xin"; 436 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 437 mmc-ddr-1_8v; 438 mmc-hs200-1_8v; 439 ti,clkbuf-sel = <0x7>; 440 ti,trm-icp = <0x8>; 441 ti,otap-del-sel-legacy = <0x0>; 442 ti,otap-del-sel-mmc-hs = <0x0>; 443 ti,otap-del-sel-sd-hs = <0x0>; 444 ti,otap-del-sel-sdr12 = <0x0>; 445 ti,otap-del-sel-sdr25 = <0x0>; 446 ti,otap-del-sel-sdr50 = <0x8>; 447 ti,otap-del-sel-sdr104 = <0x7>; 448 ti,otap-del-sel-ddr50 = <0x5>; 449 ti,otap-del-sel-ddr52 = <0x5>; 450 ti,otap-del-sel-hs200 = <0x5>; 451 ti,itap-del-sel-legacy = <0xa>; 452 ti,itap-del-sel-mmc-hs = <0x1>; 453 ti,itap-del-sel-ddr52 = <0x0>; 454 dma-coherent; 455 }; 456 457 sdhci1: mmc@4fa0000 { 458 compatible = "ti,am654-sdhci-5.1"; 459 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>; 460 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; 461 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>; 462 clock-names = "clk_ahb", "clk_xin"; 463 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 464 ti,clkbuf-sel = <0x7>; 465 ti,trm-icp = <0x8>; 466 ti,otap-del-sel-legacy = <0x0>; 467 ti,otap-del-sel-mmc-hs = <0x0>; 468 ti,otap-del-sel-sd-hs = <0x0>; 469 ti,otap-del-sel-sdr12 = <0xf>; 470 ti,otap-del-sel-sdr25 = <0xf>; 471 ti,otap-del-sel-sdr50 = <0x8>; 472 ti,otap-del-sel-sdr104 = <0x7>; 473 ti,otap-del-sel-ddr50 = <0x4>; 474 ti,otap-del-sel-ddr52 = <0x4>; 475 ti,otap-del-sel-hs200 = <0x7>; 476 ti,itap-del-sel-legacy = <0xa>; 477 ti,itap-del-sel-sd-hs = <0x1>; 478 ti,itap-del-sel-sdr12 = <0xa>; 479 ti,itap-del-sel-sdr25 = <0x1>; 480 dma-coherent; 481 }; 482 483 scm_conf: scm-conf@100000 { 484 compatible = "syscon", "simple-mfd"; 485 reg = <0 0x00100000 0 0x1c000>; 486 #address-cells = <1>; 487 #size-cells = <1>; 488 ranges = <0x0 0x0 0x00100000 0x1c000>; 489 490 serdes0_clk: clock@4080 { 491 compatible = "syscon"; 492 reg = <0x00004080 0x4>; 493 }; 494 495 serdes1_clk: clock@4090 { 496 compatible = "syscon"; 497 reg = <0x00004090 0x4>; 498 }; 499 500 serdes_mux: mux-controller { 501 compatible = "mmio-mux"; 502 #mux-control-cells = <1>; 503 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */ 504 <0x4090 0x3>; /* SERDES1 lane select */ 505 }; 506 507 dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 { 508 compatible = "syscon"; 509 reg = <0x000041e0 0x14>; 510 }; 511 512 ehrpwm_tbclk: clock-controller@4140 { 513 compatible = "ti,am654-ehrpwm-tbclk"; 514 reg = <0x4140 0x18>; 515 #clock-cells = <1>; 516 }; 517 }; 518 519 dwc3_0: dwc3@4000000 { 520 compatible = "ti,am654-dwc3"; 521 reg = <0x0 0x4000000 0x0 0x4000>; 522 #address-cells = <1>; 523 #size-cells = <1>; 524 ranges = <0x0 0x0 0x4000000 0x20000>; 525 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 526 dma-coherent; 527 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; 528 clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 529 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 530 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 531 <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ 532 533 usb0: usb@10000 { 534 compatible = "snps,dwc3"; 535 reg = <0x10000 0x10000>; 536 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 539 interrupt-names = "peripheral", 540 "host", 541 "otg"; 542 maximum-speed = "high-speed"; 543 dr_mode = "otg"; 544 phys = <&usb0_phy>; 545 phy-names = "usb2-phy"; 546 snps,dis_u3_susphy_quirk; 547 }; 548 }; 549 550 usb0_phy: phy@4100000 { 551 compatible = "ti,am654-usb2", "ti,omap-usb2"; 552 reg = <0x0 0x4100000 0x0 0x54>; 553 syscon-phy-power = <&scm_conf 0x4000>; 554 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>; 555 clock-names = "wkupclk", "refclk"; 556 #phy-cells = <0>; 557 }; 558 559 dwc3_1: dwc3@4020000 { 560 compatible = "ti,am654-dwc3"; 561 reg = <0x0 0x4020000 0x0 0x4000>; 562 #address-cells = <1>; 563 #size-cells = <1>; 564 ranges = <0x0 0x0 0x4020000 0x20000>; 565 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 566 dma-coherent; 567 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 568 clocks = <&k3_clks 152 2>; 569 assigned-clocks = <&k3_clks 152 2>; 570 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 571 572 usb1: usb@10000 { 573 compatible = "snps,dwc3"; 574 reg = <0x10000 0x10000>; 575 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 578 interrupt-names = "peripheral", 579 "host", 580 "otg"; 581 maximum-speed = "high-speed"; 582 dr_mode = "otg"; 583 phys = <&usb1_phy>; 584 phy-names = "usb2-phy"; 585 }; 586 }; 587 588 usb1_phy: phy@4110000 { 589 compatible = "ti,am654-usb2", "ti,omap-usb2"; 590 reg = <0x0 0x4110000 0x0 0x54>; 591 syscon-phy-power = <&scm_conf 0x4020>; 592 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>; 593 clock-names = "wkupclk", "refclk"; 594 #phy-cells = <0>; 595 }; 596 597 intr_main_gpio: interrupt-controller@a00000 { 598 compatible = "ti,sci-intr"; 599 reg = <0x0 0x00a00000 0x0 0x400>; 600 ti,intr-trigger-type = <1>; 601 interrupt-controller; 602 interrupt-parent = <&gic500>; 603 #interrupt-cells = <1>; 604 ti,sci = <&dmsc>; 605 ti,sci-dev-id = <100>; 606 ti,interrupt-ranges = <0 392 32>; 607 }; 608 609 main_navss: bus@30800000 { 610 compatible = "simple-mfd"; 611 #address-cells = <2>; 612 #size-cells = <2>; 613 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>; 614 dma-coherent; 615 dma-ranges; 616 617 ti,sci-dev-id = <118>; 618 619 intr_main_navss: interrupt-controller@310e0000 { 620 compatible = "ti,sci-intr"; 621 reg = <0x0 0x310e0000 0x0 0x2000>; 622 ti,intr-trigger-type = <4>; 623 interrupt-controller; 624 interrupt-parent = <&gic500>; 625 #interrupt-cells = <1>; 626 ti,sci = <&dmsc>; 627 ti,sci-dev-id = <182>; 628 ti,interrupt-ranges = <0 64 64>, 629 <64 448 64>; 630 }; 631 632 inta_main_udmass: interrupt-controller@33d00000 { 633 compatible = "ti,sci-inta"; 634 reg = <0x0 0x33d00000 0x0 0x100000>; 635 interrupt-controller; 636 interrupt-parent = <&intr_main_navss>; 637 msi-controller; 638 #interrupt-cells = <0>; 639 ti,sci = <&dmsc>; 640 ti,sci-dev-id = <179>; 641 ti,interrupt-ranges = <0 0 256>; 642 }; 643 644 secure_proxy_main: mailbox@32c00000 { 645 compatible = "ti,am654-secure-proxy"; 646 #mbox-cells = <1>; 647 reg-names = "target_data", "rt", "scfg"; 648 reg = <0x00 0x32c00000 0x00 0x100000>, 649 <0x00 0x32400000 0x00 0x100000>, 650 <0x00 0x32800000 0x00 0x100000>; 651 interrupt-names = "rx_011"; 652 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 653 }; 654 655 hwspinlock: spinlock@30e00000 { 656 compatible = "ti,am654-hwspinlock"; 657 reg = <0x00 0x30e00000 0x00 0x1000>; 658 #hwlock-cells = <1>; 659 }; 660 661 mailbox0_cluster0: mailbox@31f80000 { 662 compatible = "ti,am654-mailbox"; 663 reg = <0x00 0x31f80000 0x00 0x200>; 664 #mbox-cells = <1>; 665 ti,mbox-num-users = <4>; 666 ti,mbox-num-fifos = <16>; 667 interrupt-parent = <&intr_main_navss>; 668 status = "disabled"; 669 }; 670 671 mailbox0_cluster1: mailbox@31f81000 { 672 compatible = "ti,am654-mailbox"; 673 reg = <0x00 0x31f81000 0x00 0x200>; 674 #mbox-cells = <1>; 675 ti,mbox-num-users = <4>; 676 ti,mbox-num-fifos = <16>; 677 interrupt-parent = <&intr_main_navss>; 678 status = "disabled"; 679 }; 680 681 mailbox0_cluster2: mailbox@31f82000 { 682 compatible = "ti,am654-mailbox"; 683 reg = <0x00 0x31f82000 0x00 0x200>; 684 #mbox-cells = <1>; 685 ti,mbox-num-users = <4>; 686 ti,mbox-num-fifos = <16>; 687 interrupt-parent = <&intr_main_navss>; 688 status = "disabled"; 689 }; 690 691 mailbox0_cluster3: mailbox@31f83000 { 692 compatible = "ti,am654-mailbox"; 693 reg = <0x00 0x31f83000 0x00 0x200>; 694 #mbox-cells = <1>; 695 ti,mbox-num-users = <4>; 696 ti,mbox-num-fifos = <16>; 697 interrupt-parent = <&intr_main_navss>; 698 status = "disabled"; 699 }; 700 701 mailbox0_cluster4: mailbox@31f84000 { 702 compatible = "ti,am654-mailbox"; 703 reg = <0x00 0x31f84000 0x00 0x200>; 704 #mbox-cells = <1>; 705 ti,mbox-num-users = <4>; 706 ti,mbox-num-fifos = <16>; 707 interrupt-parent = <&intr_main_navss>; 708 status = "disabled"; 709 }; 710 711 mailbox0_cluster5: mailbox@31f85000 { 712 compatible = "ti,am654-mailbox"; 713 reg = <0x00 0x31f85000 0x00 0x200>; 714 #mbox-cells = <1>; 715 ti,mbox-num-users = <4>; 716 ti,mbox-num-fifos = <16>; 717 interrupt-parent = <&intr_main_navss>; 718 status = "disabled"; 719 }; 720 721 mailbox0_cluster6: mailbox@31f86000 { 722 compatible = "ti,am654-mailbox"; 723 reg = <0x00 0x31f86000 0x00 0x200>; 724 #mbox-cells = <1>; 725 ti,mbox-num-users = <4>; 726 ti,mbox-num-fifos = <16>; 727 interrupt-parent = <&intr_main_navss>; 728 status = "disabled"; 729 }; 730 731 mailbox0_cluster7: mailbox@31f87000 { 732 compatible = "ti,am654-mailbox"; 733 reg = <0x00 0x31f87000 0x00 0x200>; 734 #mbox-cells = <1>; 735 ti,mbox-num-users = <4>; 736 ti,mbox-num-fifos = <16>; 737 interrupt-parent = <&intr_main_navss>; 738 status = "disabled"; 739 }; 740 741 mailbox0_cluster8: mailbox@31f88000 { 742 compatible = "ti,am654-mailbox"; 743 reg = <0x00 0x31f88000 0x00 0x200>; 744 #mbox-cells = <1>; 745 ti,mbox-num-users = <4>; 746 ti,mbox-num-fifos = <16>; 747 interrupt-parent = <&intr_main_navss>; 748 status = "disabled"; 749 }; 750 751 mailbox0_cluster9: mailbox@31f89000 { 752 compatible = "ti,am654-mailbox"; 753 reg = <0x00 0x31f89000 0x00 0x200>; 754 #mbox-cells = <1>; 755 ti,mbox-num-users = <4>; 756 ti,mbox-num-fifos = <16>; 757 interrupt-parent = <&intr_main_navss>; 758 status = "disabled"; 759 }; 760 761 mailbox0_cluster10: mailbox@31f8a000 { 762 compatible = "ti,am654-mailbox"; 763 reg = <0x00 0x31f8a000 0x00 0x200>; 764 #mbox-cells = <1>; 765 ti,mbox-num-users = <4>; 766 ti,mbox-num-fifos = <16>; 767 interrupt-parent = <&intr_main_navss>; 768 status = "disabled"; 769 }; 770 771 mailbox0_cluster11: mailbox@31f8b000 { 772 compatible = "ti,am654-mailbox"; 773 reg = <0x00 0x31f8b000 0x00 0x200>; 774 #mbox-cells = <1>; 775 ti,mbox-num-users = <4>; 776 ti,mbox-num-fifos = <16>; 777 interrupt-parent = <&intr_main_navss>; 778 status = "disabled"; 779 }; 780 781 ringacc: ringacc@3c000000 { 782 compatible = "ti,am654-navss-ringacc"; 783 reg = <0x0 0x3c000000 0x0 0x400000>, 784 <0x0 0x38000000 0x0 0x400000>, 785 <0x0 0x31120000 0x0 0x100>, 786 <0x0 0x33000000 0x0 0x40000>, 787 <0x0 0x31080000 0x0 0x40000>; 788 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 789 ti,num-rings = <818>; 790 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 791 ti,sci = <&dmsc>; 792 ti,sci-dev-id = <187>; 793 msi-parent = <&inta_main_udmass>; 794 }; 795 796 main_udmap: dma-controller@31150000 { 797 compatible = "ti,am654-navss-main-udmap"; 798 reg = <0x0 0x31150000 0x0 0x100>, 799 <0x0 0x34000000 0x0 0x100000>, 800 <0x0 0x35000000 0x0 0x100000>; 801 reg-names = "gcfg", "rchanrt", "tchanrt"; 802 msi-parent = <&inta_main_udmass>; 803 #dma-cells = <1>; 804 805 ti,sci = <&dmsc>; 806 ti,sci-dev-id = <188>; 807 ti,ringacc = <&ringacc>; 808 809 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */ 810 <0xd>; /* TX_CHAN */ 811 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */ 812 <0xa>; /* RX_CHAN */ 813 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */ 814 }; 815 816 cpts@310d0000 { 817 compatible = "ti,am65-cpts"; 818 reg = <0x0 0x310d0000 0x0 0x400>; 819 reg-names = "cpts"; 820 clocks = <&main_cpts_mux>; 821 clock-names = "cpts"; 822 interrupts-extended = <&intr_main_navss 391>; 823 interrupt-names = "cpts"; 824 ti,cpts-periodic-outputs = <6>; 825 ti,cpts-ext-ts-inputs = <8>; 826 827 main_cpts_mux: refclk-mux { 828 #clock-cells = <0>; 829 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, 830 <&k3_clks 118 6>, <&k3_clks 118 3>, 831 <&k3_clks 118 8>, <&k3_clks 118 14>, 832 <&k3_clks 120 3>, <&k3_clks 121 3>; 833 assigned-clocks = <&main_cpts_mux>; 834 assigned-clock-parents = <&k3_clks 118 5>; 835 }; 836 }; 837 }; 838 839 main_gpio0: gpio@600000 { 840 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 841 reg = <0x0 0x600000 0x0 0x100>; 842 gpio-controller; 843 #gpio-cells = <2>; 844 interrupt-parent = <&intr_main_gpio>; 845 interrupts = <192>, <193>, <194>, <195>, <196>, <197>; 846 interrupt-controller; 847 #interrupt-cells = <2>; 848 ti,ngpio = <96>; 849 ti,davinci-gpio-unbanked = <0>; 850 clocks = <&k3_clks 57 0>; 851 clock-names = "gpio"; 852 }; 853 854 main_gpio1: gpio@601000 { 855 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 856 reg = <0x0 0x601000 0x0 0x100>; 857 gpio-controller; 858 #gpio-cells = <2>; 859 interrupt-parent = <&intr_main_gpio>; 860 interrupts = <200>, <201>, <202>, <203>, <204>, <205>; 861 interrupt-controller; 862 #interrupt-cells = <2>; 863 ti,ngpio = <90>; 864 ti,davinci-gpio-unbanked = <0>; 865 clocks = <&k3_clks 58 0>; 866 clock-names = "gpio"; 867 }; 868 869 pcie0_rc: pcie@5500000 { 870 compatible = "ti,am654-pcie-rc"; 871 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; 872 reg-names = "app", "dbics", "config", "atu"; 873 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 874 #address-cells = <3>; 875 #size-cells = <2>; 876 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>, 877 <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; 878 ti,syscon-pcie-id = <&scm_conf 0x210>; 879 ti,syscon-pcie-mode = <&scm_conf 0x4060>; 880 bus-range = <0x0 0xff>; 881 num-viewport = <16>; 882 max-link-speed = <2>; 883 dma-coherent; 884 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 885 msi-map = <0x0 &gic_its 0x0 0x10000>; 886 device_type = "pci"; 887 status = "disabled"; 888 }; 889 890 pcie0_ep: pcie-ep@5500000 { 891 compatible = "ti,am654-pcie-ep"; 892 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; 893 reg-names = "app", "dbics", "addr_space", "atu"; 894 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 895 ti,syscon-pcie-mode = <&scm_conf 0x4060>; 896 num-ib-windows = <16>; 897 num-ob-windows = <16>; 898 max-link-speed = <2>; 899 dma-coherent; 900 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 901 status = "disabled"; 902 }; 903 904 pcie1_rc: pcie@5600000 { 905 compatible = "ti,am654-pcie-rc"; 906 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; 907 reg-names = "app", "dbics", "config", "atu"; 908 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 909 #address-cells = <3>; 910 #size-cells = <2>; 911 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>, 912 <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>; 913 ti,syscon-pcie-id = <&scm_conf 0x210>; 914 ti,syscon-pcie-mode = <&scm_conf 0x4070>; 915 bus-range = <0x0 0xff>; 916 num-viewport = <16>; 917 max-link-speed = <2>; 918 dma-coherent; 919 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 920 msi-map = <0x0 &gic_its 0x10000 0x10000>; 921 device_type = "pci"; 922 status = "disabled"; 923 }; 924 925 pcie1_ep: pcie-ep@5600000 { 926 compatible = "ti,am654-pcie-ep"; 927 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; 928 reg-names = "app", "dbics", "addr_space", "atu"; 929 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 930 ti,syscon-pcie-mode = <&scm_conf 0x4070>; 931 num-ib-windows = <16>; 932 num-ob-windows = <16>; 933 max-link-speed = <2>; 934 dma-coherent; 935 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 936 status = "disabled"; 937 }; 938 939 mcasp0: mcasp@2b00000 { 940 compatible = "ti,am33xx-mcasp-audio"; 941 reg = <0x0 0x02b00000 0x0 0x2000>, 942 <0x0 0x02b08000 0x0 0x1000>; 943 reg-names = "mpu","dat"; 944 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 946 interrupt-names = "tx", "rx"; 947 948 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 949 dma-names = "tx", "rx"; 950 951 clocks = <&k3_clks 104 0>; 952 clock-names = "fck"; 953 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 954 status = "disabled"; 955 }; 956 957 mcasp1: mcasp@2b10000 { 958 compatible = "ti,am33xx-mcasp-audio"; 959 reg = <0x0 0x02b10000 0x0 0x2000>, 960 <0x0 0x02b18000 0x0 0x1000>; 961 reg-names = "mpu","dat"; 962 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 964 interrupt-names = "tx", "rx"; 965 966 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 967 dma-names = "tx", "rx"; 968 969 clocks = <&k3_clks 105 0>; 970 clock-names = "fck"; 971 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 972 status = "disabled"; 973 }; 974 975 mcasp2: mcasp@2b20000 { 976 compatible = "ti,am33xx-mcasp-audio"; 977 reg = <0x0 0x02b20000 0x0 0x2000>, 978 <0x0 0x02b28000 0x0 0x1000>; 979 reg-names = "mpu","dat"; 980 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 982 interrupt-names = "tx", "rx"; 983 984 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 985 dma-names = "tx", "rx"; 986 987 clocks = <&k3_clks 106 0>; 988 clock-names = "fck"; 989 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 990 status = "disabled"; 991 }; 992 993 cal: cal@6f03000 { 994 compatible = "ti,am654-cal"; 995 reg = <0x0 0x06f03000 0x0 0x400>, 996 <0x0 0x06f03800 0x0 0x40>; 997 reg-names = "cal_top", 998 "cal_rx_core0"; 999 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1000 ti,camerrx-control = <&scm_conf 0x40c0>; 1001 clock-names = "fck"; 1002 clocks = <&k3_clks 2 0>; 1003 power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>; 1004 1005 ports { 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 1009 csi2_0: port@0 { 1010 reg = <0>; 1011 }; 1012 }; 1013 }; 1014 1015 dss: dss@4a00000 { 1016 compatible = "ti,am65x-dss"; 1017 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ 1018 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ 1019 <0x0 0x04a06000 0x0 0x1000>, /* vid */ 1020 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ 1021 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ 1022 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ 1023 <0x0 0x04a0b000 0x0 0x1000>, /* vp2 */ 1024 <0x0 0x04a01000 0x0 0x1000>; /* common1 */ 1025 reg-names = "common", "vidl1", "vid", 1026 "ovr1", "ovr2", "vp1", "vp2", "common1"; 1027 1028 ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; 1029 1030 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 1031 1032 clocks = <&k3_clks 67 1>, 1033 <&k3_clks 216 1>, 1034 <&k3_clks 67 2>; 1035 clock-names = "fck", "vp1", "vp2"; 1036 1037 /* 1038 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via 1039 * DIV1. See "Figure 12-3365. DSS Integration" 1040 * in AM65x TRM for details. 1041 */ 1042 assigned-clocks = <&k3_clks 67 2>; 1043 assigned-clock-parents = <&k3_clks 67 5>; 1044 1045 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1046 1047 dma-coherent; 1048 1049 dss_ports: ports { 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 }; 1053 }; 1054 1055 ehrpwm0: pwm@3000000 { 1056 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 1057 #pwm-cells = <3>; 1058 reg = <0x0 0x3000000 0x0 0x100>; 1059 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 1060 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>; 1061 clock-names = "tbclk", "fck"; 1062 status = "disabled"; 1063 }; 1064 1065 ehrpwm1: pwm@3010000 { 1066 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 1067 #pwm-cells = <3>; 1068 reg = <0x0 0x3010000 0x0 0x100>; 1069 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 1070 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>; 1071 clock-names = "tbclk", "fck"; 1072 status = "disabled"; 1073 }; 1074 1075 ehrpwm2: pwm@3020000 { 1076 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 1077 #pwm-cells = <3>; 1078 reg = <0x0 0x3020000 0x0 0x100>; 1079 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 1080 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>; 1081 clock-names = "tbclk", "fck"; 1082 status = "disabled"; 1083 }; 1084 1085 ehrpwm3: pwm@3030000 { 1086 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 1087 #pwm-cells = <3>; 1088 reg = <0x0 0x3030000 0x0 0x100>; 1089 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 1090 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>; 1091 clock-names = "tbclk", "fck"; 1092 status = "disabled"; 1093 }; 1094 1095 ehrpwm4: pwm@3040000 { 1096 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 1097 #pwm-cells = <3>; 1098 reg = <0x0 0x3040000 0x0 0x100>; 1099 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; 1100 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>; 1101 clock-names = "tbclk", "fck"; 1102 status = "disabled"; 1103 }; 1104 1105 ehrpwm5: pwm@3050000 { 1106 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 1107 #pwm-cells = <3>; 1108 reg = <0x0 0x3050000 0x0 0x100>; 1109 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; 1110 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>; 1111 clock-names = "tbclk", "fck"; 1112 status = "disabled"; 1113 }; 1114 1115 icssg0: icssg@b000000 { 1116 compatible = "ti,am654-icssg"; 1117 reg = <0x00 0xb000000 0x00 0x80000>; 1118 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 1119 #address-cells = <1>; 1120 #size-cells = <1>; 1121 ranges = <0x0 0x00 0xb000000 0x80000>; 1122 1123 icssg0_mem: memories@0 { 1124 reg = <0x0 0x2000>, 1125 <0x2000 0x2000>, 1126 <0x10000 0x10000>; 1127 reg-names = "dram0", "dram1", 1128 "shrdram2"; 1129 }; 1130 1131 icssg0_cfg: cfg@26000 { 1132 compatible = "ti,pruss-cfg", "syscon"; 1133 reg = <0x26000 0x200>; 1134 #address-cells = <1>; 1135 #size-cells = <1>; 1136 ranges = <0x0 0x26000 0x2000>; 1137 1138 clocks { 1139 #address-cells = <1>; 1140 #size-cells = <0>; 1141 1142 icssg0_coreclk_mux: coreclk-mux@3c { 1143 reg = <0x3c>; 1144 #clock-cells = <0>; 1145 clocks = <&k3_clks 62 19>, /* icssg0_core_clk */ 1146 <&k3_clks 62 3>; /* icssg0_iclk */ 1147 assigned-clocks = <&icssg0_coreclk_mux>; 1148 assigned-clock-parents = <&k3_clks 62 3>; 1149 }; 1150 1151 icssg0_iepclk_mux: iepclk-mux@30 { 1152 reg = <0x30>; 1153 #clock-cells = <0>; 1154 clocks = <&k3_clks 62 10>, /* icssg0_iep_clk */ 1155 <&icssg0_coreclk_mux>; /* core_clk */ 1156 assigned-clocks = <&icssg0_iepclk_mux>; 1157 assigned-clock-parents = <&icssg0_coreclk_mux>; 1158 }; 1159 }; 1160 }; 1161 1162 icssg0_mii_rt: mii-rt@32000 { 1163 compatible = "ti,pruss-mii", "syscon"; 1164 reg = <0x32000 0x100>; 1165 }; 1166 1167 icssg0_mii_g_rt: mii-g-rt@33000 { 1168 compatible = "ti,pruss-mii-g", "syscon"; 1169 reg = <0x33000 0x1000>; 1170 }; 1171 1172 icssg0_intc: interrupt-controller@20000 { 1173 compatible = "ti,icssg-intc"; 1174 reg = <0x20000 0x2000>; 1175 interrupt-controller; 1176 #interrupt-cells = <3>; 1177 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 1185 interrupt-names = "host_intr0", "host_intr1", 1186 "host_intr2", "host_intr3", 1187 "host_intr4", "host_intr5", 1188 "host_intr6", "host_intr7"; 1189 }; 1190 1191 pru0_0: pru@34000 { 1192 compatible = "ti,am654-pru"; 1193 reg = <0x34000 0x4000>, 1194 <0x22000 0x100>, 1195 <0x22400 0x100>; 1196 reg-names = "iram", "control", "debug"; 1197 firmware-name = "am65x-pru0_0-fw"; 1198 }; 1199 1200 rtu0_0: rtu@4000 { 1201 compatible = "ti,am654-rtu"; 1202 reg = <0x4000 0x2000>, 1203 <0x23000 0x100>, 1204 <0x23400 0x100>; 1205 reg-names = "iram", "control", "debug"; 1206 firmware-name = "am65x-rtu0_0-fw"; 1207 }; 1208 1209 tx_pru0_0: txpru@a000 { 1210 compatible = "ti,am654-tx-pru"; 1211 reg = <0xa000 0x1800>, 1212 <0x25000 0x100>, 1213 <0x25400 0x100>; 1214 reg-names = "iram", "control", "debug"; 1215 firmware-name = "am65x-txpru0_0-fw"; 1216 }; 1217 1218 pru0_1: pru@38000 { 1219 compatible = "ti,am654-pru"; 1220 reg = <0x38000 0x4000>, 1221 <0x24000 0x100>, 1222 <0x24400 0x100>; 1223 reg-names = "iram", "control", "debug"; 1224 firmware-name = "am65x-pru0_1-fw"; 1225 }; 1226 1227 rtu0_1: rtu@6000 { 1228 compatible = "ti,am654-rtu"; 1229 reg = <0x6000 0x2000>, 1230 <0x23800 0x100>, 1231 <0x23c00 0x100>; 1232 reg-names = "iram", "control", "debug"; 1233 firmware-name = "am65x-rtu0_1-fw"; 1234 }; 1235 1236 tx_pru0_1: txpru@c000 { 1237 compatible = "ti,am654-tx-pru"; 1238 reg = <0xc000 0x1800>, 1239 <0x25800 0x100>, 1240 <0x25c00 0x100>; 1241 reg-names = "iram", "control", "debug"; 1242 firmware-name = "am65x-txpru0_1-fw"; 1243 }; 1244 1245 icssg0_mdio: mdio@32400 { 1246 compatible = "ti,davinci_mdio"; 1247 reg = <0x32400 0x100>; 1248 clocks = <&k3_clks 62 3>; 1249 clock-names = "fck"; 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 bus_freq = <1000000>; 1253 status = "disabled"; 1254 }; 1255 }; 1256 1257 icssg1: icssg@b100000 { 1258 compatible = "ti,am654-icssg"; 1259 reg = <0x00 0xb100000 0x00 0x80000>; 1260 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 1261 #address-cells = <1>; 1262 #size-cells = <1>; 1263 ranges = <0x0 0x00 0xb100000 0x80000>; 1264 1265 icssg1_mem: memories@0 { 1266 reg = <0x0 0x2000>, 1267 <0x2000 0x2000>, 1268 <0x10000 0x10000>; 1269 reg-names = "dram0", "dram1", 1270 "shrdram2"; 1271 }; 1272 1273 icssg1_cfg: cfg@26000 { 1274 compatible = "ti,pruss-cfg", "syscon"; 1275 reg = <0x26000 0x200>; 1276 #address-cells = <1>; 1277 #size-cells = <1>; 1278 ranges = <0x0 0x26000 0x2000>; 1279 1280 clocks { 1281 #address-cells = <1>; 1282 #size-cells = <0>; 1283 1284 icssg1_coreclk_mux: coreclk-mux@3c { 1285 reg = <0x3c>; 1286 #clock-cells = <0>; 1287 clocks = <&k3_clks 63 19>, /* icssg1_core_clk */ 1288 <&k3_clks 63 3>; /* icssg1_iclk */ 1289 assigned-clocks = <&icssg1_coreclk_mux>; 1290 assigned-clock-parents = <&k3_clks 63 3>; 1291 }; 1292 1293 icssg1_iepclk_mux: iepclk-mux@30 { 1294 reg = <0x30>; 1295 #clock-cells = <0>; 1296 clocks = <&k3_clks 63 10>, /* icssg1_iep_clk */ 1297 <&icssg1_coreclk_mux>; /* core_clk */ 1298 assigned-clocks = <&icssg1_iepclk_mux>; 1299 assigned-clock-parents = <&icssg1_coreclk_mux>; 1300 }; 1301 }; 1302 }; 1303 1304 icssg1_mii_rt: mii-rt@32000 { 1305 compatible = "ti,pruss-mii", "syscon"; 1306 reg = <0x32000 0x100>; 1307 }; 1308 1309 icssg1_mii_g_rt: mii-g-rt@33000 { 1310 compatible = "ti,pruss-mii-g", "syscon"; 1311 reg = <0x33000 0x1000>; 1312 }; 1313 1314 icssg1_intc: interrupt-controller@20000 { 1315 compatible = "ti,icssg-intc"; 1316 reg = <0x20000 0x2000>; 1317 interrupt-controller; 1318 #interrupt-cells = <3>; 1319 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1320 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 1321 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 1322 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1323 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 1324 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 1325 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 1326 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 1327 interrupt-names = "host_intr0", "host_intr1", 1328 "host_intr2", "host_intr3", 1329 "host_intr4", "host_intr5", 1330 "host_intr6", "host_intr7"; 1331 }; 1332 1333 pru1_0: pru@34000 { 1334 compatible = "ti,am654-pru"; 1335 reg = <0x34000 0x4000>, 1336 <0x22000 0x100>, 1337 <0x22400 0x100>; 1338 reg-names = "iram", "control", "debug"; 1339 firmware-name = "am65x-pru1_0-fw"; 1340 }; 1341 1342 rtu1_0: rtu@4000 { 1343 compatible = "ti,am654-rtu"; 1344 reg = <0x4000 0x2000>, 1345 <0x23000 0x100>, 1346 <0x23400 0x100>; 1347 reg-names = "iram", "control", "debug"; 1348 firmware-name = "am65x-rtu1_0-fw"; 1349 }; 1350 1351 tx_pru1_0: txpru@a000 { 1352 compatible = "ti,am654-tx-pru"; 1353 reg = <0xa000 0x1800>, 1354 <0x25000 0x100>, 1355 <0x25400 0x100>; 1356 reg-names = "iram", "control", "debug"; 1357 firmware-name = "am65x-txpru1_0-fw"; 1358 }; 1359 1360 pru1_1: pru@38000 { 1361 compatible = "ti,am654-pru"; 1362 reg = <0x38000 0x4000>, 1363 <0x24000 0x100>, 1364 <0x24400 0x100>; 1365 reg-names = "iram", "control", "debug"; 1366 firmware-name = "am65x-pru1_1-fw"; 1367 }; 1368 1369 rtu1_1: rtu@6000 { 1370 compatible = "ti,am654-rtu"; 1371 reg = <0x6000 0x2000>, 1372 <0x23800 0x100>, 1373 <0x23c00 0x100>; 1374 reg-names = "iram", "control", "debug"; 1375 firmware-name = "am65x-rtu1_1-fw"; 1376 }; 1377 1378 tx_pru1_1: txpru@c000 { 1379 compatible = "ti,am654-tx-pru"; 1380 reg = <0xc000 0x1800>, 1381 <0x25800 0x100>, 1382 <0x25c00 0x100>; 1383 reg-names = "iram", "control", "debug"; 1384 firmware-name = "am65x-txpru1_1-fw"; 1385 }; 1386 1387 icssg1_mdio: mdio@32400 { 1388 compatible = "ti,davinci_mdio"; 1389 reg = <0x32400 0x100>; 1390 clocks = <&k3_clks 63 3>; 1391 clock-names = "fck"; 1392 #address-cells = <1>; 1393 #size-cells = <0>; 1394 bus_freq = <1000000>; 1395 status = "disabled"; 1396 }; 1397 }; 1398 1399 icssg2: icssg@b200000 { 1400 compatible = "ti,am654-icssg"; 1401 reg = <0x00 0xb200000 0x00 0x80000>; 1402 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 1403 #address-cells = <1>; 1404 #size-cells = <1>; 1405 ranges = <0x0 0x00 0xb200000 0x80000>; 1406 1407 icssg2_mem: memories@0 { 1408 reg = <0x0 0x2000>, 1409 <0x2000 0x2000>, 1410 <0x10000 0x10000>; 1411 reg-names = "dram0", "dram1", 1412 "shrdram2"; 1413 }; 1414 1415 icssg2_cfg: cfg@26000 { 1416 compatible = "ti,pruss-cfg", "syscon"; 1417 reg = <0x26000 0x200>; 1418 #address-cells = <1>; 1419 #size-cells = <1>; 1420 ranges = <0x0 0x26000 0x2000>; 1421 1422 clocks { 1423 #address-cells = <1>; 1424 #size-cells = <0>; 1425 1426 icssg2_coreclk_mux: coreclk-mux@3c { 1427 reg = <0x3c>; 1428 #clock-cells = <0>; 1429 clocks = <&k3_clks 64 19>, /* icssg1_core_clk */ 1430 <&k3_clks 64 3>; /* icssg1_iclk */ 1431 assigned-clocks = <&icssg2_coreclk_mux>; 1432 assigned-clock-parents = <&k3_clks 64 3>; 1433 }; 1434 1435 icssg2_iepclk_mux: iepclk-mux@30 { 1436 reg = <0x30>; 1437 #clock-cells = <0>; 1438 clocks = <&k3_clks 64 10>, /* icssg1_iep_clk */ 1439 <&icssg2_coreclk_mux>; /* core_clk */ 1440 assigned-clocks = <&icssg2_iepclk_mux>; 1441 assigned-clock-parents = <&icssg2_coreclk_mux>; 1442 }; 1443 }; 1444 }; 1445 1446 icssg2_mii_rt: mii-rt@32000 { 1447 compatible = "ti,pruss-mii", "syscon"; 1448 reg = <0x32000 0x100>; 1449 }; 1450 1451 icssg2_mii_g_rt: mii-g-rt@33000 { 1452 compatible = "ti,pruss-mii-g", "syscon"; 1453 reg = <0x33000 0x1000>; 1454 }; 1455 1456 icssg2_intc: interrupt-controller@20000 { 1457 compatible = "ti,icssg-intc"; 1458 reg = <0x20000 0x2000>; 1459 interrupt-controller; 1460 #interrupt-cells = <3>; 1461 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; 1469 interrupt-names = "host_intr0", "host_intr1", 1470 "host_intr2", "host_intr3", 1471 "host_intr4", "host_intr5", 1472 "host_intr6", "host_intr7"; 1473 }; 1474 1475 pru2_0: pru@34000 { 1476 compatible = "ti,am654-pru"; 1477 reg = <0x34000 0x4000>, 1478 <0x22000 0x100>, 1479 <0x22400 0x100>; 1480 reg-names = "iram", "control", "debug"; 1481 firmware-name = "am65x-pru2_0-fw"; 1482 }; 1483 1484 rtu2_0: rtu@4000 { 1485 compatible = "ti,am654-rtu"; 1486 reg = <0x4000 0x2000>, 1487 <0x23000 0x100>, 1488 <0x23400 0x100>; 1489 reg-names = "iram", "control", "debug"; 1490 firmware-name = "am65x-rtu2_0-fw"; 1491 }; 1492 1493 tx_pru2_0: txpru@a000 { 1494 compatible = "ti,am654-tx-pru"; 1495 reg = <0xa000 0x1800>, 1496 <0x25000 0x100>, 1497 <0x25400 0x100>; 1498 reg-names = "iram", "control", "debug"; 1499 firmware-name = "am65x-txpru2_0-fw"; 1500 }; 1501 1502 pru2_1: pru@38000 { 1503 compatible = "ti,am654-pru"; 1504 reg = <0x38000 0x4000>, 1505 <0x24000 0x100>, 1506 <0x24400 0x100>; 1507 reg-names = "iram", "control", "debug"; 1508 firmware-name = "am65x-pru2_1-fw"; 1509 }; 1510 1511 rtu2_1: rtu@6000 { 1512 compatible = "ti,am654-rtu"; 1513 reg = <0x6000 0x2000>, 1514 <0x23800 0x100>, 1515 <0x23c00 0x100>; 1516 reg-names = "iram", "control", "debug"; 1517 firmware-name = "am65x-rtu2_1-fw"; 1518 }; 1519 1520 tx_pru2_1: txpru@c000 { 1521 compatible = "ti,am654-tx-pru"; 1522 reg = <0xc000 0x1800>, 1523 <0x25800 0x100>, 1524 <0x25c00 0x100>; 1525 reg-names = "iram", "control", "debug"; 1526 firmware-name = "am65x-txpru2_1-fw"; 1527 }; 1528 1529 icssg2_mdio: mdio@32400 { 1530 compatible = "ti,davinci_mdio"; 1531 reg = <0x32400 0x100>; 1532 clocks = <&k3_clks 64 3>; 1533 clock-names = "fck"; 1534 #address-cells = <1>; 1535 #size-cells = <0>; 1536 bus_freq = <1000000>; 1537 status = "disabled"; 1538 }; 1539 }; 1540}; 1541