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/kernel/linux/linux-5.10/drivers/nvmem/
Drockchip-otp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip OTP Driver
6 * Author: Finley Xiao <finley.xiao@rock-chips.com>
15 #include <linux/nvmem-provider.h>
22 /* OTP Register Offsets */
35 /* OTP Register bits and masks */
42 #define OTPC_USER_DONE BIT(2)
67 "otp", "apb_pclk", "phy",
74 static int rockchip_otp_reset(struct rockchip_otp *otp) in rockchip_otp_reset() argument
78 ret = reset_control_assert(otp->rst); in rockchip_otp_reset()
[all …]
Dlpc18xx_otp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * NXP LPC18xx/43xx OTP memory NVMEM driver
10 * TODO: add support for writing OTP register via API in boot ROM.
15 #include <linux/nvmem-provider.h>
22 * LPC18xx OTP memory contains 4 banks with 4 32-bit words. Bank 0 starts
27 * Bank 1/2 is generale purpose or AES key storage for secure devices.
44 struct lpc18xx_otp *otp = context; in lpc18xx_otp_read() local
45 unsigned int count = bytes >> 2; in lpc18xx_otp_read()
46 u32 index = offset >> 2; in lpc18xx_otp_read()
50 if (count > (LPC18XX_OTP_SIZE - index)) in lpc18xx_otp_read()
[all …]
Dimx-ocotp.c1 // SPDX-License-Identifier: GPL-2.0-only
12 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc
19 #include <linux/nvmem-provider.h>
27 * OTP Bank0 Word0
30 * of two consecutive OTP words.
105 void __iomem *base = priv->base; in imx_ocotp_wait_for_busy()
107 bm_ctrl_busy = priv->params->ctrl.bm_busy; in imx_ocotp_wait_for_busy()
108 bm_ctrl_error = priv->params->ctrl.bm_error; in imx_ocotp_wait_for_busy()
112 for (count = 10000; count >= 0; count--) { in imx_ocotp_wait_for_busy()
122 * - A write is performed to a shadow register during a shadow in imx_ocotp_wait_for_busy()
[all …]
/kernel/linux/linux-6.6/drivers/nvmem/
Dlpc18xx_otp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * NXP LPC18xx/43xx OTP memory NVMEM driver
10 * TODO: add support for writing OTP register via API in boot ROM.
15 #include <linux/nvmem-provider.h>
21 * LPC18xx OTP memory contains 4 banks with 4 32-bit words. Bank 0 starts
26 * Bank 1/2 is generale purpose or AES key storage for secure devices.
43 struct lpc18xx_otp *otp = context; in lpc18xx_otp_read() local
44 unsigned int count = bytes >> 2; in lpc18xx_otp_read()
45 u32 index = offset >> 2; in lpc18xx_otp_read()
49 if (count > (LPC18XX_OTP_SIZE - index)) in lpc18xx_otp_read()
[all …]
Drockchip-otp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip OTP Driver
6 * Author: Finley Xiao <finley.xiao@rock-chips.com>
15 #include <linux/nvmem-provider.h>
22 /* OTP Register Offsets */
35 /* OTP Register bits and masks */
42 #define OTPC_USER_DONE BIT(2)
85 static int rockchip_otp_reset(struct rockchip_otp *otp) in rockchip_otp_reset() argument
89 ret = reset_control_assert(otp->rst); in rockchip_otp_reset()
91 dev_err(otp->dev, "failed to assert otp phy %d\n", ret); in rockchip_otp_reset()
[all …]
Dsunplus-ocotp.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/nvmem-provider.h>
21 * OTP memory
47 #define OTP_READ BIT(2)
55 #define OTP_LOAD_SECURE_DONE_MASK ~BIT(2)
78 static int sp_otp_read_real(struct sp_ocotp_priv *otp, int addr, char *value) in sp_otp_read_real() argument
94 writel(readl(otp->base[OTPRX] + OTP_STATUS) & OTP_READ_DONE_MASK & in sp_otp_read_real()
95 OTP_LOAD_SECURE_DONE_MASK, otp->base[OTPRX] + OTP_STATUS); in sp_otp_read_real()
96 writel(addr, otp->base[OTPRX] + OTP_READ_ADDRESS); in sp_otp_read_real()
97 writel(readl(otp->base[OTPRX] + OTP_CONTROL_2) | OTP_READ, in sp_otp_read_real()
[all …]
Dlan9662-otpc.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/nvmem-provider.h>
24 #define OTP_OTP_PASS_FAIL_OTP_WRITE_PROHIBITED BIT(2)
47 static int lan9662_otp_power(struct lan9662_otp *otp, bool up) in lan9662_otp_power() argument
49 void __iomem *pwrdn = OTP_OTP_PWR_DN(otp->base); in lan9662_otp_power()
53 if (lan9662_otp_wait_flag_clear(OTP_OTP_STATUS(otp->base), in lan9662_otp_power()
55 return -ETIMEDOUT; in lan9662_otp_power()
63 static int lan9662_otp_execute(struct lan9662_otp *otp) in lan9662_otp_execute() argument
65 if (lan9662_otp_wait_flag_clear(OTP_OTP_CMD_GO(otp->base), in lan9662_otp_execute()
67 return -ETIMEDOUT; in lan9662_otp_execute()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
37 calibration data required for the PCIe or the USB-C PHY.
40 be called nvmem-apple-efuses.
43 tristate "Broadcom On-Chip OTP Controller support"
48 Say y here to enable read/write access to the Broadcom OTP
52 will be called nvmem-bcm-ocotp.
72 will be called nvmem-imx-iim.
75 tristate "i.MX 6/7/8 On-Chip OTP Controller support"
79 This is a driver for the On-Chip OTP Controller (OCOTP) available on
80 i.MX6 SoCs, providing access to 4 Kbits of one-time programmable
[all …]
Dimx-ocotp.c1 // SPDX-License-Identifier: GPL-2.0-only
14 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc
21 #include <linux/nvmem-provider.h>
29 * OTP Bank0 Word0
32 * of two consecutive OTP words.
107 void __iomem *base = priv->base; in imx_ocotp_wait_for_busy()
109 bm_ctrl_busy = priv->params->ctrl.bm_busy; in imx_ocotp_wait_for_busy()
110 bm_ctrl_error = priv->params->ctrl.bm_error; in imx_ocotp_wait_for_busy()
114 for (count = 10000; count >= 0; count--) { in imx_ocotp_wait_for_busy()
124 * - A write is performed to a shadow register during a shadow in imx_ocotp_wait_for_busy()
[all …]
Dstm32-romem.c1 // SPDX-License-Identifier: GPL-2.0
3 * STM32 Factory-programmed memory read access driver
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
9 #include <linux/arm-smccc.h>
12 #include <linux/nvmem-provider.h>
16 #include "stm32-bsec-optee-ta.h"
18 /* BSEC secure service access from non-secure */
49 *buf8++ = readb_relaxed(priv->base + i); in stm32_romem_read()
54 static int stm32_bsec_smc(u8 op, u32 otp, u32 data, u32 *result) in stm32_bsec_smc() argument
59 arm_smccc_smc(STM32_SMC_BSEC, op, otp, data, 0, 0, 0, 0, &res); in stm32_bsec_smc()
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/nvmem/
Drockchip,otp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/rockchip,otp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip internal OTP (One Time Programmable) memory
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,px30-otp
16 - rockchip,rk3308-otp
17 - rockchip,rk3588-otp
26 clock-names:
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Dnintendo-otp.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/nvmem/nintendo-otp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nintendo Wii and Wii U OTP
10 This binding represents the OTP memory as found on a Nintendo Wii or Wii U,
11 which contains common and per-console keys, signatures and related data
14 See https://wiiubrew.org/wiki/Hardware/OTP
17 - Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
20 - $ref: nvmem.yaml#
[all …]
Dst,stm32-romem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/st,stm32-romem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Factory-programmed data
10 This represents STM32 Factory-programmed read only non-volatile area: locked
11 flash, OTP, read-only HW regs... This contains various information such as:
16 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
19 - $ref: nvmem.yaml#
24 - st,stm32f4-otp
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/kernel/linux/linux-6.6/drivers/net/wireless/intel/iwlwifi/
Diwl-eeprom-read.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2005-2014, 2018-2019, 2021 Intel Corporation
9 #include "iwl-drv.h"
10 #include "iwl-debug.h"
11 #include "iwl-eeprom-read.h"
12 #include "iwl-io.h"
13 #include "iwl-prph.h"
14 #include "iwl-csr.h"
22 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
52 IWL_DEBUG_EEPROM(trans->dev, in iwl_eeprom_acquire_semaphore()
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/kernel/linux/linux-5.10/drivers/mfd/
Dab3100-otp.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2007-2009 ST-Ericsson AB
6 * Driver to read out OTP from the AB3100 Mixed-signal circuit
19 /* The OTP registers */
33 * @locked: whether the OTP is locked, after locking, no more bits
35 * to change bits from 1->0.
36 * @freq: clocking frequency for the OTP, this frequency is either
62 static int __init ab3100_otp_read(struct ab3100_otp *otp) in ab3100_otp_read() argument
68 err = abx500_get_register_interruptible(otp->dev, 0, in ab3100_otp_read()
71 dev_err(otp->dev, "unable to read OTPP register\n"); in ab3100_otp_read()
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/intel/iwlwifi/
Diwl-eeprom-read.c8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2018 - 2019 Intel Corporation
12 * it under the terms of version 2 of the GNU General Public License as
25 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
29 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
30 * Copyright(c) 2018 - 2019 Intel Corporation
63 #include "iwl-drv.h"
64 #include "iwl-debug.h"
65 #include "iwl-eeprom-read.h"
66 #include "iwl-io.h"
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/kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/mt7615/
Deeprom.c1 // SPDX-License-Identifier: ISC
25 return -ETIMEDOUT; in mt7615_efuse_read()
27 udelay(2); in mt7615_efuse_read()
50 if (is_mt7663(&dev->mt76)) in mt7615_efuse_init()
57 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, len, GFP_KERNEL); in mt7615_efuse_init()
58 dev->mt76.otp.size = len; in mt7615_efuse_init()
59 if (!dev->mt76.otp.data) in mt7615_efuse_init()
60 return -ENOMEM; in mt7615_efuse_init()
62 buf = dev->mt76.otp.data; in mt7615_efuse_init()
80 ret = mt76_eeprom_init(&dev->mt76, MT7615_EEPROM_FULL_SIZE); in mt7615_eeprom_load()
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7615/
Deeprom.c1 // SPDX-License-Identifier: ISC
25 return -ETIMEDOUT; in mt7615_efuse_read()
27 udelay(2); in mt7615_efuse_read()
54 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, len, GFP_KERNEL); in mt7615_efuse_init()
55 dev->mt76.otp.size = len; in mt7615_efuse_init()
56 if (!dev->mt76.otp.data) in mt7615_efuse_init()
57 return -ENOMEM; in mt7615_efuse_init()
59 buf = dev->mt76.otp.data; in mt7615_efuse_init()
75 ret = mt76_eeprom_init(&dev->mt76, MT7615_EEPROM_FULL_SIZE); in mt7615_eeprom_load()
84 u16 val = get_unaligned_le16(dev->eeprom.data); in mt7615_check_eeprom()
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mtd/
Dmtd.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
19 User-defined MTD device name. Can be used to assign user friendly
24 '#address-cells':
27 '#size-cells':
34 - compatible
37 "@[0-9a-f]+$":
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/kernel/linux/linux-6.6/drivers/mtd/spi-nor/
Dotp.c1 // SPDX-License-Identifier: GPL-2.0
3 * OTP support for SPI NOR flashes
10 #include <linux/mtd/spi-nor.h>
14 #define spi_nor_otp_region_len(nor) ((nor)->params->otp.org->len)
15 #define spi_nor_otp_n_regions(nor) ((nor)->params->otp.org->n_regions)
18 * spi_nor_otp_read_secr() - read security register
27 * an one-time-programmable memory area, consisting of multiple bytes (usually
28 * 256). Thus one "security register" maps to one OTP region.
34 * Return: number of bytes read successfully, -errno otherwise
43 read_opcode = nor->read_opcode; in spi_nor_otp_read_secr()
[all …]
/kernel/linux/linux-5.10/include/linux/mfd/wm831x/
Dotp.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/linux/mfd/wm831x/otp.h -- OTP interface for WM831x
17 * R30720 (0x7800) - Unique ID 1
19 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
20 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
21 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
24 * R30721 (0x7801) - Unique ID 2
26 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
27 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
28 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
[all …]
/kernel/linux/linux-6.6/include/linux/mfd/wm831x/
Dotp.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/linux/mfd/wm831x/otp.h -- OTP interface for WM831x
17 * R30720 (0x7800) - Unique ID 1
19 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
20 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
21 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
24 * R30721 (0x7801) - Unique ID 2
26 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
27 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
28 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
[all …]
/kernel/linux/linux-5.10/drivers/mtd/nand/onenand/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
43 bool "OneNAND OTP Support"
46 a One-Time Programmable Block memory area.
47 Also, 1st Block of NAND Flash Array can be used as OTP.
49 The OTP block can be read, programmed and locked using the same
51 OTP block cannot be erased.
53 OTP block is fully-guaranteed to be a valid block.
56 bool "OneNAND 2X program support"
58 The 2X Program is an extension of Program Operation.
59 Since the device is equipped with two DataRAMs, and two-plane NAND
/kernel/linux/linux-6.6/drivers/mtd/nand/onenand/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
45 bool "OneNAND OTP Support"
48 a One-Time Programmable Block memory area.
49 Also, 1st Block of NAND Flash Array can be used as OTP.
51 The OTP block can be read, programmed and locked using the same
53 OTP block cannot be erased.
55 OTP block is fully-guaranteed to be a valid block.
58 bool "OneNAND 2X program support"
60 The 2X Program is an extension of Program Operation.
61 Since the device is equipped with two DataRAMs, and two-plane NAND
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/nvmem/
Dst,stm32-romem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/st,stm32-romem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Factory-programmed data bindings
10 This represents STM32 Factory-programmed read only non-volatile area: locked
11 flash, OTP, read-only HW regs... This contains various information such as:
16 - Fabrice Gasnier <fabrice.gasnier@st.com>
19 - $ref: "nvmem.yaml#"
24 - st,stm32f4-otp
[all …]

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